2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
83 * Manages physical address maps.
85 * In addition to hardware address maps, this
86 * module is called upon to provide software-use-only
87 * maps which may or may not be stored in the same
88 * form as hardware maps. These pseudo-maps are
89 * used to store intermediate results from copy
90 * operations to and from address spaces.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
108 #include "opt_pmap.h"
111 #include <sys/param.h>
112 #include <sys/systm.h>
113 #include <sys/kernel.h>
115 #include <sys/lock.h>
116 #include <sys/malloc.h>
117 #include <sys/mman.h>
118 #include <sys/mutex.h>
119 #include <sys/proc.h>
121 #include <sys/vmmeter.h>
122 #include <sys/sched.h>
123 #include <sys/sysctl.h>
127 #include <sys/cpuset.h>
131 #include <vm/vm_param.h>
132 #include <vm/vm_kern.h>
133 #include <vm/vm_page.h>
134 #include <vm/vm_map.h>
135 #include <vm/vm_object.h>
136 #include <vm/vm_extern.h>
137 #include <vm/vm_pageout.h>
138 #include <vm/vm_pager.h>
139 #include <vm/vm_reserv.h>
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
148 #include <machine/smp.h>
151 #if !defined(DIAGNOSTIC)
152 #ifdef __GNUC_GNU_INLINE__
153 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
155 #define PMAP_INLINE extern inline
162 #define PV_STAT(x) do { x ; } while (0)
164 #define PV_STAT(x) do { } while (0)
167 #define pa_index(pa) ((pa) >> PDRSHIFT)
168 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
170 struct pmap kernel_pmap_store;
172 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
173 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
176 static vm_paddr_t dmaplimit;
177 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
180 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
182 static int pat_works = 1;
183 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
184 "Is page attribute table fully functional?");
186 static int pg_ps_enabled = 1;
187 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
188 "Are large page mappings enabled?");
190 #define PAT_INDEX_SIZE 8
191 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
193 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
194 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
195 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
196 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
198 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
199 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
202 * Data for the pv entry allocation mechanism
204 static int pv_entry_count;
205 static struct md_page *pv_table;
208 * All those kernel PT submaps that BSD is so fond of
210 pt_entry_t *CMAP1 = 0;
216 static caddr_t crashdumpmap;
218 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
219 static pv_entry_t get_pv_entry(pmap_t locked_pmap, boolean_t try);
220 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
221 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
222 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
223 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
224 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
226 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
228 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
229 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
230 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
232 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
234 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
235 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
236 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
237 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
238 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
239 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
240 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
241 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
242 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
243 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
244 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
246 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
247 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
249 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq,
250 vm_offset_t sva, pd_entry_t ptepde, vm_page_t *free);
251 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
252 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
254 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
256 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
257 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
259 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
261 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
263 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va, int flags);
264 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
266 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, int flags);
267 static int _pmap_unwire_pte_hold(pmap_t pmap, vm_offset_t va, vm_page_t m,
269 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, vm_page_t *);
270 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
272 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
273 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
276 * Move the kernel virtual free pointer to the next
277 * 2MB. This is used to help improve performance
278 * by using a large (2MB) page for much of the kernel
279 * (.text, .data, .bss)
282 pmap_kmem_choose(vm_offset_t addr)
284 vm_offset_t newaddr = addr;
286 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
290 /********************/
291 /* Inline functions */
292 /********************/
294 /* Return a non-clipped PD index for a given VA */
295 static __inline vm_pindex_t
296 pmap_pde_pindex(vm_offset_t va)
298 return (va >> PDRSHIFT);
302 /* Return various clipped indexes for a given VA */
303 static __inline vm_pindex_t
304 pmap_pte_index(vm_offset_t va)
307 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
310 static __inline vm_pindex_t
311 pmap_pde_index(vm_offset_t va)
314 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
317 static __inline vm_pindex_t
318 pmap_pdpe_index(vm_offset_t va)
321 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
324 static __inline vm_pindex_t
325 pmap_pml4e_index(vm_offset_t va)
328 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
331 /* Return a pointer to the PML4 slot that corresponds to a VA */
332 static __inline pml4_entry_t *
333 pmap_pml4e(pmap_t pmap, vm_offset_t va)
336 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
339 /* Return a pointer to the PDP slot that corresponds to a VA */
340 static __inline pdp_entry_t *
341 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
345 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
346 return (&pdpe[pmap_pdpe_index(va)]);
349 /* Return a pointer to the PDP slot that corresponds to a VA */
350 static __inline pdp_entry_t *
351 pmap_pdpe(pmap_t pmap, vm_offset_t va)
355 pml4e = pmap_pml4e(pmap, va);
356 if ((*pml4e & PG_V) == 0)
358 return (pmap_pml4e_to_pdpe(pml4e, va));
361 /* Return a pointer to the PD slot that corresponds to a VA */
362 static __inline pd_entry_t *
363 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
367 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
368 return (&pde[pmap_pde_index(va)]);
371 /* Return a pointer to the PD slot that corresponds to a VA */
372 static __inline pd_entry_t *
373 pmap_pde(pmap_t pmap, vm_offset_t va)
377 pdpe = pmap_pdpe(pmap, va);
378 if (pdpe == NULL || (*pdpe & PG_V) == 0)
380 return (pmap_pdpe_to_pde(pdpe, va));
383 /* Return a pointer to the PT slot that corresponds to a VA */
384 static __inline pt_entry_t *
385 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
389 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
390 return (&pte[pmap_pte_index(va)]);
393 /* Return a pointer to the PT slot that corresponds to a VA */
394 static __inline pt_entry_t *
395 pmap_pte(pmap_t pmap, vm_offset_t va)
399 pde = pmap_pde(pmap, va);
400 if (pde == NULL || (*pde & PG_V) == 0)
402 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
403 return ((pt_entry_t *)pde);
404 return (pmap_pde_to_pte(pde, va));
408 pmap_resident_count_inc(pmap_t pmap, int count)
411 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
412 pmap->pm_stats.resident_count += count;
416 pmap_resident_count_dec(pmap_t pmap, int count)
419 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
420 pmap->pm_stats.resident_count -= count;
423 PMAP_INLINE pt_entry_t *
424 vtopte(vm_offset_t va)
426 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
428 return (PTmap + ((va >> PAGE_SHIFT) & mask));
431 static __inline pd_entry_t *
432 vtopde(vm_offset_t va)
434 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
436 return (PDmap + ((va >> PDRSHIFT) & mask));
440 allocpages(vm_paddr_t *firstaddr, int n)
445 bzero((void *)ret, n * PAGE_SIZE);
446 *firstaddr += n * PAGE_SIZE;
450 CTASSERT(powerof2(NDMPML4E));
453 create_pagetables(vm_paddr_t *firstaddr)
458 KPTphys = allocpages(firstaddr, NKPT);
459 KPML4phys = allocpages(firstaddr, 1);
460 KPDPphys = allocpages(firstaddr, NKPML4E);
461 KPDphys = allocpages(firstaddr, NKPDPE);
463 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
464 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
466 DMPDPphys = allocpages(firstaddr, NDMPML4E);
468 if ((amd_feature & AMDID_PAGE1GB) != 0)
469 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
471 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
472 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
474 /* Fill in the underlying page table pages */
475 /* Read-only from zero to physfree */
476 /* XXX not fully used, underneath 2M pages */
477 for (i = 0; (i << PAGE_SHIFT) < *firstaddr; i++) {
478 ((pt_entry_t *)KPTphys)[i] = i << PAGE_SHIFT;
479 ((pt_entry_t *)KPTphys)[i] |= PG_RW | PG_V | PG_G;
482 /* Now map the page tables at their location within PTmap */
483 for (i = 0; i < NKPT; i++) {
484 ((pd_entry_t *)KPDphys)[i] = KPTphys + (i << PAGE_SHIFT);
485 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V;
488 /* Map from zero to end of allocations under 2M pages */
489 /* This replaces some of the KPTphys entries above */
490 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++) {
491 ((pd_entry_t *)KPDphys)[i] = i << PDRSHIFT;
492 ((pd_entry_t *)KPDphys)[i] |= PG_RW | PG_V | PG_PS | PG_G;
495 /* And connect up the PD to the PDP */
496 for (i = 0; i < NKPDPE; i++) {
497 ((pdp_entry_t *)KPDPphys)[i + KPDPI] = KPDphys +
499 ((pdp_entry_t *)KPDPphys)[i + KPDPI] |= PG_RW | PG_V | PG_U;
503 * Now, set up the direct map region using 2MB and/or 1GB pages. If
504 * the end of physical memory is not aligned to a 1GB page boundary,
505 * then the residual physical memory is mapped with 2MB pages. Later,
506 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
507 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
508 * that are partially used.
510 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
511 ((pd_entry_t *)DMPDphys)[j] = (vm_paddr_t)i << PDRSHIFT;
512 /* Preset PG_M and PG_A because demotion expects it. */
513 ((pd_entry_t *)DMPDphys)[j] |= PG_RW | PG_V | PG_PS | PG_G |
516 for (i = 0; i < ndm1g; i++) {
517 ((pdp_entry_t *)DMPDPphys)[i] = (vm_paddr_t)i << PDPSHIFT;
518 /* Preset PG_M and PG_A because demotion expects it. */
519 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_PS | PG_G |
522 for (j = 0; i < ndmpdp; i++, j++) {
523 ((pdp_entry_t *)DMPDPphys)[i] = DMPDphys + (j << PAGE_SHIFT);
524 ((pdp_entry_t *)DMPDPphys)[i] |= PG_RW | PG_V | PG_U;
527 /* And recursively map PML4 to itself in order to get PTmap */
528 ((pdp_entry_t *)KPML4phys)[PML4PML4I] = KPML4phys;
529 ((pdp_entry_t *)KPML4phys)[PML4PML4I] |= PG_RW | PG_V | PG_U;
531 /* Connect the Direct Map slot(s) up to the PML4. */
532 for (i = 0; i < NDMPML4E; i++) {
533 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] = DMPDPphys +
535 ((pdp_entry_t *)KPML4phys)[DMPML4I + i] |= PG_RW | PG_V | PG_U;
538 /* Connect the KVA slot up to the PML4 */
539 ((pdp_entry_t *)KPML4phys)[KPML4I] = KPDPphys;
540 ((pdp_entry_t *)KPML4phys)[KPML4I] |= PG_RW | PG_V | PG_U;
544 * Bootstrap the system enough to run with virtual memory.
546 * On amd64 this is called after mapping has already been enabled
547 * and just syncs the pmap module with what has already been done.
548 * [We can't call it easily with mapping off since the kernel is not
549 * mapped with PA == VA, hence we would have to relocate every address
550 * from the linked base (virtual) address "KERNBASE" to the actual
551 * (physical) address starting relative to 0]
554 pmap_bootstrap(vm_paddr_t *firstaddr)
557 pt_entry_t *pte, *unused;
560 * Create an initial set of page tables to run the kernel in.
562 create_pagetables(firstaddr);
564 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
565 virtual_avail = pmap_kmem_choose(virtual_avail);
567 virtual_end = VM_MAX_KERNEL_ADDRESS;
570 /* XXX do %cr0 as well */
571 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
575 * Initialize the kernel pmap (which is statically allocated).
577 PMAP_LOCK_INIT(kernel_pmap);
578 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
579 kernel_pmap->pm_root = NULL;
580 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
581 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
584 * Reserve some special page table entries/VA space for temporary
587 #define SYSMAP(c, p, v, n) \
588 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
594 * CMAP1 is only used for the memory test.
596 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
601 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
605 /* Initialize the PAT MSR. */
615 int pat_table[PAT_INDEX_SIZE];
620 /* Bail if this CPU doesn't implement PAT. */
621 if ((cpu_feature & CPUID_PAT) == 0)
624 /* Set default PAT index table. */
625 for (i = 0; i < PAT_INDEX_SIZE; i++)
627 pat_table[PAT_WRITE_BACK] = 0;
628 pat_table[PAT_WRITE_THROUGH] = 1;
629 pat_table[PAT_UNCACHEABLE] = 3;
630 pat_table[PAT_WRITE_COMBINING] = 3;
631 pat_table[PAT_WRITE_PROTECTED] = 3;
632 pat_table[PAT_UNCACHED] = 3;
634 /* Initialize default PAT entries. */
635 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
636 PAT_VALUE(1, PAT_WRITE_THROUGH) |
637 PAT_VALUE(2, PAT_UNCACHED) |
638 PAT_VALUE(3, PAT_UNCACHEABLE) |
639 PAT_VALUE(4, PAT_WRITE_BACK) |
640 PAT_VALUE(5, PAT_WRITE_THROUGH) |
641 PAT_VALUE(6, PAT_UNCACHED) |
642 PAT_VALUE(7, PAT_UNCACHEABLE);
646 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
647 * Program 5 and 6 as WP and WC.
648 * Leave 4 and 7 as WB and UC.
650 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
651 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
652 PAT_VALUE(6, PAT_WRITE_COMBINING);
653 pat_table[PAT_UNCACHED] = 2;
654 pat_table[PAT_WRITE_PROTECTED] = 5;
655 pat_table[PAT_WRITE_COMBINING] = 6;
658 * Just replace PAT Index 2 with WC instead of UC-.
660 pat_msr &= ~PAT_MASK(2);
661 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
662 pat_table[PAT_WRITE_COMBINING] = 2;
667 load_cr4(cr4 & ~CR4_PGE);
669 /* Disable caches (CD = 1, NW = 0). */
671 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
673 /* Flushes caches and TLBs. */
677 /* Update PAT and index table. */
678 wrmsr(MSR_PAT, pat_msr);
679 for (i = 0; i < PAT_INDEX_SIZE; i++)
680 pat_index[i] = pat_table[i];
682 /* Flush caches and TLBs again. */
686 /* Restore caches and PGE. */
692 * Initialize a vm_page's machine-dependent fields.
695 pmap_page_init(vm_page_t m)
698 TAILQ_INIT(&m->md.pv_list);
699 m->md.pat_mode = PAT_WRITE_BACK;
703 * Initialize the pmap module.
704 * Called by vm_init, to initialize any structures that the pmap
705 * system needs to map virtual memory.
715 * Initialize the vm page array entries for the kernel pmap's
718 for (i = 0; i < NKPT; i++) {
719 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
720 KASSERT(mpte >= vm_page_array &&
721 mpte < &vm_page_array[vm_page_array_size],
722 ("pmap_init: page table page is out of range"));
723 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
724 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
728 * If the kernel is running in a virtual machine on an AMD Family 10h
729 * processor, then it must assume that MCA is enabled by the virtual
732 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
733 CPUID_TO_FAMILY(cpu_id) == 0x10)
734 workaround_erratum383 = 1;
737 * Are large page mappings enabled?
739 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
741 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
742 ("pmap_init: can't assign to pagesizes[1]"));
743 pagesizes[1] = NBPDR;
747 * Calculate the size of the pv head table for superpages.
749 for (i = 0; phys_avail[i + 1]; i += 2);
750 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
753 * Allocate memory for the pv head table for superpages.
755 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
757 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
758 for (i = 0; i < pv_npg; i++)
759 TAILQ_INIT(&pv_table[i].pv_list);
762 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
763 "2MB page mapping counters");
765 static u_long pmap_pde_demotions;
766 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
767 &pmap_pde_demotions, 0, "2MB page demotions");
769 static u_long pmap_pde_mappings;
770 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
771 &pmap_pde_mappings, 0, "2MB page mappings");
773 static u_long pmap_pde_p_failures;
774 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
775 &pmap_pde_p_failures, 0, "2MB page promotion failures");
777 static u_long pmap_pde_promotions;
778 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
779 &pmap_pde_promotions, 0, "2MB page promotions");
781 SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
782 "1GB page mapping counters");
784 static u_long pmap_pdpe_demotions;
785 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
786 &pmap_pdpe_demotions, 0, "1GB page demotions");
788 /***************************************************
789 * Low level helper routines.....
790 ***************************************************/
793 * Determine the appropriate bits to set in a PTE or PDE for a specified
797 pmap_cache_bits(int mode, boolean_t is_pde)
799 int cache_bits, pat_flag, pat_idx;
801 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
802 panic("Unknown caching mode %d\n", mode);
804 /* The PAT bit is different for PTE's and PDE's. */
805 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
807 /* Map the caching mode to a PAT index. */
808 pat_idx = pat_index[mode];
810 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
813 cache_bits |= pat_flag;
815 cache_bits |= PG_NC_PCD;
817 cache_bits |= PG_NC_PWT;
822 * After changing the page size for the specified virtual address in the page
823 * table, flush the corresponding entries from the processor's TLB. Only the
824 * calling processor's TLB is affected.
826 * The calling thread must be pinned to a processor.
829 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
833 if ((newpde & PG_PS) == 0)
834 /* Demotion: flush a specific 2MB page mapping. */
836 else if ((newpde & PG_G) == 0)
838 * Promotion: flush every 4KB page mapping from the TLB
839 * because there are too many to flush individually.
844 * Promotion: flush every 4KB page mapping from the TLB,
845 * including any global (PG_G) mappings.
848 load_cr4(cr4 & ~CR4_PGE);
850 * Although preemption at this point could be detrimental to
851 * performance, it would not lead to an error. PG_G is simply
852 * ignored if CR4.PGE is clear. Moreover, in case this block
853 * is re-entered, the load_cr4() either above or below will
854 * modify CR4.PGE flushing the TLB.
856 load_cr4(cr4 | CR4_PGE);
861 * For SMP, these functions have to use the IPI mechanism for coherence.
863 * N.B.: Before calling any of the following TLB invalidation functions,
864 * the calling processor must ensure that all stores updating a non-
865 * kernel page table are globally performed. Otherwise, another
866 * processor could cache an old, pre-update entry without being
867 * invalidated. This can happen one of two ways: (1) The pmap becomes
868 * active on another processor after its pm_active field is checked by
869 * one of the following functions but before a store updating the page
870 * table is globally performed. (2) The pmap becomes active on another
871 * processor before its pm_active field is checked but due to
872 * speculative loads one of the following functions stills reads the
873 * pmap as inactive on the other processor.
875 * The kernel page table is exempt because its pm_active field is
876 * immutable. The kernel page table is always active on every
880 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
886 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
890 cpuid = PCPU_GET(cpuid);
891 other_cpus = all_cpus;
892 CPU_CLR(cpuid, &other_cpus);
893 if (CPU_ISSET(cpuid, &pmap->pm_active))
895 CPU_AND(&other_cpus, &pmap->pm_active);
896 if (!CPU_EMPTY(&other_cpus))
897 smp_masked_invlpg(other_cpus, va);
903 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
910 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
911 for (addr = sva; addr < eva; addr += PAGE_SIZE)
913 smp_invlpg_range(sva, eva);
915 cpuid = PCPU_GET(cpuid);
916 other_cpus = all_cpus;
917 CPU_CLR(cpuid, &other_cpus);
918 if (CPU_ISSET(cpuid, &pmap->pm_active))
919 for (addr = sva; addr < eva; addr += PAGE_SIZE)
921 CPU_AND(&other_cpus, &pmap->pm_active);
922 if (!CPU_EMPTY(&other_cpus))
923 smp_masked_invlpg_range(other_cpus, sva, eva);
929 pmap_invalidate_all(pmap_t pmap)
935 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
939 cpuid = PCPU_GET(cpuid);
940 other_cpus = all_cpus;
941 CPU_CLR(cpuid, &other_cpus);
942 if (CPU_ISSET(cpuid, &pmap->pm_active))
944 CPU_AND(&other_cpus, &pmap->pm_active);
945 if (!CPU_EMPTY(&other_cpus))
946 smp_masked_invltlb(other_cpus);
952 pmap_invalidate_cache(void)
962 cpuset_t invalidate; /* processors that invalidate their TLB */
966 u_int store; /* processor that updates the PDE */
970 pmap_update_pde_action(void *arg)
972 struct pde_action *act = arg;
974 if (act->store == PCPU_GET(cpuid))
975 pde_store(act->pde, act->newpde);
979 pmap_update_pde_teardown(void *arg)
981 struct pde_action *act = arg;
983 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
984 pmap_update_pde_invalidate(act->va, act->newpde);
988 * Change the page size for the specified virtual address in a way that
989 * prevents any possibility of the TLB ever having two entries that map the
990 * same virtual address using different page sizes. This is the recommended
991 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
992 * machine check exception for a TLB state that is improperly diagnosed as a
996 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
998 struct pde_action act;
999 cpuset_t active, other_cpus;
1003 cpuid = PCPU_GET(cpuid);
1004 other_cpus = all_cpus;
1005 CPU_CLR(cpuid, &other_cpus);
1006 if (pmap == kernel_pmap)
1009 active = pmap->pm_active;
1010 if (CPU_OVERLAP(&active, &other_cpus)) {
1012 act.invalidate = active;
1015 act.newpde = newpde;
1016 CPU_SET(cpuid, &active);
1017 smp_rendezvous_cpus(active,
1018 smp_no_rendevous_barrier, pmap_update_pde_action,
1019 pmap_update_pde_teardown, &act);
1021 pde_store(pde, newpde);
1022 if (CPU_ISSET(cpuid, &active))
1023 pmap_update_pde_invalidate(va, newpde);
1029 * Normal, non-SMP, invalidation functions.
1030 * We inline these within pmap.c for speed.
1033 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1036 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1041 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1045 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1046 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1051 pmap_invalidate_all(pmap_t pmap)
1054 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1059 pmap_invalidate_cache(void)
1066 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1069 pde_store(pde, newpde);
1070 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1071 pmap_update_pde_invalidate(va, newpde);
1075 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1078 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1081 KASSERT((sva & PAGE_MASK) == 0,
1082 ("pmap_invalidate_cache_range: sva not page-aligned"));
1083 KASSERT((eva & PAGE_MASK) == 0,
1084 ("pmap_invalidate_cache_range: eva not page-aligned"));
1086 if (cpu_feature & CPUID_SS)
1087 ; /* If "Self Snoop" is supported, do nothing. */
1088 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1089 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1092 * Otherwise, do per-cache line flush. Use the mfence
1093 * instruction to insure that previous stores are
1094 * included in the write-back. The processor
1095 * propagates flush to other processors in the cache
1099 for (; sva < eva; sva += cpu_clflush_line_size)
1105 * No targeted cache flush methods are supported by CPU,
1106 * or the supplied range is bigger than 2MB.
1107 * Globally invalidate cache.
1109 pmap_invalidate_cache();
1114 * Remove the specified set of pages from the data and instruction caches.
1116 * In contrast to pmap_invalidate_cache_range(), this function does not
1117 * rely on the CPU's self-snoop feature, because it is intended for use
1118 * when moving pages into a different cache domain.
1121 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1123 vm_offset_t daddr, eva;
1126 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1127 (cpu_feature & CPUID_CLFSH) == 0)
1128 pmap_invalidate_cache();
1131 for (i = 0; i < count; i++) {
1132 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1133 eva = daddr + PAGE_SIZE;
1134 for (; daddr < eva; daddr += cpu_clflush_line_size)
1142 * Are we current address space or kernel?
1145 pmap_is_current(pmap_t pmap)
1147 return (pmap == kernel_pmap ||
1148 (pmap->pm_pml4[PML4PML4I] & PG_FRAME) == (PML4pml4e[0] & PG_FRAME));
1152 * Routine: pmap_extract
1154 * Extract the physical page address associated
1155 * with the given map/virtual_address pair.
1158 pmap_extract(pmap_t pmap, vm_offset_t va)
1167 pdpe = pmap_pdpe(pmap, va);
1168 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1169 if ((*pdpe & PG_PS) != 0)
1170 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1172 pde = pmap_pdpe_to_pde(pdpe, va);
1173 if ((*pde & PG_V) != 0) {
1174 if ((*pde & PG_PS) != 0) {
1175 pa = (*pde & PG_PS_FRAME) |
1178 pte = pmap_pde_to_pte(pde, va);
1179 pa = (*pte & PG_FRAME) |
1190 * Routine: pmap_extract_and_hold
1192 * Atomically extract and hold the physical page
1193 * with the given pmap and virtual address pair
1194 * if that mapping permits the given protection.
1197 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1199 pd_entry_t pde, *pdep;
1208 pdep = pmap_pde(pmap, va);
1209 if (pdep != NULL && (pde = *pdep)) {
1211 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1212 if (vm_page_pa_tryrelock(pmap, (pde &
1213 PG_PS_FRAME) | (va & PDRMASK), &pa))
1215 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1220 pte = *pmap_pde_to_pte(pdep, va);
1222 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1223 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1226 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1237 pmap_kextract(vm_offset_t va)
1242 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1243 pa = DMAP_TO_PHYS(va);
1247 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1250 * Beware of a concurrent promotion that changes the
1251 * PDE at this point! For example, vtopte() must not
1252 * be used to access the PTE because it would use the
1253 * new PDE. It is, however, safe to use the old PDE
1254 * because the page table page is preserved by the
1257 pa = *pmap_pde_to_pte(&pde, va);
1258 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1264 /***************************************************
1265 * Low level mapping routines.....
1266 ***************************************************/
1269 * Add a wired page to the kva.
1270 * Note: not SMP coherent.
1273 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1278 pte_store(pte, pa | PG_RW | PG_V | PG_G);
1281 static __inline void
1282 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1287 pte_store(pte, pa | PG_RW | PG_V | PG_G | pmap_cache_bits(mode, 0));
1291 * Remove a page from the kernel pagetables.
1292 * Note: not SMP coherent.
1295 pmap_kremove(vm_offset_t va)
1304 * Used to map a range of physical addresses into kernel
1305 * virtual address space.
1307 * The value passed in '*virt' is a suggested virtual address for
1308 * the mapping. Architectures which can support a direct-mapped
1309 * physical to virtual region can return the appropriate address
1310 * within that region, leaving '*virt' unchanged. Other
1311 * architectures should map the pages starting at '*virt' and
1312 * update '*virt' with the first usable address after the mapped
1316 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1318 return PHYS_TO_DMAP(start);
1323 * Add a list of wired pages to the kva
1324 * this routine is only used for temporary
1325 * kernel mappings that do not need to have
1326 * page modification or references recorded.
1327 * Note that old mappings are simply written
1328 * over. The page *must* be wired.
1329 * Note: SMP coherent. Uses a ranged shootdown IPI.
1332 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1334 pt_entry_t *endpte, oldpte, pa, *pte;
1339 endpte = pte + count;
1340 while (pte < endpte) {
1342 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1343 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1345 pte_store(pte, pa | PG_G | PG_RW | PG_V);
1349 if (__predict_false((oldpte & PG_V) != 0))
1350 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1355 * This routine tears out page mappings from the
1356 * kernel -- it is meant only for temporary mappings.
1357 * Note: SMP coherent. Uses a ranged shootdown IPI.
1360 pmap_qremove(vm_offset_t sva, int count)
1365 while (count-- > 0) {
1369 pmap_invalidate_range(kernel_pmap, sva, va);
1372 /***************************************************
1373 * Page table page management routines.....
1374 ***************************************************/
1375 static __inline void
1376 pmap_free_zero_pages(vm_page_t free)
1380 while (free != NULL) {
1383 /* Preserve the page's PG_ZERO setting. */
1384 vm_page_free_toq(m);
1389 * Schedule the specified unused page table page to be freed. Specifically,
1390 * add the page to the specified list of pages that will be released to the
1391 * physical memory manager after the TLB has been updated.
1393 static __inline void
1394 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1398 m->flags |= PG_ZERO;
1400 m->flags &= ~PG_ZERO;
1406 * Inserts the specified page table page into the specified pmap's collection
1407 * of idle page table pages. Each of a pmap's page table pages is responsible
1408 * for mapping a distinct range of virtual addresses. The pmap's collection is
1409 * ordered by this virtual address range.
1412 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1416 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1417 root = pmap->pm_root;
1422 root = vm_page_splay(mpte->pindex, root);
1423 if (mpte->pindex < root->pindex) {
1424 mpte->left = root->left;
1427 } else if (mpte->pindex == root->pindex)
1428 panic("pmap_insert_pt_page: pindex already inserted");
1430 mpte->right = root->right;
1435 pmap->pm_root = mpte;
1439 * Looks for a page table page mapping the specified virtual address in the
1440 * specified pmap's collection of idle page table pages. Returns NULL if there
1441 * is no page table page corresponding to the specified virtual address.
1444 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1447 vm_pindex_t pindex = pmap_pde_pindex(va);
1449 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1450 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1451 mpte = vm_page_splay(pindex, mpte);
1452 if ((pmap->pm_root = mpte)->pindex != pindex)
1459 * Removes the specified page table page from the specified pmap's collection
1460 * of idle page table pages. The specified page table page must be a member of
1461 * the pmap's collection.
1464 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1468 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1469 if (mpte != pmap->pm_root) {
1470 root = vm_page_splay(mpte->pindex, pmap->pm_root);
1471 KASSERT(mpte == root,
1472 ("pmap_remove_pt_page: mpte %p is missing from pmap %p",
1475 if (mpte->left == NULL)
1478 root = vm_page_splay(mpte->pindex, mpte->left);
1479 root->right = mpte->right;
1481 pmap->pm_root = root;
1485 * This routine unholds page table pages, and if the hold count
1486 * drops to zero, then it decrements the wire count.
1489 pmap_unwire_pte_hold(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_page_t *free)
1493 if (m->wire_count == 0)
1494 return (_pmap_unwire_pte_hold(pmap, va, m, free));
1500 _pmap_unwire_pte_hold(pmap_t pmap, vm_offset_t va, vm_page_t m,
1504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1506 * unmap the page table page
1508 if (m->pindex >= (NUPDE + NUPDPE)) {
1511 pml4 = pmap_pml4e(pmap, va);
1513 } else if (m->pindex >= NUPDE) {
1516 pdp = pmap_pdpe(pmap, va);
1521 pd = pmap_pde(pmap, va);
1524 pmap_resident_count_dec(pmap, 1);
1525 if (m->pindex < NUPDE) {
1526 /* We just released a PT, unhold the matching PD */
1529 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
1530 pmap_unwire_pte_hold(pmap, va, pdpg, free);
1532 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
1533 /* We just released a PD, unhold the matching PDP */
1536 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
1537 pmap_unwire_pte_hold(pmap, va, pdppg, free);
1541 * This is a release store so that the ordinary store unmapping
1542 * the page table page is globally performed before TLB shoot-
1545 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1548 * Put page on a list so that it is released after
1549 * *ALL* TLB shootdown is done
1551 pmap_add_delayed_free_list(m, free, TRUE);
1557 * After removing a page table entry, this routine is used to
1558 * conditionally free the page, and manage the hold/wire counts.
1561 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, vm_page_t *free)
1565 if (va >= VM_MAXUSER_ADDRESS)
1567 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1568 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1569 return (pmap_unwire_pte_hold(pmap, va, mpte, free));
1573 pmap_pinit0(pmap_t pmap)
1576 PMAP_LOCK_INIT(pmap);
1577 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1578 pmap->pm_root = NULL;
1579 CPU_ZERO(&pmap->pm_active);
1580 PCPU_SET(curpmap, pmap);
1581 TAILQ_INIT(&pmap->pm_pvchunk);
1582 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1586 * Initialize a preallocated and zeroed pmap structure,
1587 * such as one in a vmspace structure.
1590 pmap_pinit(pmap_t pmap)
1593 static vm_pindex_t color;
1596 PMAP_LOCK_INIT(pmap);
1599 * allocate the page directory page
1601 while ((pml4pg = vm_page_alloc(NULL, color++, VM_ALLOC_NOOBJ |
1602 VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1605 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
1607 if ((pml4pg->flags & PG_ZERO) == 0)
1608 pagezero(pmap->pm_pml4);
1610 /* Wire in kernel global address entries. */
1611 pmap->pm_pml4[KPML4I] = KPDPphys | PG_RW | PG_V | PG_U;
1612 for (i = 0; i < NDMPML4E; i++) {
1613 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + (i << PAGE_SHIFT)) |
1614 PG_RW | PG_V | PG_U;
1617 /* install self-referential address mapping entry(s) */
1618 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | PG_V | PG_RW | PG_A | PG_M;
1620 pmap->pm_root = NULL;
1621 CPU_ZERO(&pmap->pm_active);
1622 TAILQ_INIT(&pmap->pm_pvchunk);
1623 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1629 * this routine is called if the page table page is not
1632 * Note: If a page allocation fails at page table level two or three,
1633 * one or two pages may be held during the wait, only to be released
1634 * afterwards. This conservative approach is easily argued to avoid
1638 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, int flags)
1640 vm_page_t m, pdppg, pdpg;
1642 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1643 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1644 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1646 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1648 * Allocate a page table page.
1650 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1651 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1652 if (flags & M_WAITOK) {
1654 vm_page_unlock_queues();
1656 vm_page_lock_queues();
1661 * Indicate the need to retry. While waiting, the page table
1662 * page may have been allocated.
1666 if ((m->flags & PG_ZERO) == 0)
1670 * Map the pagetable page into the process address space, if
1671 * it isn't already there.
1674 if (ptepindex >= (NUPDE + NUPDPE)) {
1676 vm_pindex_t pml4index;
1678 /* Wire up a new PDPE page */
1679 pml4index = ptepindex - (NUPDE + NUPDPE);
1680 pml4 = &pmap->pm_pml4[pml4index];
1681 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1683 } else if (ptepindex >= NUPDE) {
1684 vm_pindex_t pml4index;
1685 vm_pindex_t pdpindex;
1689 /* Wire up a new PDE page */
1690 pdpindex = ptepindex - NUPDE;
1691 pml4index = pdpindex >> NPML4EPGSHIFT;
1693 pml4 = &pmap->pm_pml4[pml4index];
1694 if ((*pml4 & PG_V) == 0) {
1695 /* Have to allocate a new pdp, recurse */
1696 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
1699 atomic_subtract_int(&cnt.v_wire_count, 1);
1700 vm_page_free_zero(m);
1704 /* Add reference to pdp page */
1705 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
1706 pdppg->wire_count++;
1708 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1710 /* Now find the pdp page */
1711 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1712 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1715 vm_pindex_t pml4index;
1716 vm_pindex_t pdpindex;
1721 /* Wire up a new PTE page */
1722 pdpindex = ptepindex >> NPDPEPGSHIFT;
1723 pml4index = pdpindex >> NPML4EPGSHIFT;
1725 /* First, find the pdp and check that its valid. */
1726 pml4 = &pmap->pm_pml4[pml4index];
1727 if ((*pml4 & PG_V) == 0) {
1728 /* Have to allocate a new pd, recurse */
1729 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1732 atomic_subtract_int(&cnt.v_wire_count, 1);
1733 vm_page_free_zero(m);
1736 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1737 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1739 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
1740 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
1741 if ((*pdp & PG_V) == 0) {
1742 /* Have to allocate a new pd, recurse */
1743 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
1746 atomic_subtract_int(&cnt.v_wire_count,
1748 vm_page_free_zero(m);
1752 /* Add reference to the pd page */
1753 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
1757 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
1759 /* Now we know where the page directory page is */
1760 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
1761 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
1764 pmap_resident_count_inc(pmap, 1);
1770 pmap_allocpde(pmap_t pmap, vm_offset_t va, int flags)
1772 vm_pindex_t pdpindex, ptepindex;
1776 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1777 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1778 ("pmap_allocpde: flags is neither M_NOWAIT nor M_WAITOK"));
1780 pdpe = pmap_pdpe(pmap, va);
1781 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1782 /* Add a reference to the pd page. */
1783 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
1786 /* Allocate a pd page. */
1787 ptepindex = pmap_pde_pindex(va);
1788 pdpindex = ptepindex >> NPDPEPGSHIFT;
1789 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, flags);
1790 if (pdpg == NULL && (flags & M_WAITOK))
1797 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1799 vm_pindex_t ptepindex;
1803 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1804 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1805 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1808 * Calculate pagetable page index
1810 ptepindex = pmap_pde_pindex(va);
1813 * Get the page directory entry
1815 pd = pmap_pde(pmap, va);
1818 * This supports switching from a 2MB page to a
1821 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
1822 if (!pmap_demote_pde(pmap, pd, va)) {
1824 * Invalidation of the 2MB page mapping may have caused
1825 * the deallocation of the underlying PD page.
1832 * If the page table page is mapped, we just increment the
1833 * hold count, and activate it.
1835 if (pd != NULL && (*pd & PG_V) != 0) {
1836 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
1840 * Here if the pte page isn't mapped, or if it has been
1843 m = _pmap_allocpte(pmap, ptepindex, flags);
1844 if (m == NULL && (flags & M_WAITOK))
1851 /***************************************************
1852 * Pmap allocation/deallocation routines.
1853 ***************************************************/
1856 * Release any resources held by the given physical map.
1857 * Called when a pmap initialized by pmap_pinit is being released.
1858 * Should only be called if the map contains no valid mappings.
1861 pmap_release(pmap_t pmap)
1866 KASSERT(pmap->pm_stats.resident_count == 0,
1867 ("pmap_release: pmap resident count %ld != 0",
1868 pmap->pm_stats.resident_count));
1869 KASSERT(pmap->pm_root == NULL,
1870 ("pmap_release: pmap has reserved page table page(s)"));
1872 m = PHYS_TO_VM_PAGE(pmap->pm_pml4[PML4PML4I] & PG_FRAME);
1874 pmap->pm_pml4[KPML4I] = 0; /* KVA */
1875 for (i = 0; i < NDMPML4E; i++) /* Direct Map */
1876 pmap->pm_pml4[DMPML4I + i] = 0;
1877 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
1880 atomic_subtract_int(&cnt.v_wire_count, 1);
1881 vm_page_free_zero(m);
1882 PMAP_LOCK_DESTROY(pmap);
1886 kvm_size(SYSCTL_HANDLER_ARGS)
1888 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1890 return sysctl_handle_long(oidp, &ksize, 0, req);
1892 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1893 0, 0, kvm_size, "LU", "Size of KVM");
1896 kvm_free(SYSCTL_HANDLER_ARGS)
1898 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1900 return sysctl_handle_long(oidp, &kfree, 0, req);
1902 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1903 0, 0, kvm_free, "LU", "Amount of KVM free");
1906 * grow the number of kernel page table entries, if needed
1909 pmap_growkernel(vm_offset_t addr)
1913 pd_entry_t *pde, newpdir;
1916 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1919 * Return if "addr" is within the range of kernel page table pages
1920 * that were preallocated during pmap bootstrap. Moreover, leave
1921 * "kernel_vm_end" and the kernel page table as they were.
1923 * The correctness of this action is based on the following
1924 * argument: vm_map_findspace() allocates contiguous ranges of the
1925 * kernel virtual address space. It calls this function if a range
1926 * ends after "kernel_vm_end". If the kernel is mapped between
1927 * "kernel_vm_end" and "addr", then the range cannot begin at
1928 * "kernel_vm_end". In fact, its beginning address cannot be less
1929 * than the kernel. Thus, there is no immediate need to allocate
1930 * any new kernel page table pages between "kernel_vm_end" and
1933 if (KERNBASE < addr && addr <= KERNBASE + NKPT * NBPDR)
1936 addr = roundup2(addr, NBPDR);
1937 if (addr - 1 >= kernel_map->max_offset)
1938 addr = kernel_map->max_offset;
1939 while (kernel_vm_end < addr) {
1940 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
1941 if ((*pdpe & PG_V) == 0) {
1942 /* We need a new PDP entry */
1943 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
1944 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1945 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1947 panic("pmap_growkernel: no memory to grow kernel");
1948 if ((nkpg->flags & PG_ZERO) == 0)
1949 pmap_zero_page(nkpg);
1950 paddr = VM_PAGE_TO_PHYS(nkpg);
1951 *pdpe = (pdp_entry_t)
1952 (paddr | PG_V | PG_RW | PG_A | PG_M);
1953 continue; /* try again */
1955 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1956 if ((*pde & PG_V) != 0) {
1957 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1958 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1959 kernel_vm_end = kernel_map->max_offset;
1965 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
1966 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1969 panic("pmap_growkernel: no memory to grow kernel");
1970 if ((nkpg->flags & PG_ZERO) == 0)
1971 pmap_zero_page(nkpg);
1972 paddr = VM_PAGE_TO_PHYS(nkpg);
1973 newpdir = (pd_entry_t) (paddr | PG_V | PG_RW | PG_A | PG_M);
1974 pde_store(pde, newpdir);
1976 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1977 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1978 kernel_vm_end = kernel_map->max_offset;
1985 /***************************************************
1986 * page management routines.
1987 ***************************************************/
1989 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1990 CTASSERT(_NPCM == 3);
1991 CTASSERT(_NPCPV == 168);
1993 static __inline struct pv_chunk *
1994 pv_to_chunk(pv_entry_t pv)
1997 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK);
2000 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2002 #define PC_FREE0 0xfffffffffffffffful
2003 #define PC_FREE1 0xfffffffffffffffful
2004 #define PC_FREE2 0x000000fffffffffful
2006 static uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2008 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2009 "Current number of pv entries");
2012 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2014 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2015 "Current number of pv entry chunks");
2016 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2017 "Current number of pv entry chunks allocated");
2018 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2019 "Current number of pv entry chunks frees");
2020 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2021 "Number of times tried to get a chunk page but failed.");
2023 static long pv_entry_frees, pv_entry_allocs;
2024 static int pv_entry_spare;
2026 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2027 "Current number of pv entry frees");
2028 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2029 "Current number of pv entry allocs");
2030 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2031 "Current number of spare pv entries");
2033 static int pmap_collect_inactive, pmap_collect_active;
2035 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
2036 "Current number times pmap_collect called on inactive queue");
2037 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
2038 "Current number times pmap_collect called on active queue");
2042 * We are in a serious low memory condition. Resort to
2043 * drastic measures to free some pages so we can allocate
2044 * another pv entry chunk. This is normally called to
2045 * unmap inactive pages, and if necessary, active pages.
2047 * We do not, however, unmap 2mpages because subsequent accesses will
2048 * allocate per-page pv entries until repromotion occurs, thereby
2049 * exacerbating the shortage of free pv entries.
2052 pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
2056 pt_entry_t *pte, tpte;
2057 pv_entry_t next_pv, pv;
2061 TAILQ_FOREACH(m, &vpq->pl, pageq) {
2062 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy)
2064 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2067 /* Avoid deadlock and lock recursion. */
2068 if (pmap > locked_pmap)
2070 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2072 pmap_resident_count_dec(pmap, 1);
2073 pde = pmap_pde(pmap, va);
2074 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found"
2075 " a 2mpage in page %p's pv list", m));
2076 pte = pmap_pde_to_pte(pde, va);
2077 tpte = pte_load_clear(pte);
2078 KASSERT((tpte & PG_W) == 0,
2079 ("pmap_collect: wired pte %#lx", tpte));
2081 vm_page_aflag_set(m, PGA_REFERENCED);
2082 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2085 pmap_unuse_pt(pmap, va, *pde, &free);
2086 pmap_invalidate_page(pmap, va);
2087 pmap_free_zero_pages(free);
2088 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2089 free_pv_entry(pmap, pv);
2090 if (pmap != locked_pmap)
2093 if (TAILQ_EMPTY(&m->md.pv_list) &&
2094 TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list))
2095 vm_page_aflag_clear(m, PGA_WRITEABLE);
2101 * free the pv_entry back to the free list
2104 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2107 struct pv_chunk *pc;
2108 int idx, field, bit;
2110 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2111 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2112 PV_STAT(pv_entry_frees++);
2113 PV_STAT(pv_entry_spare++);
2115 pc = pv_to_chunk(pv);
2116 idx = pv - &pc->pc_pventry[0];
2119 pc->pc_map[field] |= 1ul << bit;
2120 /* move to head of list */
2121 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2122 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2123 pc->pc_map[2] != PC_FREE2) {
2124 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2127 PV_STAT(pv_entry_spare -= _NPCPV);
2128 PV_STAT(pc_chunk_count--);
2129 PV_STAT(pc_chunk_frees++);
2130 /* entire chunk is free, return it */
2131 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2132 dump_drop_page(m->phys_addr);
2133 vm_page_unwire(m, 0);
2138 * get a new pv_entry, allocating a block from the system
2142 get_pv_entry(pmap_t pmap, boolean_t try)
2144 static vm_pindex_t colour;
2145 struct vpgqueues *pq;
2148 struct pv_chunk *pc;
2151 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2152 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2153 PV_STAT(pv_entry_allocs++);
2156 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2158 for (field = 0; field < _NPCM; field++) {
2159 if (pc->pc_map[field]) {
2160 bit = bsfq(pc->pc_map[field]);
2164 if (field < _NPCM) {
2165 pv = &pc->pc_pventry[field * 64 + bit];
2166 pc->pc_map[field] &= ~(1ul << bit);
2167 /* If this was the last item, move it to tail */
2168 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2169 pc->pc_map[2] == 0) {
2170 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2171 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2175 PV_STAT(pv_entry_spare--);
2179 /* No free items, allocate another chunk */
2180 m = vm_page_alloc(NULL, colour, (pq == &vm_page_queues[PQ_ACTIVE] ?
2181 VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | VM_ALLOC_NOOBJ |
2185 PV_STAT(pc_chunk_tryfail++);
2189 * Reclaim pv entries: At first, destroy mappings to inactive
2190 * pages. After that, if a pv chunk entry is still needed,
2191 * destroy mappings to active pages.
2194 PV_STAT(pmap_collect_inactive++);
2195 pq = &vm_page_queues[PQ_INACTIVE];
2196 } else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2197 PV_STAT(pmap_collect_active++);
2198 pq = &vm_page_queues[PQ_ACTIVE];
2200 panic("get_pv_entry: allocation failed");
2201 pmap_collect(pmap, pq);
2204 PV_STAT(pc_chunk_count++);
2205 PV_STAT(pc_chunk_allocs++);
2207 dump_add_page(m->phys_addr);
2208 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2210 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2211 pc->pc_map[1] = PC_FREE1;
2212 pc->pc_map[2] = PC_FREE2;
2213 pv = &pc->pc_pventry[0];
2214 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2216 PV_STAT(pv_entry_spare += _NPCPV - 1);
2221 * First find and then remove the pv entry for the specified pmap and virtual
2222 * address from the specified pv list. Returns the pv entry if found and NULL
2223 * otherwise. This operation can be performed on pv lists for either 4KB or
2224 * 2MB page mappings.
2226 static __inline pv_entry_t
2227 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2231 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2232 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2233 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2234 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2242 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2243 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2244 * entries for each of the 4KB page mappings.
2247 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2249 struct md_page *pvh;
2251 vm_offset_t va_last;
2254 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2255 KASSERT((pa & PDRMASK) == 0,
2256 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
2259 * Transfer the 2mpage's pv entry for this mapping to the first
2262 pvh = pa_to_pvh(pa);
2263 va = trunc_2mpage(va);
2264 pv = pmap_pvh_remove(pvh, pmap, va);
2265 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2266 m = PHYS_TO_VM_PAGE(pa);
2267 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2268 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2269 va_last = va + NBPDR - PAGE_SIZE;
2272 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2273 ("pmap_pv_demote_pde: page %p is not managed", m));
2275 pmap_insert_entry(pmap, va, m);
2276 } while (va < va_last);
2280 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2281 * replace the many pv entries for the 4KB page mappings by a single pv entry
2282 * for the 2MB page mapping.
2285 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2287 struct md_page *pvh;
2289 vm_offset_t va_last;
2292 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2293 KASSERT((pa & PDRMASK) == 0,
2294 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
2297 * Transfer the first page's pv entry for this mapping to the
2298 * 2mpage's pv list. Aside from avoiding the cost of a call
2299 * to get_pv_entry(), a transfer avoids the possibility that
2300 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2301 * removes one of the mappings that is being promoted.
2303 m = PHYS_TO_VM_PAGE(pa);
2304 va = trunc_2mpage(va);
2305 pv = pmap_pvh_remove(&m->md, pmap, va);
2306 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2307 pvh = pa_to_pvh(pa);
2308 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2309 /* Free the remaining NPTEPG - 1 pv entries. */
2310 va_last = va + NBPDR - PAGE_SIZE;
2314 pmap_pvh_free(&m->md, pmap, va);
2315 } while (va < va_last);
2319 * First find and then destroy the pv entry for the specified pmap and virtual
2320 * address. This operation can be performed on pv lists for either 4KB or 2MB
2324 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2328 pv = pmap_pvh_remove(pvh, pmap, va);
2329 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2330 free_pv_entry(pmap, pv);
2334 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2336 struct md_page *pvh;
2338 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2339 pmap_pvh_free(&m->md, pmap, va);
2340 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2342 if (TAILQ_EMPTY(&pvh->pv_list))
2343 vm_page_aflag_clear(m, PGA_WRITEABLE);
2348 * Create a pv entry for page at pa for
2352 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2356 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2357 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2358 pv = get_pv_entry(pmap, FALSE);
2360 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2364 * Conditionally create a pv entry.
2367 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2371 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2372 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2373 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
2375 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2382 * Create the pv entry for a 2MB page mapping.
2385 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2387 struct md_page *pvh;
2390 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2391 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
2393 pvh = pa_to_pvh(pa);
2394 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2401 * Fills a page table page with mappings to consecutive physical pages.
2404 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2408 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2410 newpte += PAGE_SIZE;
2415 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
2416 * mapping is invalidated.
2419 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2421 pd_entry_t newpde, oldpde;
2422 pt_entry_t *firstpte, newpte;
2424 vm_page_t free, mpte;
2426 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2428 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2429 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2430 mpte = pmap_lookup_pt_page(pmap, va);
2432 pmap_remove_pt_page(pmap, mpte);
2434 KASSERT((oldpde & PG_W) == 0,
2435 ("pmap_demote_pde: page table page for a wired mapping"
2439 * Invalidate the 2MB page mapping and return "failure" if the
2440 * mapping was never accessed or the allocation of the new
2441 * page table page fails. If the 2MB page mapping belongs to
2442 * the direct map region of the kernel's address space, then
2443 * the page allocation request specifies the highest possible
2444 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
2445 * normal. Page table pages are preallocated for every other
2446 * part of the kernel address space, so the direct map region
2447 * is the only part of the kernel address space that must be
2450 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2451 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
2452 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
2453 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2455 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free);
2456 pmap_invalidate_page(pmap, trunc_2mpage(va));
2457 pmap_free_zero_pages(free);
2458 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
2459 " in pmap %p", va, pmap);
2462 if (va < VM_MAXUSER_ADDRESS)
2463 pmap_resident_count_inc(pmap, 1);
2465 mptepa = VM_PAGE_TO_PHYS(mpte);
2466 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
2467 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2468 KASSERT((oldpde & PG_A) != 0,
2469 ("pmap_demote_pde: oldpde is missing PG_A"));
2470 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2471 ("pmap_demote_pde: oldpde is missing PG_M"));
2472 newpte = oldpde & ~PG_PS;
2473 if ((newpte & PG_PDE_PAT) != 0)
2474 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2477 * If the page table page is new, initialize it.
2479 if (mpte->wire_count == 1) {
2480 mpte->wire_count = NPTEPG;
2481 pmap_fill_ptp(firstpte, newpte);
2483 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2484 ("pmap_demote_pde: firstpte and newpte map different physical"
2488 * If the mapping has changed attributes, update the page table
2491 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2492 pmap_fill_ptp(firstpte, newpte);
2495 * Demote the mapping. This pmap is locked. The old PDE has
2496 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2497 * set. Thus, there is no danger of a race with another
2498 * processor changing the setting of PG_A and/or PG_M between
2499 * the read above and the store below.
2501 if (workaround_erratum383)
2502 pmap_update_pde(pmap, va, pde, newpde);
2504 pde_store(pde, newpde);
2507 * Invalidate a stale recursive mapping of the page table page.
2509 if (va >= VM_MAXUSER_ADDRESS)
2510 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2513 * Demote the pv entry. This depends on the earlier demotion
2514 * of the mapping. Specifically, the (re)creation of a per-
2515 * page pv entry might trigger the execution of pmap_collect(),
2516 * which might reclaim a newly (re)created per-page pv entry
2517 * and destroy the associated mapping. In order to destroy
2518 * the mapping, the PDE must have already changed from mapping
2519 * the 2mpage to referencing the page table page.
2521 if ((oldpde & PG_MANAGED) != 0)
2522 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2524 pmap_pde_demotions++;
2525 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
2526 " in pmap %p", va, pmap);
2531 * pmap_remove_pde: do the things to unmap a superpage in a process
2534 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2537 struct md_page *pvh;
2539 vm_offset_t eva, va;
2542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2543 KASSERT((sva & PDRMASK) == 0,
2544 ("pmap_remove_pde: sva is not 2mpage aligned"));
2545 oldpde = pte_load_clear(pdq);
2547 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2550 * Machines that don't support invlpg, also don't support
2554 pmap_invalidate_page(kernel_pmap, sva);
2555 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
2556 if (oldpde & PG_MANAGED) {
2557 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2558 pmap_pvh_free(pvh, pmap, sva);
2560 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2561 va < eva; va += PAGE_SIZE, m++) {
2562 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2565 vm_page_aflag_set(m, PGA_REFERENCED);
2566 if (TAILQ_EMPTY(&m->md.pv_list) &&
2567 TAILQ_EMPTY(&pvh->pv_list))
2568 vm_page_aflag_clear(m, PGA_WRITEABLE);
2571 if (pmap == kernel_pmap) {
2572 if (!pmap_demote_pde(pmap, pdq, sva))
2573 panic("pmap_remove_pde: failed demotion");
2575 mpte = pmap_lookup_pt_page(pmap, sva);
2577 pmap_remove_pt_page(pmap, mpte);
2578 pmap_resident_count_dec(pmap, 1);
2579 KASSERT(mpte->wire_count == NPTEPG,
2580 ("pmap_remove_pde: pte page wire count error"));
2581 mpte->wire_count = 0;
2582 pmap_add_delayed_free_list(mpte, free, FALSE);
2583 atomic_subtract_int(&cnt.v_wire_count, 1);
2586 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
2590 * pmap_remove_pte: do the things to unmap a page in a process
2593 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2594 pd_entry_t ptepde, vm_page_t *free)
2599 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2600 oldpte = pte_load_clear(ptq);
2602 pmap->pm_stats.wired_count -= 1;
2603 pmap_resident_count_dec(pmap, 1);
2604 if (oldpte & PG_MANAGED) {
2605 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2606 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2609 vm_page_aflag_set(m, PGA_REFERENCED);
2610 pmap_remove_entry(pmap, m, va);
2612 return (pmap_unuse_pt(pmap, va, ptepde, free));
2616 * Remove a single page from a process address space
2619 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, vm_page_t *free)
2623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2624 if ((*pde & PG_V) == 0)
2626 pte = pmap_pde_to_pte(pde, va);
2627 if ((*pte & PG_V) == 0)
2629 pmap_remove_pte(pmap, pte, va, *pde, free);
2630 pmap_invalidate_page(pmap, va);
2634 * Remove the given range of addresses from the specified map.
2636 * It is assumed that the start and end are properly
2637 * rounded to the page size.
2640 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2642 vm_offset_t va, va_next;
2643 pml4_entry_t *pml4e;
2645 pd_entry_t ptpaddr, *pde;
2647 vm_page_t free = NULL;
2651 * Perform an unsynchronized read. This is, however, safe.
2653 if (pmap->pm_stats.resident_count == 0)
2658 vm_page_lock_queues();
2662 * special handling of removing one page. a very
2663 * common operation and easy to short circuit some
2666 if (sva + PAGE_SIZE == eva) {
2667 pde = pmap_pde(pmap, sva);
2668 if (pde && (*pde & PG_PS) == 0) {
2669 pmap_remove_page(pmap, sva, pde, &free);
2674 for (; sva < eva; sva = va_next) {
2676 if (pmap->pm_stats.resident_count == 0)
2679 pml4e = pmap_pml4e(pmap, sva);
2680 if ((*pml4e & PG_V) == 0) {
2681 va_next = (sva + NBPML4) & ~PML4MASK;
2687 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
2688 if ((*pdpe & PG_V) == 0) {
2689 va_next = (sva + NBPDP) & ~PDPMASK;
2696 * Calculate index for next page table.
2698 va_next = (sva + NBPDR) & ~PDRMASK;
2702 pde = pmap_pdpe_to_pde(pdpe, sva);
2706 * Weed out invalid mappings.
2712 * Check for large page.
2714 if ((ptpaddr & PG_PS) != 0) {
2716 * Are we removing the entire large page? If not,
2717 * demote the mapping and fall through.
2719 if (sva + NBPDR == va_next && eva >= va_next) {
2721 * The TLB entry for a PG_G mapping is
2722 * invalidated by pmap_remove_pde().
2724 if ((ptpaddr & PG_G) == 0)
2726 pmap_remove_pde(pmap, pde, sva, &free);
2728 } else if (!pmap_demote_pde(pmap, pde, sva)) {
2729 /* The large page mapping was destroyed. */
2736 * Limit our scan to either the end of the va represented
2737 * by the current page table page, or to the end of the
2738 * range being removed.
2744 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2747 if (va != va_next) {
2748 pmap_invalidate_range(pmap, va, sva);
2753 if ((*pte & PG_G) == 0)
2755 else if (va == va_next)
2757 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free)) {
2763 pmap_invalidate_range(pmap, va, sva);
2767 pmap_invalidate_all(pmap);
2768 vm_page_unlock_queues();
2770 pmap_free_zero_pages(free);
2774 * Routine: pmap_remove_all
2776 * Removes this physical page from
2777 * all physical maps in which it resides.
2778 * Reflects back modify bits to the pager.
2781 * Original versions of this routine were very
2782 * inefficient because they iteratively called
2783 * pmap_remove (slow...)
2787 pmap_remove_all(vm_page_t m)
2789 struct md_page *pvh;
2792 pt_entry_t *pte, tpte;
2797 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2798 ("pmap_remove_all: page %p is not managed", m));
2800 vm_page_lock_queues();
2801 if ((m->flags & PG_FICTITIOUS) != 0)
2802 goto small_mappings;
2803 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2804 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2808 pde = pmap_pde(pmap, va);
2809 (void)pmap_demote_pde(pmap, pde, va);
2813 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2816 pmap_resident_count_dec(pmap, 1);
2817 pde = pmap_pde(pmap, pv->pv_va);
2818 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
2819 " a 2mpage in page %p's pv list", m));
2820 pte = pmap_pde_to_pte(pde, pv->pv_va);
2821 tpte = pte_load_clear(pte);
2823 pmap->pm_stats.wired_count--;
2825 vm_page_aflag_set(m, PGA_REFERENCED);
2828 * Update the vm_page_t clean and reference bits.
2830 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2832 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
2833 pmap_invalidate_page(pmap, pv->pv_va);
2834 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2835 free_pv_entry(pmap, pv);
2838 vm_page_aflag_clear(m, PGA_WRITEABLE);
2839 vm_page_unlock_queues();
2840 pmap_free_zero_pages(free);
2844 * pmap_protect_pde: do the things to protect a 2mpage in a process
2847 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
2849 pd_entry_t newpde, oldpde;
2850 vm_offset_t eva, va;
2852 boolean_t anychanged;
2854 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2855 KASSERT((sva & PDRMASK) == 0,
2856 ("pmap_protect_pde: sva is not 2mpage aligned"));
2859 oldpde = newpde = *pde;
2860 if (oldpde & PG_MANAGED) {
2862 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2863 va < eva; va += PAGE_SIZE, m++)
2864 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2867 if ((prot & VM_PROT_WRITE) == 0)
2868 newpde &= ~(PG_RW | PG_M);
2869 if ((prot & VM_PROT_EXECUTE) == 0)
2871 if (newpde != oldpde) {
2872 if (!atomic_cmpset_long(pde, oldpde, newpde))
2875 pmap_invalidate_page(pmap, sva);
2879 return (anychanged);
2883 * Set the physical protection on the
2884 * specified range of this map as requested.
2887 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2889 vm_offset_t va_next;
2890 pml4_entry_t *pml4e;
2892 pd_entry_t ptpaddr, *pde;
2895 boolean_t pv_lists_locked;
2897 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2898 pmap_remove(pmap, sva, eva);
2902 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
2903 (VM_PROT_WRITE|VM_PROT_EXECUTE))
2906 pv_lists_locked = FALSE;
2911 for (; sva < eva; sva = va_next) {
2913 pml4e = pmap_pml4e(pmap, sva);
2914 if ((*pml4e & PG_V) == 0) {
2915 va_next = (sva + NBPML4) & ~PML4MASK;
2921 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
2922 if ((*pdpe & PG_V) == 0) {
2923 va_next = (sva + NBPDP) & ~PDPMASK;
2929 va_next = (sva + NBPDR) & ~PDRMASK;
2933 pde = pmap_pdpe_to_pde(pdpe, sva);
2937 * Weed out invalid mappings.
2943 * Check for large page.
2945 if ((ptpaddr & PG_PS) != 0) {
2947 * Are we protecting the entire large page? If not,
2948 * demote the mapping and fall through.
2950 if (sva + NBPDR == va_next && eva >= va_next) {
2952 * The TLB entry for a PG_G mapping is
2953 * invalidated by pmap_protect_pde().
2955 if (pmap_protect_pde(pmap, pde, sva, prot))
2959 if (!pv_lists_locked) {
2960 pv_lists_locked = TRUE;
2961 if (!mtx_trylock(&vm_page_queue_mtx)) {
2963 pmap_invalidate_all(
2966 vm_page_lock_queues();
2970 if (!pmap_demote_pde(pmap, pde, sva)) {
2972 * The large page mapping was
2983 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2985 pt_entry_t obits, pbits;
2989 obits = pbits = *pte;
2990 if ((pbits & PG_V) == 0)
2993 if ((prot & VM_PROT_WRITE) == 0) {
2994 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
2995 (PG_MANAGED | PG_M | PG_RW)) {
2996 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
2999 pbits &= ~(PG_RW | PG_M);
3001 if ((prot & VM_PROT_EXECUTE) == 0)
3004 if (pbits != obits) {
3005 if (!atomic_cmpset_long(pte, obits, pbits))
3008 pmap_invalidate_page(pmap, sva);
3015 pmap_invalidate_all(pmap);
3016 if (pv_lists_locked)
3017 vm_page_unlock_queues();
3022 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3023 * single page table page (PTP) to a single 2MB page mapping. For promotion
3024 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3025 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3026 * identical characteristics.
3029 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3032 pt_entry_t *firstpte, oldpte, pa, *pte;
3033 vm_offset_t oldpteva;
3036 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3039 * Examine the first PTE in the specified PTP. Abort if this PTE is
3040 * either invalid, unused, or does not map the first 4KB physical page
3041 * within a 2MB page.
3043 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
3046 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3047 pmap_pde_p_failures++;
3048 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3049 " in pmap %p", va, pmap);
3052 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3054 * When PG_M is already clear, PG_RW can be cleared without
3055 * a TLB invalidation.
3057 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
3063 * Examine each of the other PTEs in the specified PTP. Abort if this
3064 * PTE maps an unexpected 4KB physical page or does not have identical
3065 * characteristics to the first PTE.
3067 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3068 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3071 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3072 pmap_pde_p_failures++;
3073 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3074 " in pmap %p", va, pmap);
3077 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3079 * When PG_M is already clear, PG_RW can be cleared
3080 * without a TLB invalidation.
3082 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
3085 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3087 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3088 " in pmap %p", oldpteva, pmap);
3090 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3091 pmap_pde_p_failures++;
3092 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
3093 " in pmap %p", va, pmap);
3100 * Save the page table page in its current state until the PDE
3101 * mapping the superpage is demoted by pmap_demote_pde() or
3102 * destroyed by pmap_remove_pde().
3104 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3105 KASSERT(mpte >= vm_page_array &&
3106 mpte < &vm_page_array[vm_page_array_size],
3107 ("pmap_promote_pde: page table page is out of range"));
3108 KASSERT(mpte->pindex == pmap_pde_pindex(va),
3109 ("pmap_promote_pde: page table page's pindex is wrong"));
3110 pmap_insert_pt_page(pmap, mpte);
3113 * Promote the pv entries.
3115 if ((newpde & PG_MANAGED) != 0)
3116 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3119 * Propagate the PAT index to its proper position.
3121 if ((newpde & PG_PTE_PAT) != 0)
3122 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3125 * Map the superpage.
3127 if (workaround_erratum383)
3128 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3130 pde_store(pde, PG_PS | newpde);
3132 pmap_pde_promotions++;
3133 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
3134 " in pmap %p", va, pmap);
3138 * Insert the given physical page (p) at
3139 * the specified virtual address (v) in the
3140 * target physical map with the protection requested.
3142 * If specified, the page will be wired down, meaning
3143 * that the related pte can not be reclaimed.
3145 * NB: This is the only routine which MAY NOT lazy-evaluate
3146 * or lose information. That is, this routine must actually
3147 * insert this page into the given map NOW.
3150 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3151 vm_prot_t prot, boolean_t wired)
3155 pt_entry_t newpte, origpte;
3161 va = trunc_page(va);
3162 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3163 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3164 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
3166 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3167 VM_OBJECT_LOCKED(m->object),
3168 ("pmap_enter: page %p is not busy", m));
3172 vm_page_lock_queues();
3176 * In the case that a page table page is not
3177 * resident, we are creating it here.
3179 if (va < VM_MAXUSER_ADDRESS)
3180 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3182 pde = pmap_pde(pmap, va);
3183 if (pde != NULL && (*pde & PG_V) != 0) {
3184 if ((*pde & PG_PS) != 0)
3185 panic("pmap_enter: attempted pmap_enter on 2MB page");
3186 pte = pmap_pde_to_pte(pde, va);
3188 panic("pmap_enter: invalid page directory va=%#lx", va);
3190 pa = VM_PAGE_TO_PHYS(m);
3193 opa = origpte & PG_FRAME;
3196 * Mapping has not changed, must be protection or wiring change.
3198 if (origpte && (opa == pa)) {
3200 * Wiring change, just update stats. We don't worry about
3201 * wiring PT pages as they remain resident as long as there
3202 * are valid mappings in them. Hence, if a user page is wired,
3203 * the PT page will be also.
3205 if (wired && ((origpte & PG_W) == 0))
3206 pmap->pm_stats.wired_count++;
3207 else if (!wired && (origpte & PG_W))
3208 pmap->pm_stats.wired_count--;
3211 * Remove extra pte reference
3216 if (origpte & PG_MANAGED) {
3226 * Mapping has changed, invalidate old range and fall through to
3227 * handle validating new mapping.
3231 pmap->pm_stats.wired_count--;
3232 if (origpte & PG_MANAGED) {
3233 om = PHYS_TO_VM_PAGE(opa);
3234 pv = pmap_pvh_remove(&om->md, pmap, va);
3238 KASSERT(mpte->wire_count > 0,
3239 ("pmap_enter: missing reference to page table page,"
3243 pmap_resident_count_inc(pmap, 1);
3246 * Enter on the PV list if part of our managed memory.
3248 if ((m->oflags & VPO_UNMANAGED) == 0) {
3249 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3250 ("pmap_enter: managed mapping within the clean submap"));
3252 pv = get_pv_entry(pmap, FALSE);
3254 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3256 } else if (pv != NULL)
3257 free_pv_entry(pmap, pv);
3260 * Increment counters
3263 pmap->pm_stats.wired_count++;
3267 * Now validate mapping with desired protection/wiring.
3269 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3270 if ((prot & VM_PROT_WRITE) != 0) {
3272 if ((newpte & PG_MANAGED) != 0)
3273 vm_page_aflag_set(m, PGA_WRITEABLE);
3275 if ((prot & VM_PROT_EXECUTE) == 0)
3279 if (va < VM_MAXUSER_ADDRESS)
3281 if (pmap == kernel_pmap)
3285 * if the mapping or permission bits are different, we need
3286 * to update the pte.
3288 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3290 if ((access & VM_PROT_WRITE) != 0)
3292 if (origpte & PG_V) {
3294 origpte = pte_load_store(pte, newpte);
3295 if (origpte & PG_A) {
3296 if (origpte & PG_MANAGED)
3297 vm_page_aflag_set(om, PGA_REFERENCED);
3298 if (opa != VM_PAGE_TO_PHYS(m) || ((origpte &
3299 PG_NX) == 0 && (newpte & PG_NX)))
3302 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3303 if ((origpte & PG_MANAGED) != 0)
3305 if ((newpte & PG_RW) == 0)
3308 if ((origpte & PG_MANAGED) != 0 &&
3309 TAILQ_EMPTY(&om->md.pv_list) &&
3310 ((om->flags & PG_FICTITIOUS) != 0 ||
3311 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3312 vm_page_aflag_clear(om, PGA_WRITEABLE);
3314 pmap_invalidate_page(pmap, va);
3316 pte_store(pte, newpte);
3320 * If both the page table page and the reservation are fully
3321 * populated, then attempt promotion.
3323 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3324 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3325 vm_reserv_level_iffullpop(m) == 0)
3326 pmap_promote_pde(pmap, pde, va);
3328 vm_page_unlock_queues();
3333 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
3334 * otherwise. Fails if (1) a page table page cannot be allocated without
3335 * blocking, (2) a mapping already exists at the specified virtual address, or
3336 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3339 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3341 pd_entry_t *pde, newpde;
3342 vm_page_t free, mpde;
3344 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3345 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3346 if ((mpde = pmap_allocpde(pmap, va, M_NOWAIT)) == NULL) {
3347 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3348 " in pmap %p", va, pmap);
3351 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
3352 pde = &pde[pmap_pde_index(va)];
3353 if ((*pde & PG_V) != 0) {
3354 KASSERT(mpde->wire_count > 1,
3355 ("pmap_enter_pde: mpde's wire count is too low"));
3357 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3358 " in pmap %p", va, pmap);
3361 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3363 if ((m->oflags & VPO_UNMANAGED) == 0) {
3364 newpde |= PG_MANAGED;
3367 * Abort this mapping if its PV entry could not be created.
3369 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3371 if (pmap_unwire_pte_hold(pmap, va, mpde, &free)) {
3372 pmap_invalidate_page(pmap, va);
3373 pmap_free_zero_pages(free);
3375 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3376 " in pmap %p", va, pmap);
3380 if ((prot & VM_PROT_EXECUTE) == 0)
3382 if (va < VM_MAXUSER_ADDRESS)
3386 * Increment counters.
3388 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3391 * Map the superpage.
3393 pde_store(pde, newpde);
3395 pmap_pde_mappings++;
3396 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3397 " in pmap %p", va, pmap);
3402 * Maps a sequence of resident pages belonging to the same object.
3403 * The sequence begins with the given page m_start. This page is
3404 * mapped at the given virtual address start. Each subsequent page is
3405 * mapped at a virtual address that is offset from start by the same
3406 * amount as the page is offset from m_start within the object. The
3407 * last page in the sequence is the page with the largest offset from
3408 * m_start that can be mapped at a virtual address less than the given
3409 * virtual address end. Not every virtual page between start and end
3410 * is mapped; only those for which a resident page exists with the
3411 * corresponding offset from m_start are mapped.
3414 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3415 vm_page_t m_start, vm_prot_t prot)
3419 vm_pindex_t diff, psize;
3421 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3422 psize = atop(end - start);
3425 vm_page_lock_queues();
3427 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3428 va = start + ptoa(diff);
3429 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3430 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3431 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3432 pmap_enter_pde(pmap, va, m, prot))
3433 m = &m[NBPDR / PAGE_SIZE - 1];
3435 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3437 m = TAILQ_NEXT(m, listq);
3439 vm_page_unlock_queues();
3444 * this code makes some *MAJOR* assumptions:
3445 * 1. Current pmap & pmap exists.
3448 * 4. No page table pages.
3449 * but is *MUCH* faster than pmap_enter...
3453 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3456 vm_page_lock_queues();
3458 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3459 vm_page_unlock_queues();
3464 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3465 vm_prot_t prot, vm_page_t mpte)
3471 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3472 (m->oflags & VPO_UNMANAGED) != 0,
3473 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3474 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3475 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3478 * In the case that a page table page is not
3479 * resident, we are creating it here.
3481 if (va < VM_MAXUSER_ADDRESS) {
3482 vm_pindex_t ptepindex;
3486 * Calculate pagetable page index
3488 ptepindex = pmap_pde_pindex(va);
3489 if (mpte && (mpte->pindex == ptepindex)) {
3493 * Get the page directory entry
3495 ptepa = pmap_pde(pmap, va);
3498 * If the page table page is mapped, we just increment
3499 * the hold count, and activate it.
3501 if (ptepa && (*ptepa & PG_V) != 0) {
3504 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
3507 mpte = _pmap_allocpte(pmap, ptepindex,
3513 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3514 pte = &pte[pmap_pte_index(va)];
3528 * Enter on the PV list if part of our managed memory.
3530 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3531 !pmap_try_insert_pv_entry(pmap, va, m)) {
3534 if (pmap_unwire_pte_hold(pmap, va, mpte, &free)) {
3535 pmap_invalidate_page(pmap, va);
3536 pmap_free_zero_pages(free);
3544 * Increment counters
3546 pmap_resident_count_inc(pmap, 1);
3548 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3549 if ((prot & VM_PROT_EXECUTE) == 0)
3553 * Now validate mapping with RO protection
3555 if ((m->oflags & VPO_UNMANAGED) != 0)
3556 pte_store(pte, pa | PG_V | PG_U);
3558 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3563 * Make a temporary mapping for a physical address. This is only intended
3564 * to be used for panic dumps.
3567 pmap_kenter_temporary(vm_paddr_t pa, int i)
3571 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3572 pmap_kenter(va, pa);
3574 return ((void *)crashdumpmap);
3578 * This code maps large physical mmap regions into the
3579 * processor address space. Note that some shortcuts
3580 * are taken, but the code works.
3583 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3584 vm_pindex_t pindex, vm_size_t size)
3587 vm_paddr_t pa, ptepa;
3591 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3592 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3593 ("pmap_object_init_pt: non-device object"));
3594 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3595 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3597 p = vm_page_lookup(object, pindex);
3598 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3599 ("pmap_object_init_pt: invalid page %p", p));
3600 pat_mode = p->md.pat_mode;
3603 * Abort the mapping if the first page is not physically
3604 * aligned to a 2MB page boundary.
3606 ptepa = VM_PAGE_TO_PHYS(p);
3607 if (ptepa & (NBPDR - 1))
3611 * Skip the first page. Abort the mapping if the rest of
3612 * the pages are not physically contiguous or have differing
3613 * memory attributes.
3615 p = TAILQ_NEXT(p, listq);
3616 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3618 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3619 ("pmap_object_init_pt: invalid page %p", p));
3620 if (pa != VM_PAGE_TO_PHYS(p) ||
3621 pat_mode != p->md.pat_mode)
3623 p = TAILQ_NEXT(p, listq);
3627 * Map using 2MB pages. Since "ptepa" is 2M aligned and
3628 * "size" is a multiple of 2M, adding the PAT setting to "pa"
3629 * will not affect the termination of this loop.
3632 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3633 size; pa += NBPDR) {
3634 pdpg = pmap_allocpde(pmap, addr, M_NOWAIT);
3637 * The creation of mappings below is only an
3638 * optimization. If a page directory page
3639 * cannot be allocated without blocking,
3640 * continue on to the next mapping rather than
3646 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3647 pde = &pde[pmap_pde_index(addr)];
3648 if ((*pde & PG_V) == 0) {
3649 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3650 PG_U | PG_RW | PG_V);
3651 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
3652 pmap_pde_mappings++;
3654 /* Continue on if the PDE is already valid. */
3656 KASSERT(pdpg->wire_count > 0,
3657 ("pmap_object_init_pt: missing reference "
3658 "to page directory page, va: 0x%lx", addr));
3667 * Routine: pmap_change_wiring
3668 * Function: Change the wiring attribute for a map/virtual-address
3670 * In/out conditions:
3671 * The mapping must already exist in the pmap.
3674 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3678 boolean_t are_queues_locked;
3680 are_queues_locked = FALSE;
3683 * Wiring is not a hardware characteristic so there is no need to
3688 pde = pmap_pde(pmap, va);
3689 if ((*pde & PG_PS) != 0) {
3690 if (!wired != ((*pde & PG_W) == 0)) {
3691 if (!are_queues_locked) {
3692 are_queues_locked = TRUE;
3693 if (!mtx_trylock(&vm_page_queue_mtx)) {
3695 vm_page_lock_queues();
3699 if (!pmap_demote_pde(pmap, pde, va))
3700 panic("pmap_change_wiring: demotion failed");
3704 pte = pmap_pde_to_pte(pde, va);
3705 if (wired && (*pte & PG_W) == 0) {
3706 pmap->pm_stats.wired_count++;
3707 atomic_set_long(pte, PG_W);
3708 } else if (!wired && (*pte & PG_W) != 0) {
3709 pmap->pm_stats.wired_count--;
3710 atomic_clear_long(pte, PG_W);
3713 if (are_queues_locked)
3714 vm_page_unlock_queues();
3719 * Copy the range specified by src_addr/len
3720 * from the source map to the range dst_addr/len
3721 * in the destination map.
3723 * This routine is only advisory and need not do anything.
3727 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3728 vm_offset_t src_addr)
3732 vm_offset_t end_addr = src_addr + len;
3733 vm_offset_t va_next;
3735 if (dst_addr != src_addr)
3738 vm_page_lock_queues();
3739 if (dst_pmap < src_pmap) {
3740 PMAP_LOCK(dst_pmap);
3741 PMAP_LOCK(src_pmap);
3743 PMAP_LOCK(src_pmap);
3744 PMAP_LOCK(dst_pmap);
3746 for (addr = src_addr; addr < end_addr; addr = va_next) {
3747 pt_entry_t *src_pte, *dst_pte;
3748 vm_page_t dstmpde, dstmpte, srcmpte;
3749 pml4_entry_t *pml4e;
3751 pd_entry_t srcptepaddr, *pde;
3753 KASSERT(addr < UPT_MIN_ADDRESS,
3754 ("pmap_copy: invalid to pmap_copy page tables"));
3756 pml4e = pmap_pml4e(src_pmap, addr);
3757 if ((*pml4e & PG_V) == 0) {
3758 va_next = (addr + NBPML4) & ~PML4MASK;
3764 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
3765 if ((*pdpe & PG_V) == 0) {
3766 va_next = (addr + NBPDP) & ~PDPMASK;
3772 va_next = (addr + NBPDR) & ~PDRMASK;
3776 pde = pmap_pdpe_to_pde(pdpe, addr);
3778 if (srcptepaddr == 0)
3781 if (srcptepaddr & PG_PS) {
3782 dstmpde = pmap_allocpde(dst_pmap, addr, M_NOWAIT);
3783 if (dstmpde == NULL)
3785 pde = (pd_entry_t *)
3786 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
3787 pde = &pde[pmap_pde_index(addr)];
3788 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
3789 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
3791 *pde = srcptepaddr & ~PG_W;
3792 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
3794 dstmpde->wire_count--;
3798 srcptepaddr &= PG_FRAME;
3799 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
3800 KASSERT(srcmpte->wire_count > 0,
3801 ("pmap_copy: source page table page is unused"));
3803 if (va_next > end_addr)
3806 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
3807 src_pte = &src_pte[pmap_pte_index(addr)];
3809 while (addr < va_next) {
3813 * we only virtual copy managed pages
3815 if ((ptetemp & PG_MANAGED) != 0) {
3816 if (dstmpte != NULL &&
3817 dstmpte->pindex == pmap_pde_pindex(addr))
3818 dstmpte->wire_count++;
3819 else if ((dstmpte = pmap_allocpte(dst_pmap,
3820 addr, M_NOWAIT)) == NULL)
3822 dst_pte = (pt_entry_t *)
3823 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
3824 dst_pte = &dst_pte[pmap_pte_index(addr)];
3825 if (*dst_pte == 0 &&
3826 pmap_try_insert_pv_entry(dst_pmap, addr,
3827 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
3829 * Clear the wired, modified, and
3830 * accessed (referenced) bits
3833 *dst_pte = ptetemp & ~(PG_W | PG_M |
3835 pmap_resident_count_inc(dst_pmap, 1);
3838 if (pmap_unwire_pte_hold(dst_pmap,
3839 addr, dstmpte, &free)) {
3840 pmap_invalidate_page(dst_pmap,
3842 pmap_free_zero_pages(free);
3846 if (dstmpte->wire_count >= srcmpte->wire_count)
3854 vm_page_unlock_queues();
3855 PMAP_UNLOCK(src_pmap);
3856 PMAP_UNLOCK(dst_pmap);
3860 * pmap_zero_page zeros the specified hardware page by mapping
3861 * the page into KVM and using bzero to clear its contents.
3864 pmap_zero_page(vm_page_t m)
3866 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3868 pagezero((void *)va);
3872 * pmap_zero_page_area zeros the specified hardware page by mapping
3873 * the page into KVM and using bzero to clear its contents.
3875 * off and size may not cover an area beyond a single hardware page.
3878 pmap_zero_page_area(vm_page_t m, int off, int size)
3880 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3882 if (off == 0 && size == PAGE_SIZE)
3883 pagezero((void *)va);
3885 bzero((char *)va + off, size);
3889 * pmap_zero_page_idle zeros the specified hardware page by mapping
3890 * the page into KVM and using bzero to clear its contents. This
3891 * is intended to be called from the vm_pagezero process only and
3895 pmap_zero_page_idle(vm_page_t m)
3897 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3899 pagezero((void *)va);
3903 * pmap_copy_page copies the specified (machine independent)
3904 * page by mapping the page into virtual memory and using
3905 * bcopy to copy the page, one machine dependent page at a
3909 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3911 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3912 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3914 pagecopy((void *)src, (void *)dst);
3918 * Returns true if the pmap's pv is one of the first
3919 * 16 pvs linked to from this page. This count may
3920 * be changed upwards or downwards in the future; it
3921 * is only necessary that true be returned for a small
3922 * subset of pmaps for proper page aging.
3925 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3927 struct md_page *pvh;
3932 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3933 ("pmap_page_exists_quick: page %p is not managed", m));
3935 vm_page_lock_queues();
3936 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3937 if (PV_PMAP(pv) == pmap) {
3945 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3946 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3947 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
3948 if (PV_PMAP(pv) == pmap) {
3957 vm_page_unlock_queues();
3962 * pmap_page_wired_mappings:
3964 * Return the number of managed mappings to the given physical page
3968 pmap_page_wired_mappings(vm_page_t m)
3973 if ((m->oflags & VPO_UNMANAGED) != 0)
3975 vm_page_lock_queues();
3976 count = pmap_pvh_wired_mappings(&m->md, count);
3977 if ((m->flags & PG_FICTITIOUS) == 0) {
3978 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
3981 vm_page_unlock_queues();
3986 * pmap_pvh_wired_mappings:
3988 * Return the updated number "count" of managed mappings that are wired.
3991 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
3997 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3998 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4001 pte = pmap_pte(pmap, pv->pv_va);
4002 if ((*pte & PG_W) != 0)
4010 * Returns TRUE if the given page is mapped individually or as part of
4011 * a 2mpage. Otherwise, returns FALSE.
4014 pmap_page_is_mapped(vm_page_t m)
4018 if ((m->oflags & VPO_UNMANAGED) != 0)
4020 vm_page_lock_queues();
4021 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4022 ((m->flags & PG_FICTITIOUS) == 0 &&
4023 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4024 vm_page_unlock_queues();
4029 * Remove all pages from specified address space
4030 * this aids process exit speeds. Also, this code
4031 * is special cased for current process only, but
4032 * can have the more generic (and slightly slower)
4033 * mode enabled. This is much faster than pmap_remove
4034 * in the case of running down an entire address space.
4037 pmap_remove_pages(pmap_t pmap)
4040 pt_entry_t *pte, tpte;
4041 vm_page_t free = NULL;
4042 vm_page_t m, mpte, mt;
4044 struct md_page *pvh;
4045 struct pv_chunk *pc, *npc;
4048 uint64_t inuse, bitmask;
4051 if (pmap != PCPU_GET(curpmap)) {
4052 printf("warning: pmap_remove_pages called with non-current pmap\n");
4055 vm_page_lock_queues();
4057 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4059 for (field = 0; field < _NPCM; field++) {
4060 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4061 while (inuse != 0) {
4063 bitmask = 1UL << bit;
4064 idx = field * 64 + bit;
4065 pv = &pc->pc_pventry[idx];
4068 pte = pmap_pdpe(pmap, pv->pv_va);
4070 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
4072 if ((tpte & (PG_PS | PG_V)) == PG_V) {
4074 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
4076 pte = &pte[pmap_pte_index(pv->pv_va)];
4077 tpte = *pte & ~PG_PTE_PAT;
4079 if ((tpte & PG_V) == 0)
4083 * We cannot remove wired pages from a process' mapping at this time
4090 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4091 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4092 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4093 m, (uintmax_t)m->phys_addr,
4096 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4097 m < &vm_page_array[vm_page_array_size],
4098 ("pmap_remove_pages: bad tpte %#jx",
4104 * Update the vm_page_t clean/reference bits.
4106 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4107 if ((tpte & PG_PS) != 0) {
4108 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4115 PV_STAT(pv_entry_frees++);
4116 PV_STAT(pv_entry_spare++);
4118 pc->pc_map[field] |= bitmask;
4119 if ((tpte & PG_PS) != 0) {
4120 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4121 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4122 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4123 if (TAILQ_EMPTY(&pvh->pv_list)) {
4124 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4125 if (TAILQ_EMPTY(&mt->md.pv_list))
4126 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4128 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4130 pmap_remove_pt_page(pmap, mpte);
4131 pmap_resident_count_dec(pmap, 1);
4132 KASSERT(mpte->wire_count == NPTEPG,
4133 ("pmap_remove_pages: pte page wire count error"));
4134 mpte->wire_count = 0;
4135 pmap_add_delayed_free_list(mpte, &free, FALSE);
4136 atomic_subtract_int(&cnt.v_wire_count, 1);
4139 pmap_resident_count_dec(pmap, 1);
4140 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4141 if (TAILQ_EMPTY(&m->md.pv_list) &&
4142 (m->flags & PG_FICTITIOUS) == 0) {
4143 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4144 if (TAILQ_EMPTY(&pvh->pv_list))
4145 vm_page_aflag_clear(m, PGA_WRITEABLE);
4148 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
4152 PV_STAT(pv_entry_spare -= _NPCPV);
4153 PV_STAT(pc_chunk_count--);
4154 PV_STAT(pc_chunk_frees++);
4155 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4156 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4157 dump_drop_page(m->phys_addr);
4158 vm_page_unwire(m, 0);
4162 pmap_invalidate_all(pmap);
4163 vm_page_unlock_queues();
4165 pmap_free_zero_pages(free);
4171 * Return whether or not the specified physical page was modified
4172 * in any physical maps.
4175 pmap_is_modified(vm_page_t m)
4179 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4180 ("pmap_is_modified: page %p is not managed", m));
4183 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4184 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4185 * is clear, no PTEs can have PG_M set.
4187 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4188 if ((m->oflags & VPO_BUSY) == 0 &&
4189 (m->aflags & PGA_WRITEABLE) == 0)
4191 vm_page_lock_queues();
4192 rv = pmap_is_modified_pvh(&m->md) ||
4193 ((m->flags & PG_FICTITIOUS) == 0 &&
4194 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4195 vm_page_unlock_queues();
4200 * Returns TRUE if any of the given mappings were used to modify
4201 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4202 * mappings are supported.
4205 pmap_is_modified_pvh(struct md_page *pvh)
4212 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4214 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4217 pte = pmap_pte(pmap, pv->pv_va);
4218 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4227 * pmap_is_prefaultable:
4229 * Return whether or not the specified virtual address is elgible
4233 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4241 pde = pmap_pde(pmap, addr);
4242 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
4243 pte = pmap_pde_to_pte(pde, addr);
4244 rv = (*pte & PG_V) == 0;
4251 * pmap_is_referenced:
4253 * Return whether or not the specified physical page was referenced
4254 * in any physical maps.
4257 pmap_is_referenced(vm_page_t m)
4261 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4262 ("pmap_is_referenced: page %p is not managed", m));
4263 vm_page_lock_queues();
4264 rv = pmap_is_referenced_pvh(&m->md) ||
4265 ((m->flags & PG_FICTITIOUS) == 0 &&
4266 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4267 vm_page_unlock_queues();
4272 * Returns TRUE if any of the given mappings were referenced and FALSE
4273 * otherwise. Both page and 2mpage mappings are supported.
4276 pmap_is_referenced_pvh(struct md_page *pvh)
4283 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4285 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4288 pte = pmap_pte(pmap, pv->pv_va);
4289 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4298 * Clear the write and modified bits in each of the given page's mappings.
4301 pmap_remove_write(vm_page_t m)
4303 struct md_page *pvh;
4305 pv_entry_t next_pv, pv;
4307 pt_entry_t oldpte, *pte;
4310 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4311 ("pmap_remove_write: page %p is not managed", m));
4314 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4315 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4316 * is clear, no page table entries need updating.
4318 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4319 if ((m->oflags & VPO_BUSY) == 0 &&
4320 (m->aflags & PGA_WRITEABLE) == 0)
4322 vm_page_lock_queues();
4323 if ((m->flags & PG_FICTITIOUS) != 0)
4324 goto small_mappings;
4325 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4326 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4330 pde = pmap_pde(pmap, va);
4331 if ((*pde & PG_RW) != 0)
4332 (void)pmap_demote_pde(pmap, pde, va);
4336 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4339 pde = pmap_pde(pmap, pv->pv_va);
4340 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4341 " a 2mpage in page %p's pv list", m));
4342 pte = pmap_pde_to_pte(pde, pv->pv_va);
4345 if (oldpte & PG_RW) {
4346 if (!atomic_cmpset_long(pte, oldpte, oldpte &
4349 if ((oldpte & PG_M) != 0)
4351 pmap_invalidate_page(pmap, pv->pv_va);
4355 vm_page_aflag_clear(m, PGA_WRITEABLE);
4356 vm_page_unlock_queues();
4360 * pmap_ts_referenced:
4362 * Return a count of reference bits for a page, clearing those bits.
4363 * It is not necessary for every reference bit to be cleared, but it
4364 * is necessary that 0 only be returned when there are truly no
4365 * reference bits set.
4367 * XXX: The exact number of bits to check and clear is a matter that
4368 * should be tested and standardized at some point in the future for
4369 * optimal aging of shared pages.
4372 pmap_ts_referenced(vm_page_t m)
4374 struct md_page *pvh;
4375 pv_entry_t pv, pvf, pvn;
4377 pd_entry_t oldpde, *pde;
4382 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4383 ("pmap_ts_referenced: page %p is not managed", m));
4384 vm_page_lock_queues();
4385 if ((m->flags & PG_FICTITIOUS) != 0)
4386 goto small_mappings;
4387 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4388 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4392 pde = pmap_pde(pmap, va);
4394 if ((oldpde & PG_A) != 0) {
4395 if (pmap_demote_pde(pmap, pde, va)) {
4396 if ((oldpde & PG_W) == 0) {
4398 * Remove the mapping to a single page
4399 * so that a subsequent access may
4400 * repromote. Since the underlying
4401 * page table page is fully populated,
4402 * this removal never frees a page
4405 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4407 pmap_remove_page(pmap, va, pde, NULL);
4419 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4422 pvn = TAILQ_NEXT(pv, pv_list);
4423 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4424 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4427 pde = pmap_pde(pmap, pv->pv_va);
4428 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4429 " found a 2mpage in page %p's pv list", m));
4430 pte = pmap_pde_to_pte(pde, pv->pv_va);
4431 if ((*pte & PG_A) != 0) {
4432 atomic_clear_long(pte, PG_A);
4433 pmap_invalidate_page(pmap, pv->pv_va);
4439 } while ((pv = pvn) != NULL && pv != pvf);
4442 vm_page_unlock_queues();
4447 * Clear the modify bits on the specified physical page.
4450 pmap_clear_modify(vm_page_t m)
4452 struct md_page *pvh;
4454 pv_entry_t next_pv, pv;
4455 pd_entry_t oldpde, *pde;
4456 pt_entry_t oldpte, *pte;
4459 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4460 ("pmap_clear_modify: page %p is not managed", m));
4461 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4462 KASSERT((m->oflags & VPO_BUSY) == 0,
4463 ("pmap_clear_modify: page %p is busy", m));
4466 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4467 * If the object containing the page is locked and the page is not
4468 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4470 if ((m->aflags & PGA_WRITEABLE) == 0)
4472 vm_page_lock_queues();
4473 if ((m->flags & PG_FICTITIOUS) != 0)
4474 goto small_mappings;
4475 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4476 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4480 pde = pmap_pde(pmap, va);
4482 if ((oldpde & PG_RW) != 0) {
4483 if (pmap_demote_pde(pmap, pde, va)) {
4484 if ((oldpde & PG_W) == 0) {
4486 * Write protect the mapping to a
4487 * single page so that a subsequent
4488 * write access may repromote.
4490 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4492 pte = pmap_pde_to_pte(pde, va);
4494 if ((oldpte & PG_V) != 0) {
4495 while (!atomic_cmpset_long(pte,
4497 oldpte & ~(PG_M | PG_RW)))
4500 pmap_invalidate_page(pmap, va);
4508 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4511 pde = pmap_pde(pmap, pv->pv_va);
4512 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4513 " a 2mpage in page %p's pv list", m));
4514 pte = pmap_pde_to_pte(pde, pv->pv_va);
4515 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4516 atomic_clear_long(pte, PG_M);
4517 pmap_invalidate_page(pmap, pv->pv_va);
4521 vm_page_unlock_queues();
4525 * pmap_clear_reference:
4527 * Clear the reference bit on the specified physical page.
4530 pmap_clear_reference(vm_page_t m)
4532 struct md_page *pvh;
4534 pv_entry_t next_pv, pv;
4535 pd_entry_t oldpde, *pde;
4539 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4540 ("pmap_clear_reference: page %p is not managed", m));
4541 vm_page_lock_queues();
4542 if ((m->flags & PG_FICTITIOUS) != 0)
4543 goto small_mappings;
4544 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4545 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4549 pde = pmap_pde(pmap, va);
4551 if ((oldpde & PG_A) != 0) {
4552 if (pmap_demote_pde(pmap, pde, va)) {
4554 * Remove the mapping to a single page so
4555 * that a subsequent access may repromote.
4556 * Since the underlying page table page is
4557 * fully populated, this removal never frees
4558 * a page table page.
4560 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4562 pmap_remove_page(pmap, va, pde, NULL);
4568 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4571 pde = pmap_pde(pmap, pv->pv_va);
4572 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4573 " a 2mpage in page %p's pv list", m));
4574 pte = pmap_pde_to_pte(pde, pv->pv_va);
4576 atomic_clear_long(pte, PG_A);
4577 pmap_invalidate_page(pmap, pv->pv_va);
4581 vm_page_unlock_queues();
4585 * Miscellaneous support routines follow
4588 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4589 static __inline void
4590 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4595 * The cache mode bits are all in the low 32-bits of the
4596 * PTE, so we can just spin on updating the low 32-bits.
4599 opte = *(u_int *)pte;
4600 npte = opte & ~PG_PTE_CACHE;
4602 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4605 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
4606 static __inline void
4607 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4612 * The cache mode bits are all in the low 32-bits of the
4613 * PDE, so we can just spin on updating the low 32-bits.
4616 opde = *(u_int *)pde;
4617 npde = opde & ~PG_PDE_CACHE;
4619 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4623 * Map a set of physical memory pages into the kernel virtual
4624 * address space. Return a pointer to where it is mapped. This
4625 * routine is intended to be used for mapping device memory,
4629 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4631 vm_offset_t va, offset;
4635 * If the specified range of physical addresses fits within the direct
4636 * map window, use the direct map.
4638 if (pa < dmaplimit && pa + size < dmaplimit) {
4639 va = PHYS_TO_DMAP(pa);
4640 if (!pmap_change_attr(va, size, mode))
4641 return ((void *)va);
4643 offset = pa & PAGE_MASK;
4644 size = roundup(offset + size, PAGE_SIZE);
4645 va = kmem_alloc_nofault(kernel_map, size);
4647 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4648 pa = trunc_page(pa);
4649 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4650 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
4651 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
4652 pmap_invalidate_cache_range(va, va + tmpsize);
4653 return ((void *)(va + offset));
4657 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
4660 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
4664 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4667 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4671 pmap_unmapdev(vm_offset_t va, vm_size_t size)
4673 vm_offset_t base, offset, tmpva;
4675 /* If we gave a direct map region in pmap_mapdev, do nothing */
4676 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
4678 base = trunc_page(va);
4679 offset = va & PAGE_MASK;
4680 size = roundup(offset + size, PAGE_SIZE);
4681 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
4682 pmap_kremove(tmpva);
4683 pmap_invalidate_range(kernel_pmap, va, tmpva);
4684 kmem_free(kernel_map, base, size);
4688 * Tries to demote a 1GB page mapping.
4691 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
4693 pdp_entry_t newpdpe, oldpdpe;
4694 pd_entry_t *firstpde, newpde, *pde;
4698 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4700 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
4701 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
4702 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
4703 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4704 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
4705 " in pmap %p", va, pmap);
4708 mpdepa = VM_PAGE_TO_PHYS(mpde);
4709 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
4710 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
4711 KASSERT((oldpdpe & PG_A) != 0,
4712 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
4713 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
4714 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
4718 * Initialize the page directory page.
4720 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
4726 * Demote the mapping.
4731 * Invalidate a stale recursive mapping of the page directory page.
4733 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
4735 pmap_pdpe_demotions++;
4736 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
4737 " in pmap %p", va, pmap);
4742 * Sets the memory attribute for the specified page.
4745 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4748 m->md.pat_mode = ma;
4751 * If "m" is a normal page, update its direct mapping. This update
4752 * can be relied upon to perform any cache operations that are
4753 * required for data coherence.
4755 if ((m->flags & PG_FICTITIOUS) == 0 &&
4756 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4758 panic("memory attribute change on the direct map failed");
4762 * Changes the specified virtual address range's memory type to that given by
4763 * the parameter "mode". The specified virtual address range must be
4764 * completely contained within either the direct map or the kernel map. If
4765 * the virtual address range is contained within the kernel map, then the
4766 * memory type for each of the corresponding ranges of the direct map is also
4767 * changed. (The corresponding ranges of the direct map are those ranges that
4768 * map the same physical pages as the specified virtual address range.) These
4769 * changes to the direct map are necessary because Intel describes the
4770 * behavior of their processors as "undefined" if two or more mappings to the
4771 * same physical page have different memory types.
4773 * Returns zero if the change completed successfully, and either EINVAL or
4774 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4775 * of the virtual address range was not mapped, and ENOMEM is returned if
4776 * there was insufficient memory available to complete the change. In the
4777 * latter case, the memory type may have been changed on some part of the
4778 * virtual address range or the direct map.
4781 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4785 PMAP_LOCK(kernel_pmap);
4786 error = pmap_change_attr_locked(va, size, mode);
4787 PMAP_UNLOCK(kernel_pmap);
4792 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4794 vm_offset_t base, offset, tmpva;
4795 vm_paddr_t pa_start, pa_end;
4799 int cache_bits_pte, cache_bits_pde, error;
4802 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4803 base = trunc_page(va);
4804 offset = va & PAGE_MASK;
4805 size = roundup(offset + size, PAGE_SIZE);
4808 * Only supported on kernel virtual addresses, including the direct
4809 * map but excluding the recursive map.
4811 if (base < DMAP_MIN_ADDRESS)
4814 cache_bits_pde = pmap_cache_bits(mode, 1);
4815 cache_bits_pte = pmap_cache_bits(mode, 0);
4819 * Pages that aren't mapped aren't supported. Also break down 2MB pages
4820 * into 4KB pages if required.
4822 for (tmpva = base; tmpva < base + size; ) {
4823 pdpe = pmap_pdpe(kernel_pmap, tmpva);
4826 if (*pdpe & PG_PS) {
4828 * If the current 1GB page already has the required
4829 * memory type, then we need not demote this page. Just
4830 * increment tmpva to the next 1GB page frame.
4832 if ((*pdpe & PG_PDE_CACHE) == cache_bits_pde) {
4833 tmpva = trunc_1gpage(tmpva) + NBPDP;
4838 * If the current offset aligns with a 1GB page frame
4839 * and there is at least 1GB left within the range, then
4840 * we need not break down this page into 2MB pages.
4842 if ((tmpva & PDPMASK) == 0 &&
4843 tmpva + PDPMASK < base + size) {
4847 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
4850 pde = pmap_pdpe_to_pde(pdpe, tmpva);
4855 * If the current 2MB page already has the required
4856 * memory type, then we need not demote this page. Just
4857 * increment tmpva to the next 2MB page frame.
4859 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
4860 tmpva = trunc_2mpage(tmpva) + NBPDR;
4865 * If the current offset aligns with a 2MB page frame
4866 * and there is at least 2MB left within the range, then
4867 * we need not break down this page into 4KB pages.
4869 if ((tmpva & PDRMASK) == 0 &&
4870 tmpva + PDRMASK < base + size) {
4874 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
4877 pte = pmap_pde_to_pte(pde, tmpva);
4885 * Ok, all the pages exist, so run through them updating their
4886 * cache mode if required.
4888 pa_start = pa_end = 0;
4889 for (tmpva = base; tmpva < base + size; ) {
4890 pdpe = pmap_pdpe(kernel_pmap, tmpva);
4891 if (*pdpe & PG_PS) {
4892 if ((*pdpe & PG_PDE_CACHE) != cache_bits_pde) {
4893 pmap_pde_attr(pdpe, cache_bits_pde);
4896 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
4897 if (pa_start == pa_end) {
4898 /* Start physical address run. */
4899 pa_start = *pdpe & PG_PS_FRAME;
4900 pa_end = pa_start + NBPDP;
4901 } else if (pa_end == (*pdpe & PG_PS_FRAME))
4904 /* Run ended, update direct map. */
4905 error = pmap_change_attr_locked(
4906 PHYS_TO_DMAP(pa_start),
4907 pa_end - pa_start, mode);
4910 /* Start physical address run. */
4911 pa_start = *pdpe & PG_PS_FRAME;
4912 pa_end = pa_start + NBPDP;
4915 tmpva = trunc_1gpage(tmpva) + NBPDP;
4918 pde = pmap_pdpe_to_pde(pdpe, tmpva);
4920 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
4921 pmap_pde_attr(pde, cache_bits_pde);
4924 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
4925 if (pa_start == pa_end) {
4926 /* Start physical address run. */
4927 pa_start = *pde & PG_PS_FRAME;
4928 pa_end = pa_start + NBPDR;
4929 } else if (pa_end == (*pde & PG_PS_FRAME))
4932 /* Run ended, update direct map. */
4933 error = pmap_change_attr_locked(
4934 PHYS_TO_DMAP(pa_start),
4935 pa_end - pa_start, mode);
4938 /* Start physical address run. */
4939 pa_start = *pde & PG_PS_FRAME;
4940 pa_end = pa_start + NBPDR;
4943 tmpva = trunc_2mpage(tmpva) + NBPDR;
4945 pte = pmap_pde_to_pte(pde, tmpva);
4946 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
4947 pmap_pte_attr(pte, cache_bits_pte);
4950 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
4951 if (pa_start == pa_end) {
4952 /* Start physical address run. */
4953 pa_start = *pte & PG_FRAME;
4954 pa_end = pa_start + PAGE_SIZE;
4955 } else if (pa_end == (*pte & PG_FRAME))
4956 pa_end += PAGE_SIZE;
4958 /* Run ended, update direct map. */
4959 error = pmap_change_attr_locked(
4960 PHYS_TO_DMAP(pa_start),
4961 pa_end - pa_start, mode);
4964 /* Start physical address run. */
4965 pa_start = *pte & PG_FRAME;
4966 pa_end = pa_start + PAGE_SIZE;
4972 if (error == 0 && pa_start != pa_end)
4973 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
4974 pa_end - pa_start, mode);
4977 * Flush CPU caches if required to make sure any data isn't cached that
4978 * shouldn't be, etc.
4981 pmap_invalidate_range(kernel_pmap, base, tmpva);
4982 pmap_invalidate_cache_range(base, tmpva);
4988 * Demotes any mapping within the direct map region that covers more than the
4989 * specified range of physical addresses. This range's size must be a power
4990 * of two and its starting address must be a multiple of its size. Since the
4991 * demotion does not change any attributes of the mapping, a TLB invalidation
4992 * is not mandatory. The caller may, however, request a TLB invalidation.
4995 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
5004 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
5005 KASSERT((base & (len - 1)) == 0,
5006 ("pmap_demote_DMAP: base is not a multiple of len"));
5007 if (len < NBPDP && base < dmaplimit) {
5008 va = PHYS_TO_DMAP(base);
5010 PMAP_LOCK(kernel_pmap);
5011 pdpe = pmap_pdpe(kernel_pmap, va);
5012 if ((*pdpe & PG_V) == 0)
5013 panic("pmap_demote_DMAP: invalid PDPE");
5014 if ((*pdpe & PG_PS) != 0) {
5015 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
5016 panic("pmap_demote_DMAP: PDPE failed");
5020 pde = pmap_pdpe_to_pde(pdpe, va);
5021 if ((*pde & PG_V) == 0)
5022 panic("pmap_demote_DMAP: invalid PDE");
5023 if ((*pde & PG_PS) != 0) {
5024 if (!pmap_demote_pde(kernel_pmap, pde, va))
5025 panic("pmap_demote_DMAP: PDE failed");
5029 if (changed && invalidate)
5030 pmap_invalidate_page(kernel_pmap, va);
5031 PMAP_UNLOCK(kernel_pmap);
5036 * perform the pmap work for mincore
5039 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5048 pdep = pmap_pde(pmap, addr);
5049 if (pdep != NULL && (*pdep & PG_V)) {
5050 if (*pdep & PG_PS) {
5052 /* Compute the physical address of the 4KB page. */
5053 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5055 val = MINCORE_SUPER;
5057 pte = *pmap_pde_to_pte(pdep, addr);
5058 pa = pte & PG_FRAME;
5066 if ((pte & PG_V) != 0) {
5067 val |= MINCORE_INCORE;
5068 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5069 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5070 if ((pte & PG_A) != 0)
5071 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5073 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5074 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5075 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5076 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5077 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5080 PA_UNLOCK_COND(*locked_pa);
5086 pmap_activate(struct thread *td)
5088 pmap_t pmap, oldpmap;
5093 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5094 oldpmap = PCPU_GET(curpmap);
5095 cpuid = PCPU_GET(cpuid);
5097 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5098 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5100 CPU_CLR(cpuid, &oldpmap->pm_active);
5101 CPU_SET(cpuid, &pmap->pm_active);
5103 cr3 = DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4);
5104 td->td_pcb->pcb_cr3 = cr3;
5106 PCPU_SET(curpmap, pmap);
5111 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5116 * Increase the starting virtual address of the given mapping if a
5117 * different alignment might result in more superpage mappings.
5120 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5121 vm_offset_t *addr, vm_size_t size)
5123 vm_offset_t superpage_offset;
5127 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5128 offset += ptoa(object->pg_color);
5129 superpage_offset = offset & PDRMASK;
5130 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5131 (*addr & PDRMASK) == superpage_offset)
5133 if ((*addr & PDRMASK) < superpage_offset)
5134 *addr = (*addr & ~PDRMASK) + superpage_offset;
5136 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;