2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
48 * Copyright (c) 2003 Networks Associates Technology, Inc.
49 * All rights reserved.
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
66 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
69 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
79 #define AMD64_NPT_AWARE
81 #include <sys/cdefs.h>
82 __FBSDID("$FreeBSD$");
85 * Manages physical address maps.
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
103 #include "opt_pmap.h"
106 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/kernel.h>
111 #include <sys/lock.h>
112 #include <sys/malloc.h>
113 #include <sys/mman.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/_unrhdr.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
132 #include <vm/vm_pager.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
137 #include <machine/intr_machdep.h>
138 #include <machine/apicvar.h>
139 #include <machine/cpu.h>
140 #include <machine/cputypes.h>
141 #include <machine/md_var.h>
142 #include <machine/pcb.h>
143 #include <machine/specialreg.h>
145 #include <machine/smp.h>
148 static __inline boolean_t
149 pmap_emulate_ad_bits(pmap_t pmap)
152 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
155 static __inline pt_entry_t
156 pmap_valid_bit(pmap_t pmap)
160 switch (pmap->pm_type) {
165 if (pmap_emulate_ad_bits(pmap))
166 mask = EPT_PG_EMUL_V;
171 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
177 static __inline pt_entry_t
178 pmap_rw_bit(pmap_t pmap)
182 switch (pmap->pm_type) {
187 if (pmap_emulate_ad_bits(pmap))
188 mask = EPT_PG_EMUL_RW;
193 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
199 static __inline pt_entry_t
200 pmap_global_bit(pmap_t pmap)
204 switch (pmap->pm_type) {
212 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
218 static __inline pt_entry_t
219 pmap_accessed_bit(pmap_t pmap)
223 switch (pmap->pm_type) {
228 if (pmap_emulate_ad_bits(pmap))
234 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
240 static __inline pt_entry_t
241 pmap_modified_bit(pmap_t pmap)
245 switch (pmap->pm_type) {
250 if (pmap_emulate_ad_bits(pmap))
256 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
262 #if !defined(DIAGNOSTIC)
263 #ifdef __GNUC_GNU_INLINE__
264 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
266 #define PMAP_INLINE extern inline
273 #define PV_STAT(x) do { x ; } while (0)
275 #define PV_STAT(x) do { } while (0)
278 #define pa_index(pa) ((pa) >> PDRSHIFT)
279 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
281 #define NPV_LIST_LOCKS MAXCPU
283 #define PHYS_TO_PV_LIST_LOCK(pa) \
284 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
286 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
287 struct rwlock **_lockp = (lockp); \
288 struct rwlock *_new_lock; \
290 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
291 if (_new_lock != *_lockp) { \
292 if (*_lockp != NULL) \
293 rw_wunlock(*_lockp); \
294 *_lockp = _new_lock; \
299 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
300 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
302 #define RELEASE_PV_LIST_LOCK(lockp) do { \
303 struct rwlock **_lockp = (lockp); \
305 if (*_lockp != NULL) { \
306 rw_wunlock(*_lockp); \
311 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
312 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
314 struct pmap kernel_pmap_store;
316 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
317 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
320 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
321 "Number of kernel page table pages allocated on bootup");
324 vm_paddr_t dmaplimit;
325 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
328 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
330 static int pat_works = 1;
331 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
332 "Is page attribute table fully functional?");
334 static int pg_ps_enabled = 1;
335 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
336 "Are large page mappings enabled?");
338 #define PAT_INDEX_SIZE 8
339 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
341 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
342 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
343 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
344 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
346 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
347 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
348 static int ndmpdpphys; /* number of DMPDPphys pages */
350 static struct rwlock_padalign pvh_global_lock;
353 * Data for the pv entry allocation mechanism
355 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
356 static struct mtx pv_chunks_mutex;
357 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
358 static struct md_page *pv_table;
361 * All those kernel PT submaps that BSD is so fond of
363 pt_entry_t *CMAP1 = 0;
366 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
368 static struct unrhdr pcid_unr;
369 static struct mtx pcid_mtx;
370 int pmap_pcid_enabled = 0;
371 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN, &pmap_pcid_enabled,
372 0, "Is TLB Context ID enabled ?");
373 int invpcid_works = 0;
374 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
375 "Is the invpcid instruction available ?");
378 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
385 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
387 return (sysctl_handle_64(oidp, &res, 0, req));
389 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RW |
390 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
391 "Count of saved TLB context on switch");
393 /* pmap_copy_pages() over non-DMAP */
394 static struct mtx cpage_lock;
395 static vm_offset_t cpage_a;
396 static vm_offset_t cpage_b;
401 static caddr_t crashdumpmap;
403 static void free_pv_chunk(struct pv_chunk *pc);
404 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
405 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
406 static int popcnt_pc_map_elem(uint64_t elem);
407 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
408 static void reserve_pv_entries(pmap_t pmap, int needed,
409 struct rwlock **lockp);
410 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
411 struct rwlock **lockp);
412 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
413 struct rwlock **lockp);
414 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
415 struct rwlock **lockp);
416 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
417 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
420 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
421 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
422 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
423 vm_offset_t va, struct rwlock **lockp);
424 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
426 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
427 vm_prot_t prot, struct rwlock **lockp);
428 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
429 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
430 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
431 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
432 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
433 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
434 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
435 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
436 struct rwlock **lockp);
437 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
439 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
440 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
441 struct spglist *free, struct rwlock **lockp);
442 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
443 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
444 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
445 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
446 struct spglist *free);
447 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
448 vm_page_t m, struct rwlock **lockp);
449 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
451 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
453 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
454 struct rwlock **lockp);
455 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
456 struct rwlock **lockp);
457 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
458 struct rwlock **lockp);
460 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
461 struct spglist *free);
462 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
463 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
466 * Move the kernel virtual free pointer to the next
467 * 2MB. This is used to help improve performance
468 * by using a large (2MB) page for much of the kernel
469 * (.text, .data, .bss)
472 pmap_kmem_choose(vm_offset_t addr)
474 vm_offset_t newaddr = addr;
476 newaddr = (addr + (NBPDR - 1)) & ~(NBPDR - 1);
480 /********************/
481 /* Inline functions */
482 /********************/
484 /* Return a non-clipped PD index for a given VA */
485 static __inline vm_pindex_t
486 pmap_pde_pindex(vm_offset_t va)
488 return (va >> PDRSHIFT);
492 /* Return various clipped indexes for a given VA */
493 static __inline vm_pindex_t
494 pmap_pte_index(vm_offset_t va)
497 return ((va >> PAGE_SHIFT) & ((1ul << NPTEPGSHIFT) - 1));
500 static __inline vm_pindex_t
501 pmap_pde_index(vm_offset_t va)
504 return ((va >> PDRSHIFT) & ((1ul << NPDEPGSHIFT) - 1));
507 static __inline vm_pindex_t
508 pmap_pdpe_index(vm_offset_t va)
511 return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1));
514 static __inline vm_pindex_t
515 pmap_pml4e_index(vm_offset_t va)
518 return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1));
521 /* Return a pointer to the PML4 slot that corresponds to a VA */
522 static __inline pml4_entry_t *
523 pmap_pml4e(pmap_t pmap, vm_offset_t va)
526 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
529 /* Return a pointer to the PDP slot that corresponds to a VA */
530 static __inline pdp_entry_t *
531 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
535 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
536 return (&pdpe[pmap_pdpe_index(va)]);
539 /* Return a pointer to the PDP slot that corresponds to a VA */
540 static __inline pdp_entry_t *
541 pmap_pdpe(pmap_t pmap, vm_offset_t va)
546 PG_V = pmap_valid_bit(pmap);
547 pml4e = pmap_pml4e(pmap, va);
548 if ((*pml4e & PG_V) == 0)
550 return (pmap_pml4e_to_pdpe(pml4e, va));
553 /* Return a pointer to the PD slot that corresponds to a VA */
554 static __inline pd_entry_t *
555 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
559 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
560 return (&pde[pmap_pde_index(va)]);
563 /* Return a pointer to the PD slot that corresponds to a VA */
564 static __inline pd_entry_t *
565 pmap_pde(pmap_t pmap, vm_offset_t va)
570 PG_V = pmap_valid_bit(pmap);
571 pdpe = pmap_pdpe(pmap, va);
572 if (pdpe == NULL || (*pdpe & PG_V) == 0)
574 return (pmap_pdpe_to_pde(pdpe, va));
577 /* Return a pointer to the PT slot that corresponds to a VA */
578 static __inline pt_entry_t *
579 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
583 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
584 return (&pte[pmap_pte_index(va)]);
587 /* Return a pointer to the PT slot that corresponds to a VA */
588 static __inline pt_entry_t *
589 pmap_pte(pmap_t pmap, vm_offset_t va)
594 PG_V = pmap_valid_bit(pmap);
595 pde = pmap_pde(pmap, va);
596 if (pde == NULL || (*pde & PG_V) == 0)
598 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
599 return ((pt_entry_t *)pde);
600 return (pmap_pde_to_pte(pde, va));
604 pmap_resident_count_inc(pmap_t pmap, int count)
607 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
608 pmap->pm_stats.resident_count += count;
612 pmap_resident_count_dec(pmap_t pmap, int count)
615 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
616 KASSERT(pmap->pm_stats.resident_count >= count,
617 ("pmap %p resident count underflow %ld %d", pmap,
618 pmap->pm_stats.resident_count, count));
619 pmap->pm_stats.resident_count -= count;
622 PMAP_INLINE pt_entry_t *
623 vtopte(vm_offset_t va)
625 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
627 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
629 return (PTmap + ((va >> PAGE_SHIFT) & mask));
632 static __inline pd_entry_t *
633 vtopde(vm_offset_t va)
635 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
637 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
639 return (PDmap + ((va >> PDRSHIFT) & mask));
643 allocpages(vm_paddr_t *firstaddr, int n)
648 bzero((void *)ret, n * PAGE_SIZE);
649 *firstaddr += n * PAGE_SIZE;
653 CTASSERT(powerof2(NDMPML4E));
655 /* number of kernel PDP slots */
656 #define NKPDPE(ptpgs) howmany((ptpgs), NPDEPG)
659 nkpt_init(vm_paddr_t addr)
666 pt_pages = howmany(addr, 1 << PDRSHIFT);
667 pt_pages += NKPDPE(pt_pages);
670 * Add some slop beyond the bare minimum required for bootstrapping
673 * This is quite important when allocating KVA for kernel modules.
674 * The modules are required to be linked in the negative 2GB of
675 * the address space. If we run out of KVA in this region then
676 * pmap_growkernel() will need to allocate page table pages to map
677 * the entire 512GB of KVA space which is an unnecessary tax on
680 pt_pages += 8; /* 16MB additional slop for kernel modules */
686 create_pagetables(vm_paddr_t *firstaddr)
688 int i, j, ndm1g, nkpdpe;
694 /* Allocate page table pages for the direct map */
695 ndmpdp = (ptoa(Maxmem) + NBPDP - 1) >> PDPSHIFT;
696 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
698 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
699 if (ndmpdpphys > NDMPML4E) {
701 * Each NDMPML4E allows 512 GB, so limit to that,
702 * and then readjust ndmpdp and ndmpdpphys.
704 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
705 Maxmem = atop(NDMPML4E * NBPML4);
706 ndmpdpphys = NDMPML4E;
707 ndmpdp = NDMPML4E * NPDEPG;
709 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
711 if ((amd_feature & AMDID_PAGE1GB) != 0)
712 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
714 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
715 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
718 KPML4phys = allocpages(firstaddr, 1);
719 KPDPphys = allocpages(firstaddr, NKPML4E);
722 * Allocate the initial number of kernel page table pages required to
723 * bootstrap. We defer this until after all memory-size dependent
724 * allocations are done (e.g. direct map), so that we don't have to
725 * build in too much slop in our estimate.
727 * Note that when NKPML4E > 1, we have an empty page underneath
728 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
729 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
731 nkpt_init(*firstaddr);
732 nkpdpe = NKPDPE(nkpt);
734 KPTphys = allocpages(firstaddr, nkpt);
735 KPDphys = allocpages(firstaddr, nkpdpe);
737 /* Fill in the underlying page table pages */
738 /* Nominally read-only (but really R/W) from zero to physfree */
739 /* XXX not fully used, underneath 2M pages */
740 pt_p = (pt_entry_t *)KPTphys;
741 for (i = 0; ptoa(i) < *firstaddr; i++)
742 pt_p[i] = ptoa(i) | X86_PG_RW | X86_PG_V | X86_PG_G;
744 /* Now map the page tables at their location within PTmap */
745 pd_p = (pd_entry_t *)KPDphys;
746 for (i = 0; i < nkpt; i++)
747 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
749 /* Map from zero to end of allocations under 2M pages */
750 /* This replaces some of the KPTphys entries above */
751 for (i = 0; (i << PDRSHIFT) < *firstaddr; i++)
752 pd_p[i] = (i << PDRSHIFT) | X86_PG_RW | X86_PG_V | PG_PS |
755 /* And connect up the PD to the PDP (leaving room for L4 pages) */
756 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
757 for (i = 0; i < nkpdpe; i++)
758 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V |
762 * Now, set up the direct map region using 2MB and/or 1GB pages. If
763 * the end of physical memory is not aligned to a 1GB page boundary,
764 * then the residual physical memory is mapped with 2MB pages. Later,
765 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
766 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
767 * that are partially used.
769 pd_p = (pd_entry_t *)DMPDphys;
770 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
771 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
772 /* Preset PG_M and PG_A because demotion expects it. */
773 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
776 pdp_p = (pdp_entry_t *)DMPDPphys;
777 for (i = 0; i < ndm1g; i++) {
778 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
779 /* Preset PG_M and PG_A because demotion expects it. */
780 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | X86_PG_G |
783 for (j = 0; i < ndmpdp; i++, j++) {
784 pdp_p[i] = DMPDphys + ptoa(j);
785 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_U;
788 /* And recursively map PML4 to itself in order to get PTmap */
789 p4_p = (pml4_entry_t *)KPML4phys;
790 p4_p[PML4PML4I] = KPML4phys;
791 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | PG_U;
793 /* Connect the Direct Map slot(s) up to the PML4. */
794 for (i = 0; i < ndmpdpphys; i++) {
795 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
796 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | PG_U;
799 /* Connect the KVA slots up to the PML4 */
800 for (i = 0; i < NKPML4E; i++) {
801 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
802 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V | PG_U;
807 * Bootstrap the system enough to run with virtual memory.
809 * On amd64 this is called after mapping has already been enabled
810 * and just syncs the pmap module with what has already been done.
811 * [We can't call it easily with mapping off since the kernel is not
812 * mapped with PA == VA, hence we would have to relocate every address
813 * from the linked base (virtual) address "KERNBASE" to the actual
814 * (physical) address starting relative to 0]
817 pmap_bootstrap(vm_paddr_t *firstaddr)
823 * Create an initial set of page tables to run the kernel in.
825 create_pagetables(firstaddr);
827 virtual_avail = (vm_offset_t) KERNBASE + *firstaddr;
828 virtual_avail = pmap_kmem_choose(virtual_avail);
830 virtual_end = VM_MAX_KERNEL_ADDRESS;
833 /* XXX do %cr0 as well */
834 load_cr4(rcr4() | CR4_PGE | CR4_PSE);
836 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
837 load_cr4(rcr4() | CR4_SMEP);
840 * Initialize the kernel pmap (which is statically allocated).
842 PMAP_LOCK_INIT(kernel_pmap);
843 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
844 kernel_pmap->pm_cr3 = KPML4phys;
845 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
846 CPU_FILL(&kernel_pmap->pm_save); /* always superset of pm_active */
847 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
848 kernel_pmap->pm_flags = pmap_flags;
851 * Initialize the global pv list lock.
853 rw_init(&pvh_global_lock, "pmap pv global");
856 * Reserve some special page table entries/VA space for temporary
859 #define SYSMAP(c, p, v, n) \
860 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
866 * Crashdump maps. The first page is reused as CMAP1 for the
869 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
870 CADDR1 = crashdumpmap;
874 /* Initialize the PAT MSR. */
877 /* Initialize TLB Context Id. */
878 TUNABLE_INT_FETCH("vm.pmap.pcid_enabled", &pmap_pcid_enabled);
879 if ((cpu_feature2 & CPUID2_PCID) != 0 && pmap_pcid_enabled) {
880 load_cr4(rcr4() | CR4_PCIDE);
881 mtx_init(&pcid_mtx, "pcid", NULL, MTX_DEF);
882 init_unrhdr(&pcid_unr, 1, (1 << 12) - 1, &pcid_mtx);
883 /* Check for INVPCID support */
884 invpcid_works = (cpu_stdext_feature & CPUID_STDEXT_INVPCID)
886 kernel_pmap->pm_pcid = 0;
888 pmap_pcid_enabled = 0;
891 pmap_pcid_enabled = 0;
900 int pat_table[PAT_INDEX_SIZE];
905 /* Bail if this CPU doesn't implement PAT. */
906 if ((cpu_feature & CPUID_PAT) == 0)
909 /* Set default PAT index table. */
910 for (i = 0; i < PAT_INDEX_SIZE; i++)
912 pat_table[PAT_WRITE_BACK] = 0;
913 pat_table[PAT_WRITE_THROUGH] = 1;
914 pat_table[PAT_UNCACHEABLE] = 3;
915 pat_table[PAT_WRITE_COMBINING] = 3;
916 pat_table[PAT_WRITE_PROTECTED] = 3;
917 pat_table[PAT_UNCACHED] = 3;
919 /* Initialize default PAT entries. */
920 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
921 PAT_VALUE(1, PAT_WRITE_THROUGH) |
922 PAT_VALUE(2, PAT_UNCACHED) |
923 PAT_VALUE(3, PAT_UNCACHEABLE) |
924 PAT_VALUE(4, PAT_WRITE_BACK) |
925 PAT_VALUE(5, PAT_WRITE_THROUGH) |
926 PAT_VALUE(6, PAT_UNCACHED) |
927 PAT_VALUE(7, PAT_UNCACHEABLE);
931 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
932 * Program 5 and 6 as WP and WC.
933 * Leave 4 and 7 as WB and UC.
935 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
936 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
937 PAT_VALUE(6, PAT_WRITE_COMBINING);
938 pat_table[PAT_UNCACHED] = 2;
939 pat_table[PAT_WRITE_PROTECTED] = 5;
940 pat_table[PAT_WRITE_COMBINING] = 6;
943 * Just replace PAT Index 2 with WC instead of UC-.
945 pat_msr &= ~PAT_MASK(2);
946 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
947 pat_table[PAT_WRITE_COMBINING] = 2;
952 load_cr4(cr4 & ~CR4_PGE);
954 /* Disable caches (CD = 1, NW = 0). */
956 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
958 /* Flushes caches and TLBs. */
962 /* Update PAT and index table. */
963 wrmsr(MSR_PAT, pat_msr);
964 for (i = 0; i < PAT_INDEX_SIZE; i++)
965 pat_index[i] = pat_table[i];
967 /* Flush caches and TLBs again. */
971 /* Restore caches and PGE. */
977 * Initialize a vm_page's machine-dependent fields.
980 pmap_page_init(vm_page_t m)
983 TAILQ_INIT(&m->md.pv_list);
984 m->md.pat_mode = PAT_WRITE_BACK;
988 * Initialize the pmap module.
989 * Called by vm_init, to initialize any structures that the pmap
990 * system needs to map virtual memory.
1000 * Initialize the vm page array entries for the kernel pmap's
1003 for (i = 0; i < nkpt; i++) {
1004 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1005 KASSERT(mpte >= vm_page_array &&
1006 mpte < &vm_page_array[vm_page_array_size],
1007 ("pmap_init: page table page is out of range"));
1008 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1009 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1013 * If the kernel is running on a virtual machine, then it must assume
1014 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1015 * be prepared for the hypervisor changing the vendor and family that
1016 * are reported by CPUID. Consequently, the workaround for AMD Family
1017 * 10h Erratum 383 is enabled if the processor's feature set does not
1018 * include at least one feature that is only supported by older Intel
1019 * or newer AMD processors.
1021 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
1022 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1023 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1025 workaround_erratum383 = 1;
1028 * Are large page mappings enabled?
1030 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1031 if (pg_ps_enabled) {
1032 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1033 ("pmap_init: can't assign to pagesizes[1]"));
1034 pagesizes[1] = NBPDR;
1038 * Initialize the pv chunk list mutex.
1040 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1043 * Initialize the pool of pv list locks.
1045 for (i = 0; i < NPV_LIST_LOCKS; i++)
1046 rw_init(&pv_list_locks[i], "pmap pv list");
1049 * Calculate the size of the pv head table for superpages.
1051 for (i = 0; phys_avail[i + 1]; i += 2);
1052 pv_npg = round_2mpage(phys_avail[(i - 2) + 1]) / NBPDR;
1055 * Allocate memory for the pv head table for superpages.
1057 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1059 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
1061 for (i = 0; i < pv_npg; i++)
1062 TAILQ_INIT(&pv_table[i].pv_list);
1064 mtx_init(&cpage_lock, "cpage", NULL, MTX_DEF);
1065 cpage_a = kva_alloc(PAGE_SIZE);
1066 cpage_b = kva_alloc(PAGE_SIZE);
1069 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
1070 "2MB page mapping counters");
1072 static u_long pmap_pde_demotions;
1073 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
1074 &pmap_pde_demotions, 0, "2MB page demotions");
1076 static u_long pmap_pde_mappings;
1077 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
1078 &pmap_pde_mappings, 0, "2MB page mappings");
1080 static u_long pmap_pde_p_failures;
1081 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
1082 &pmap_pde_p_failures, 0, "2MB page promotion failures");
1084 static u_long pmap_pde_promotions;
1085 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
1086 &pmap_pde_promotions, 0, "2MB page promotions");
1088 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
1089 "1GB page mapping counters");
1091 static u_long pmap_pdpe_demotions;
1092 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
1093 &pmap_pdpe_demotions, 0, "1GB page demotions");
1095 /***************************************************
1096 * Low level helper routines.....
1097 ***************************************************/
1100 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
1102 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
1104 switch (pmap->pm_type) {
1106 /* Verify that both PAT bits are not set at the same time */
1107 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
1108 ("Invalid PAT bits in entry %#lx", entry));
1110 /* Swap the PAT bits if one of them is set */
1111 if ((entry & x86_pat_bits) != 0)
1112 entry ^= x86_pat_bits;
1116 * Nothing to do - the memory attributes are represented
1117 * the same way for regular pages and superpages.
1121 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
1128 * Determine the appropriate bits to set in a PTE or PDE for a specified
1132 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
1134 int cache_bits, pat_flag, pat_idx;
1136 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
1137 panic("Unknown caching mode %d\n", mode);
1139 switch (pmap->pm_type) {
1141 /* The PAT bit is different for PTE's and PDE's. */
1142 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
1144 /* Map the caching mode to a PAT index. */
1145 pat_idx = pat_index[mode];
1147 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1150 cache_bits |= pat_flag;
1152 cache_bits |= PG_NC_PCD;
1154 cache_bits |= PG_NC_PWT;
1158 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
1162 panic("unsupported pmap type %d", pmap->pm_type);
1165 return (cache_bits);
1169 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
1173 switch (pmap->pm_type) {
1175 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
1178 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
1181 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
1187 static __inline boolean_t
1188 pmap_ps_enabled(pmap_t pmap)
1191 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
1195 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
1198 switch (pmap->pm_type) {
1204 * This is a little bogus since the generation number is
1205 * supposed to be bumped up when a region of the address
1206 * space is invalidated in the page tables.
1208 * In this case the old PDE entry is valid but yet we want
1209 * to make sure that any mappings using the old entry are
1210 * invalidated in the TLB.
1212 * The reason this works as expected is because we rendezvous
1213 * "all" host cpus and force any vcpu context to exit as a
1216 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1219 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
1221 pde_store(pde, newpde);
1225 * After changing the page size for the specified virtual address in the page
1226 * table, flush the corresponding entries from the processor's TLB. Only the
1227 * calling processor's TLB is affected.
1229 * The calling thread must be pinned to a processor.
1232 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
1236 if (pmap->pm_type == PT_EPT)
1239 KASSERT(pmap->pm_type == PT_X86,
1240 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
1242 PG_G = pmap_global_bit(pmap);
1244 if ((newpde & PG_PS) == 0)
1245 /* Demotion: flush a specific 2MB page mapping. */
1247 else if ((newpde & PG_G) == 0)
1249 * Promotion: flush every 4KB page mapping from the TLB
1250 * because there are too many to flush individually.
1255 * Promotion: flush every 4KB page mapping from the TLB,
1256 * including any global (PG_G) mappings.
1264 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va)
1266 struct invpcid_descr d;
1269 if (invpcid_works) {
1270 d.pcid = pmap->pm_pcid;
1273 invpcid(&d, INVPCID_ADDR);
1279 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1281 load_cr3(cr3 | CR3_PCID_SAVE);
1286 * For SMP, these functions have to use the IPI mechanism for coherence.
1288 * N.B.: Before calling any of the following TLB invalidation functions,
1289 * the calling processor must ensure that all stores updating a non-
1290 * kernel page table are globally performed. Otherwise, another
1291 * processor could cache an old, pre-update entry without being
1292 * invalidated. This can happen one of two ways: (1) The pmap becomes
1293 * active on another processor after its pm_active field is checked by
1294 * one of the following functions but before a store updating the page
1295 * table is globally performed. (2) The pmap becomes active on another
1296 * processor before its pm_active field is checked but due to
1297 * speculative loads one of the following functions stills reads the
1298 * pmap as inactive on the other processor.
1300 * The kernel page table is exempt because its pm_active field is
1301 * immutable. The kernel page table is always active on every
1306 * Interrupt the cpus that are executing in the guest context.
1307 * This will force the vcpu to exit and the cached EPT mappings
1308 * will be invalidated by the host before the next vmresume.
1310 static __inline void
1311 pmap_invalidate_ept(pmap_t pmap)
1316 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
1317 ("pmap_invalidate_ept: absurd pm_active"));
1320 * The TLB mappings associated with a vcpu context are not
1321 * flushed each time a different vcpu is chosen to execute.
1323 * This is in contrast with a process's vtop mappings that
1324 * are flushed from the TLB on each context switch.
1326 * Therefore we need to do more than just a TLB shootdown on
1327 * the active cpus in 'pmap->pm_active'. To do this we keep
1328 * track of the number of invalidations performed on this pmap.
1330 * Each vcpu keeps a cache of this counter and compares it
1331 * just before a vmresume. If the counter is out-of-date an
1332 * invept will be done to flush stale mappings from the TLB.
1334 atomic_add_acq_long(&pmap->pm_eptgen, 1);
1337 * Force the vcpu to exit and trap back into the hypervisor.
1339 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
1340 ipi_selected(pmap->pm_active, ipinum);
1345 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1347 cpuset_t other_cpus;
1350 if (pmap->pm_type == PT_EPT) {
1351 pmap_invalidate_ept(pmap);
1355 KASSERT(pmap->pm_type == PT_X86,
1356 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
1359 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1360 if (!pmap_pcid_enabled) {
1363 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1364 if (pmap == PCPU_GET(curpmap))
1367 pmap_invalidate_page_pcid(pmap, va);
1372 smp_invlpg(pmap, va);
1374 cpuid = PCPU_GET(cpuid);
1375 other_cpus = all_cpus;
1376 CPU_CLR(cpuid, &other_cpus);
1377 if (CPU_ISSET(cpuid, &pmap->pm_active))
1379 else if (pmap_pcid_enabled) {
1380 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1381 pmap_invalidate_page_pcid(pmap, va);
1385 if (pmap_pcid_enabled)
1386 CPU_AND(&other_cpus, &pmap->pm_save);
1388 CPU_AND(&other_cpus, &pmap->pm_active);
1389 if (!CPU_EMPTY(&other_cpus))
1390 smp_masked_invlpg(other_cpus, pmap, va);
1396 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1398 struct invpcid_descr d;
1402 if (invpcid_works) {
1403 d.pcid = pmap->pm_pcid;
1405 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
1407 invpcid(&d, INVPCID_ADDR);
1414 load_cr3(pmap->pm_cr3 | CR3_PCID_SAVE);
1415 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1417 load_cr3(cr3 | CR3_PCID_SAVE);
1422 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1424 cpuset_t other_cpus;
1428 if (pmap->pm_type == PT_EPT) {
1429 pmap_invalidate_ept(pmap);
1433 KASSERT(pmap->pm_type == PT_X86,
1434 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
1437 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1438 if (!pmap_pcid_enabled) {
1439 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1442 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1443 if (pmap == PCPU_GET(curpmap)) {
1444 for (addr = sva; addr < eva;
1448 pmap_invalidate_range_pcid(pmap,
1455 smp_invlpg_range(pmap, sva, eva);
1457 cpuid = PCPU_GET(cpuid);
1458 other_cpus = all_cpus;
1459 CPU_CLR(cpuid, &other_cpus);
1460 if (CPU_ISSET(cpuid, &pmap->pm_active)) {
1461 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1463 } else if (pmap_pcid_enabled) {
1464 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0)
1465 pmap_invalidate_range_pcid(pmap, sva, eva);
1469 if (pmap_pcid_enabled)
1470 CPU_AND(&other_cpus, &pmap->pm_save);
1472 CPU_AND(&other_cpus, &pmap->pm_active);
1473 if (!CPU_EMPTY(&other_cpus))
1474 smp_masked_invlpg_range(other_cpus, pmap, sva, eva);
1480 pmap_invalidate_all(pmap_t pmap)
1482 cpuset_t other_cpus;
1483 struct invpcid_descr d;
1487 if (pmap->pm_type == PT_EPT) {
1488 pmap_invalidate_ept(pmap);
1492 KASSERT(pmap->pm_type == PT_X86,
1493 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
1496 cpuid = PCPU_GET(cpuid);
1497 if (pmap == kernel_pmap ||
1498 (pmap_pcid_enabled && !CPU_CMP(&pmap->pm_save, &all_cpus)) ||
1499 !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1500 if (invpcid_works) {
1501 bzero(&d, sizeof(d));
1502 invpcid(&d, INVPCID_CTXGLOB);
1506 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1507 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1510 other_cpus = all_cpus;
1511 CPU_CLR(cpuid, &other_cpus);
1514 * This logic is duplicated in the Xinvltlb shootdown
1517 if (pmap_pcid_enabled) {
1518 if (pmap->pm_pcid != -1 && pmap->pm_pcid != 0) {
1519 if (invpcid_works) {
1520 d.pcid = pmap->pm_pcid;
1523 invpcid(&d, INVPCID_CTX);
1529 * Bit 63 is clear, pcid TLB
1530 * entries are invalidated.
1532 load_cr3(pmap->pm_cr3);
1533 load_cr3(cr3 | CR3_PCID_SAVE);
1539 } else if (CPU_ISSET(cpuid, &pmap->pm_active))
1541 if (!CPU_ISSET(cpuid, &pmap->pm_active))
1542 CPU_CLR_ATOMIC(cpuid, &pmap->pm_save);
1543 if (pmap_pcid_enabled)
1544 CPU_AND(&other_cpus, &pmap->pm_save);
1546 CPU_AND(&other_cpus, &pmap->pm_active);
1547 if (!CPU_EMPTY(&other_cpus))
1548 smp_masked_invltlb(other_cpus, pmap);
1554 pmap_invalidate_cache(void)
1564 cpuset_t invalidate; /* processors that invalidate their TLB */
1569 u_int store; /* processor that updates the PDE */
1573 pmap_update_pde_action(void *arg)
1575 struct pde_action *act = arg;
1577 if (act->store == PCPU_GET(cpuid))
1578 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
1582 pmap_update_pde_teardown(void *arg)
1584 struct pde_action *act = arg;
1586 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1587 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
1591 * Change the page size for the specified virtual address in a way that
1592 * prevents any possibility of the TLB ever having two entries that map the
1593 * same virtual address using different page sizes. This is the recommended
1594 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1595 * machine check exception for a TLB state that is improperly diagnosed as a
1599 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1601 struct pde_action act;
1602 cpuset_t active, other_cpus;
1606 cpuid = PCPU_GET(cpuid);
1607 other_cpus = all_cpus;
1608 CPU_CLR(cpuid, &other_cpus);
1609 if (pmap == kernel_pmap || pmap->pm_type == PT_EPT)
1612 active = pmap->pm_active;
1613 CPU_AND_ATOMIC(&pmap->pm_save, &active);
1615 if (CPU_OVERLAP(&active, &other_cpus)) {
1617 act.invalidate = active;
1621 act.newpde = newpde;
1622 CPU_SET(cpuid, &active);
1623 smp_rendezvous_cpus(active,
1624 smp_no_rendevous_barrier, pmap_update_pde_action,
1625 pmap_update_pde_teardown, &act);
1627 pmap_update_pde_store(pmap, pde, newpde);
1628 if (CPU_ISSET(cpuid, &active))
1629 pmap_update_pde_invalidate(pmap, va, newpde);
1635 * Normal, non-SMP, invalidation functions.
1636 * We inline these within pmap.c for speed.
1639 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1642 switch (pmap->pm_type) {
1644 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1651 panic("pmap_invalidate_page: unknown type: %d", pmap->pm_type);
1656 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1660 switch (pmap->pm_type) {
1662 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1663 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1670 panic("pmap_invalidate_range: unknown type: %d", pmap->pm_type);
1675 pmap_invalidate_all(pmap_t pmap)
1678 switch (pmap->pm_type) {
1680 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1687 panic("pmap_invalidate_all: unknown type %d", pmap->pm_type);
1692 pmap_invalidate_cache(void)
1699 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1702 pmap_update_pde_store(pmap, pde, newpde);
1703 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1704 pmap_update_pde_invalidate(pmap, va, newpde);
1706 CPU_ZERO(&pmap->pm_save);
1710 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1713 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1717 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1719 KASSERT((sva & PAGE_MASK) == 0,
1720 ("pmap_invalidate_cache_range: sva not page-aligned"));
1721 KASSERT((eva & PAGE_MASK) == 0,
1722 ("pmap_invalidate_cache_range: eva not page-aligned"));
1725 if ((cpu_feature & CPUID_SS) != 0 && !force)
1726 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1727 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1728 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1731 * XXX: Some CPUs fault, hang, or trash the local APIC
1732 * registers if we use CLFLUSH on the local APIC
1733 * range. The local APIC is always uncached, so we
1734 * don't need to flush for that range anyway.
1736 if (pmap_kextract(sva) == lapic_paddr)
1740 * Otherwise, do per-cache line flush. Use the mfence
1741 * instruction to insure that previous stores are
1742 * included in the write-back. The processor
1743 * propagates flush to other processors in the cache
1747 for (; sva < eva; sva += cpu_clflush_line_size)
1753 * No targeted cache flush methods are supported by CPU,
1754 * or the supplied range is bigger than 2MB.
1755 * Globally invalidate cache.
1757 pmap_invalidate_cache();
1762 * Remove the specified set of pages from the data and instruction caches.
1764 * In contrast to pmap_invalidate_cache_range(), this function does not
1765 * rely on the CPU's self-snoop feature, because it is intended for use
1766 * when moving pages into a different cache domain.
1769 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1771 vm_offset_t daddr, eva;
1774 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1775 (cpu_feature & CPUID_CLFSH) == 0)
1776 pmap_invalidate_cache();
1779 for (i = 0; i < count; i++) {
1780 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
1781 eva = daddr + PAGE_SIZE;
1782 for (; daddr < eva; daddr += cpu_clflush_line_size)
1790 * Routine: pmap_extract
1792 * Extract the physical page address associated
1793 * with the given map/virtual_address pair.
1796 pmap_extract(pmap_t pmap, vm_offset_t va)
1800 pt_entry_t *pte, PG_V;
1804 PG_V = pmap_valid_bit(pmap);
1806 pdpe = pmap_pdpe(pmap, va);
1807 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
1808 if ((*pdpe & PG_PS) != 0)
1809 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
1811 pde = pmap_pdpe_to_pde(pdpe, va);
1812 if ((*pde & PG_V) != 0) {
1813 if ((*pde & PG_PS) != 0) {
1814 pa = (*pde & PG_PS_FRAME) |
1817 pte = pmap_pde_to_pte(pde, va);
1818 pa = (*pte & PG_FRAME) |
1829 * Routine: pmap_extract_and_hold
1831 * Atomically extract and hold the physical page
1832 * with the given pmap and virtual address pair
1833 * if that mapping permits the given protection.
1836 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1838 pd_entry_t pde, *pdep;
1839 pt_entry_t pte, PG_RW, PG_V;
1845 PG_RW = pmap_rw_bit(pmap);
1846 PG_V = pmap_valid_bit(pmap);
1849 pdep = pmap_pde(pmap, va);
1850 if (pdep != NULL && (pde = *pdep)) {
1852 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1853 if (vm_page_pa_tryrelock(pmap, (pde &
1854 PG_PS_FRAME) | (va & PDRMASK), &pa))
1856 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1861 pte = *pmap_pde_to_pte(pdep, va);
1863 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1864 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1867 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1878 pmap_kextract(vm_offset_t va)
1883 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1884 pa = DMAP_TO_PHYS(va);
1888 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
1891 * Beware of a concurrent promotion that changes the
1892 * PDE at this point! For example, vtopte() must not
1893 * be used to access the PTE because it would use the
1894 * new PDE. It is, however, safe to use the old PDE
1895 * because the page table page is preserved by the
1898 pa = *pmap_pde_to_pte(&pde, va);
1899 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1905 /***************************************************
1906 * Low level mapping routines.....
1907 ***************************************************/
1910 * Add a wired page to the kva.
1911 * Note: not SMP coherent.
1914 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1919 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G);
1922 static __inline void
1923 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1929 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
1930 pte_store(pte, pa | X86_PG_RW | X86_PG_V | X86_PG_G | cache_bits);
1934 * Remove a page from the kernel pagetables.
1935 * Note: not SMP coherent.
1938 pmap_kremove(vm_offset_t va)
1947 * Used to map a range of physical addresses into kernel
1948 * virtual address space.
1950 * The value passed in '*virt' is a suggested virtual address for
1951 * the mapping. Architectures which can support a direct-mapped
1952 * physical to virtual region can return the appropriate address
1953 * within that region, leaving '*virt' unchanged. Other
1954 * architectures should map the pages starting at '*virt' and
1955 * update '*virt' with the first usable address after the mapped
1959 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1961 return PHYS_TO_DMAP(start);
1966 * Add a list of wired pages to the kva
1967 * this routine is only used for temporary
1968 * kernel mappings that do not need to have
1969 * page modification or references recorded.
1970 * Note that old mappings are simply written
1971 * over. The page *must* be wired.
1972 * Note: SMP coherent. Uses a ranged shootdown IPI.
1975 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1977 pt_entry_t *endpte, oldpte, pa, *pte;
1983 endpte = pte + count;
1984 while (pte < endpte) {
1986 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
1987 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
1988 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
1990 pte_store(pte, pa | X86_PG_G | X86_PG_RW | X86_PG_V);
1994 if (__predict_false((oldpte & X86_PG_V) != 0))
1995 pmap_invalidate_range(kernel_pmap, sva, sva + count *
2000 * This routine tears out page mappings from the
2001 * kernel -- it is meant only for temporary mappings.
2002 * Note: SMP coherent. Uses a ranged shootdown IPI.
2005 pmap_qremove(vm_offset_t sva, int count)
2010 while (count-- > 0) {
2011 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
2015 pmap_invalidate_range(kernel_pmap, sva, va);
2018 /***************************************************
2019 * Page table page management routines.....
2020 ***************************************************/
2021 static __inline void
2022 pmap_free_zero_pages(struct spglist *free)
2026 while ((m = SLIST_FIRST(free)) != NULL) {
2027 SLIST_REMOVE_HEAD(free, plinks.s.ss);
2028 /* Preserve the page's PG_ZERO setting. */
2029 vm_page_free_toq(m);
2034 * Schedule the specified unused page table page to be freed. Specifically,
2035 * add the page to the specified list of pages that will be released to the
2036 * physical memory manager after the TLB has been updated.
2038 static __inline void
2039 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
2040 boolean_t set_PG_ZERO)
2044 m->flags |= PG_ZERO;
2046 m->flags &= ~PG_ZERO;
2047 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
2051 * Inserts the specified page table page into the specified pmap's collection
2052 * of idle page table pages. Each of a pmap's page table pages is responsible
2053 * for mapping a distinct range of virtual addresses. The pmap's collection is
2054 * ordered by this virtual address range.
2057 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2060 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2061 return (vm_radix_insert(&pmap->pm_root, mpte));
2065 * Looks for a page table page mapping the specified virtual address in the
2066 * specified pmap's collection of idle page table pages. Returns NULL if there
2067 * is no page table page corresponding to the specified virtual address.
2069 static __inline vm_page_t
2070 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
2073 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2074 return (vm_radix_lookup(&pmap->pm_root, pmap_pde_pindex(va)));
2078 * Removes the specified page table page from the specified pmap's collection
2079 * of idle page table pages. The specified page table page must be a member of
2080 * the pmap's collection.
2082 static __inline void
2083 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
2086 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2087 vm_radix_remove(&pmap->pm_root, mpte->pindex);
2091 * Decrements a page table page's wire count, which is used to record the
2092 * number of valid page table entries within the page. If the wire count
2093 * drops to zero, then the page table page is unmapped. Returns TRUE if the
2094 * page table page was unmapped and FALSE otherwise.
2096 static inline boolean_t
2097 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2101 if (m->wire_count == 0) {
2102 _pmap_unwire_ptp(pmap, va, m, free);
2109 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
2112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2114 * unmap the page table page
2116 if (m->pindex >= (NUPDE + NUPDPE)) {
2119 pml4 = pmap_pml4e(pmap, va);
2121 } else if (m->pindex >= NUPDE) {
2124 pdp = pmap_pdpe(pmap, va);
2129 pd = pmap_pde(pmap, va);
2132 pmap_resident_count_dec(pmap, 1);
2133 if (m->pindex < NUPDE) {
2134 /* We just released a PT, unhold the matching PD */
2137 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
2138 pmap_unwire_ptp(pmap, va, pdpg, free);
2140 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
2141 /* We just released a PD, unhold the matching PDP */
2144 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
2145 pmap_unwire_ptp(pmap, va, pdppg, free);
2149 * This is a release store so that the ordinary store unmapping
2150 * the page table page is globally performed before TLB shoot-
2153 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
2156 * Put page on a list so that it is released after
2157 * *ALL* TLB shootdown is done
2159 pmap_add_delayed_free_list(m, free, TRUE);
2163 * After removing a page table entry, this routine is used to
2164 * conditionally free the page, and manage the hold/wire counts.
2167 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
2168 struct spglist *free)
2172 if (va >= VM_MAXUSER_ADDRESS)
2174 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
2175 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2176 return (pmap_unwire_ptp(pmap, va, mpte, free));
2180 pmap_pinit0(pmap_t pmap)
2183 PMAP_LOCK_INIT(pmap);
2184 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
2185 pmap->pm_cr3 = KPML4phys;
2186 pmap->pm_root.rt_root = 0;
2187 CPU_ZERO(&pmap->pm_active);
2188 CPU_ZERO(&pmap->pm_save);
2189 PCPU_SET(curpmap, pmap);
2190 TAILQ_INIT(&pmap->pm_pvchunk);
2191 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2192 pmap->pm_pcid = pmap_pcid_enabled ? 0 : -1;
2193 pmap->pm_flags = pmap_flags;
2197 * Initialize a preallocated and zeroed pmap structure,
2198 * such as one in a vmspace structure.
2201 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
2204 vm_paddr_t pml4phys;
2208 * allocate the page directory page
2210 while ((pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2211 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
2214 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
2215 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
2217 pmap->pm_cr3 = ~0; /* initialize to an invalid value */
2219 if ((pml4pg->flags & PG_ZERO) == 0)
2220 pagezero(pmap->pm_pml4);
2223 * Do not install the host kernel mappings in the nested page
2224 * tables. These mappings are meaningless in the guest physical
2227 if ((pmap->pm_type = pm_type) == PT_X86) {
2228 pmap->pm_cr3 = pml4phys;
2230 /* Wire in kernel global address entries. */
2231 for (i = 0; i < NKPML4E; i++) {
2232 pmap->pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) |
2233 X86_PG_RW | X86_PG_V | PG_U;
2235 for (i = 0; i < ndmpdpphys; i++) {
2236 pmap->pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) |
2237 X86_PG_RW | X86_PG_V | PG_U;
2240 /* install self-referential address mapping entry(s) */
2241 pmap->pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) |
2242 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2244 if (pmap_pcid_enabled) {
2245 pmap->pm_pcid = alloc_unr(&pcid_unr);
2246 if (pmap->pm_pcid != -1)
2247 pmap->pm_cr3 |= pmap->pm_pcid;
2251 pmap->pm_root.rt_root = 0;
2252 CPU_ZERO(&pmap->pm_active);
2253 TAILQ_INIT(&pmap->pm_pvchunk);
2254 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2255 pmap->pm_flags = flags;
2256 pmap->pm_eptgen = 0;
2257 CPU_ZERO(&pmap->pm_save);
2263 pmap_pinit(pmap_t pmap)
2266 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
2270 * This routine is called if the desired page table page does not exist.
2272 * If page table page allocation fails, this routine may sleep before
2273 * returning NULL. It sleeps only if a lock pointer was given.
2275 * Note: If a page allocation fails at page table level two or three,
2276 * one or two pages may be held during the wait, only to be released
2277 * afterwards. This conservative approach is easily argued to avoid
2281 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
2283 vm_page_t m, pdppg, pdpg;
2284 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
2286 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2288 PG_A = pmap_accessed_bit(pmap);
2289 PG_M = pmap_modified_bit(pmap);
2290 PG_V = pmap_valid_bit(pmap);
2291 PG_RW = pmap_rw_bit(pmap);
2294 * Allocate a page table page.
2296 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
2297 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2298 if (lockp != NULL) {
2299 RELEASE_PV_LIST_LOCK(lockp);
2301 rw_runlock(&pvh_global_lock);
2303 rw_rlock(&pvh_global_lock);
2308 * Indicate the need to retry. While waiting, the page table
2309 * page may have been allocated.
2313 if ((m->flags & PG_ZERO) == 0)
2317 * Map the pagetable page into the process address space, if
2318 * it isn't already there.
2321 if (ptepindex >= (NUPDE + NUPDPE)) {
2323 vm_pindex_t pml4index;
2325 /* Wire up a new PDPE page */
2326 pml4index = ptepindex - (NUPDE + NUPDPE);
2327 pml4 = &pmap->pm_pml4[pml4index];
2328 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2330 } else if (ptepindex >= NUPDE) {
2331 vm_pindex_t pml4index;
2332 vm_pindex_t pdpindex;
2336 /* Wire up a new PDE page */
2337 pdpindex = ptepindex - NUPDE;
2338 pml4index = pdpindex >> NPML4EPGSHIFT;
2340 pml4 = &pmap->pm_pml4[pml4index];
2341 if ((*pml4 & PG_V) == 0) {
2342 /* Have to allocate a new pdp, recurse */
2343 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
2346 atomic_subtract_int(&cnt.v_wire_count, 1);
2347 vm_page_free_zero(m);
2351 /* Add reference to pdp page */
2352 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
2353 pdppg->wire_count++;
2355 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2357 /* Now find the pdp page */
2358 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2359 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2362 vm_pindex_t pml4index;
2363 vm_pindex_t pdpindex;
2368 /* Wire up a new PTE page */
2369 pdpindex = ptepindex >> NPDPEPGSHIFT;
2370 pml4index = pdpindex >> NPML4EPGSHIFT;
2372 /* First, find the pdp and check that its valid. */
2373 pml4 = &pmap->pm_pml4[pml4index];
2374 if ((*pml4 & PG_V) == 0) {
2375 /* Have to allocate a new pd, recurse */
2376 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2379 atomic_subtract_int(&cnt.v_wire_count, 1);
2380 vm_page_free_zero(m);
2383 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2384 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2386 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
2387 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
2388 if ((*pdp & PG_V) == 0) {
2389 /* Have to allocate a new pd, recurse */
2390 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
2393 atomic_subtract_int(&cnt.v_wire_count,
2395 vm_page_free_zero(m);
2399 /* Add reference to the pd page */
2400 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
2404 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
2406 /* Now we know where the page directory page is */
2407 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
2408 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
2411 pmap_resident_count_inc(pmap, 1);
2417 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2419 vm_pindex_t pdpindex, ptepindex;
2420 pdp_entry_t *pdpe, PG_V;
2423 PG_V = pmap_valid_bit(pmap);
2426 pdpe = pmap_pdpe(pmap, va);
2427 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
2428 /* Add a reference to the pd page. */
2429 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
2432 /* Allocate a pd page. */
2433 ptepindex = pmap_pde_pindex(va);
2434 pdpindex = ptepindex >> NPDPEPGSHIFT;
2435 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
2436 if (pdpg == NULL && lockp != NULL)
2443 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
2445 vm_pindex_t ptepindex;
2446 pd_entry_t *pd, PG_V;
2449 PG_V = pmap_valid_bit(pmap);
2452 * Calculate pagetable page index
2454 ptepindex = pmap_pde_pindex(va);
2457 * Get the page directory entry
2459 pd = pmap_pde(pmap, va);
2462 * This supports switching from a 2MB page to a
2465 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
2466 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
2468 * Invalidation of the 2MB page mapping may have caused
2469 * the deallocation of the underlying PD page.
2476 * If the page table page is mapped, we just increment the
2477 * hold count, and activate it.
2479 if (pd != NULL && (*pd & PG_V) != 0) {
2480 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
2484 * Here if the pte page isn't mapped, or if it has been
2487 m = _pmap_allocpte(pmap, ptepindex, lockp);
2488 if (m == NULL && lockp != NULL)
2495 /***************************************************
2496 * Pmap allocation/deallocation routines.
2497 ***************************************************/
2500 * Release any resources held by the given physical map.
2501 * Called when a pmap initialized by pmap_pinit is being released.
2502 * Should only be called if the map contains no valid mappings.
2505 pmap_release(pmap_t pmap)
2510 KASSERT(pmap->pm_stats.resident_count == 0,
2511 ("pmap_release: pmap resident count %ld != 0",
2512 pmap->pm_stats.resident_count));
2513 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2514 ("pmap_release: pmap has reserved page table page(s)"));
2516 if (pmap_pcid_enabled) {
2518 * Invalidate any left TLB entries, to allow the reuse
2521 pmap_invalidate_all(pmap);
2524 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
2526 for (i = 0; i < NKPML4E; i++) /* KVA */
2527 pmap->pm_pml4[KPML4BASE + i] = 0;
2528 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
2529 pmap->pm_pml4[DMPML4I + i] = 0;
2530 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
2533 atomic_subtract_int(&cnt.v_wire_count, 1);
2534 vm_page_free_zero(m);
2535 if (pmap->pm_pcid != -1)
2536 free_unr(&pcid_unr, pmap->pm_pcid);
2540 kvm_size(SYSCTL_HANDLER_ARGS)
2542 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
2544 return sysctl_handle_long(oidp, &ksize, 0, req);
2546 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2547 0, 0, kvm_size, "LU", "Size of KVM");
2550 kvm_free(SYSCTL_HANDLER_ARGS)
2552 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2554 return sysctl_handle_long(oidp, &kfree, 0, req);
2556 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2557 0, 0, kvm_free, "LU", "Amount of KVM free");
2560 * grow the number of kernel page table entries, if needed
2563 pmap_growkernel(vm_offset_t addr)
2567 pd_entry_t *pde, newpdir;
2570 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2573 * Return if "addr" is within the range of kernel page table pages
2574 * that were preallocated during pmap bootstrap. Moreover, leave
2575 * "kernel_vm_end" and the kernel page table as they were.
2577 * The correctness of this action is based on the following
2578 * argument: vm_map_findspace() allocates contiguous ranges of the
2579 * kernel virtual address space. It calls this function if a range
2580 * ends after "kernel_vm_end". If the kernel is mapped between
2581 * "kernel_vm_end" and "addr", then the range cannot begin at
2582 * "kernel_vm_end". In fact, its beginning address cannot be less
2583 * than the kernel. Thus, there is no immediate need to allocate
2584 * any new kernel page table pages between "kernel_vm_end" and
2587 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
2590 addr = roundup2(addr, NBPDR);
2591 if (addr - 1 >= kernel_map->max_offset)
2592 addr = kernel_map->max_offset;
2593 while (kernel_vm_end < addr) {
2594 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
2595 if ((*pdpe & X86_PG_V) == 0) {
2596 /* We need a new PDP entry */
2597 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
2598 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
2599 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2601 panic("pmap_growkernel: no memory to grow kernel");
2602 if ((nkpg->flags & PG_ZERO) == 0)
2603 pmap_zero_page(nkpg);
2604 paddr = VM_PAGE_TO_PHYS(nkpg);
2605 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
2606 X86_PG_A | X86_PG_M);
2607 continue; /* try again */
2609 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
2610 if ((*pde & X86_PG_V) != 0) {
2611 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2612 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2613 kernel_vm_end = kernel_map->max_offset;
2619 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
2620 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2623 panic("pmap_growkernel: no memory to grow kernel");
2624 if ((nkpg->flags & PG_ZERO) == 0)
2625 pmap_zero_page(nkpg);
2626 paddr = VM_PAGE_TO_PHYS(nkpg);
2627 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
2628 pde_store(pde, newpdir);
2630 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2631 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2632 kernel_vm_end = kernel_map->max_offset;
2639 /***************************************************
2640 * page management routines.
2641 ***************************************************/
2643 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2644 CTASSERT(_NPCM == 3);
2645 CTASSERT(_NPCPV == 168);
2647 static __inline struct pv_chunk *
2648 pv_to_chunk(pv_entry_t pv)
2651 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2654 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2656 #define PC_FREE0 0xfffffffffffffffful
2657 #define PC_FREE1 0xfffffffffffffffful
2658 #define PC_FREE2 0x000000fffffffffful
2660 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
2663 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2665 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2666 "Current number of pv entry chunks");
2667 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2668 "Current number of pv entry chunks allocated");
2669 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2670 "Current number of pv entry chunks frees");
2671 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2672 "Number of times tried to get a chunk page but failed.");
2674 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
2675 static int pv_entry_spare;
2677 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2678 "Current number of pv entry frees");
2679 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2680 "Current number of pv entry allocs");
2681 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2682 "Current number of pv entries");
2683 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2684 "Current number of spare pv entries");
2688 * We are in a serious low memory condition. Resort to
2689 * drastic measures to free some pages so we can allocate
2690 * another pv entry chunk.
2692 * Returns NULL if PV entries were reclaimed from the specified pmap.
2694 * We do not, however, unmap 2mpages because subsequent accesses will
2695 * allocate per-page pv entries until repromotion occurs, thereby
2696 * exacerbating the shortage of free pv entries.
2699 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
2701 struct pch new_tail;
2702 struct pv_chunk *pc;
2703 struct md_page *pvh;
2706 pt_entry_t *pte, tpte;
2707 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
2711 struct spglist free;
2713 int bit, field, freed;
2715 rw_assert(&pvh_global_lock, RA_LOCKED);
2716 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2717 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
2720 PG_G = PG_A = PG_M = PG_RW = 0;
2722 TAILQ_INIT(&new_tail);
2723 mtx_lock(&pv_chunks_mutex);
2724 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
2725 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2726 mtx_unlock(&pv_chunks_mutex);
2727 if (pmap != pc->pc_pmap) {
2729 pmap_invalidate_all(pmap);
2730 if (pmap != locked_pmap)
2734 /* Avoid deadlock and lock recursion. */
2735 if (pmap > locked_pmap) {
2736 RELEASE_PV_LIST_LOCK(lockp);
2738 } else if (pmap != locked_pmap &&
2739 !PMAP_TRYLOCK(pmap)) {
2741 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2742 mtx_lock(&pv_chunks_mutex);
2745 PG_G = pmap_global_bit(pmap);
2746 PG_A = pmap_accessed_bit(pmap);
2747 PG_M = pmap_modified_bit(pmap);
2748 PG_RW = pmap_rw_bit(pmap);
2752 * Destroy every non-wired, 4 KB page mapping in the chunk.
2755 for (field = 0; field < _NPCM; field++) {
2756 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2757 inuse != 0; inuse &= ~(1UL << bit)) {
2759 pv = &pc->pc_pventry[field * 64 + bit];
2761 pde = pmap_pde(pmap, va);
2762 if ((*pde & PG_PS) != 0)
2764 pte = pmap_pde_to_pte(pde, va);
2765 if ((*pte & PG_W) != 0)
2767 tpte = pte_load_clear(pte);
2768 if ((tpte & PG_G) != 0)
2769 pmap_invalidate_page(pmap, va);
2770 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2771 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2773 if ((tpte & PG_A) != 0)
2774 vm_page_aflag_set(m, PGA_REFERENCED);
2775 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2776 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2778 if (TAILQ_EMPTY(&m->md.pv_list) &&
2779 (m->flags & PG_FICTITIOUS) == 0) {
2780 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2781 if (TAILQ_EMPTY(&pvh->pv_list)) {
2782 vm_page_aflag_clear(m,
2786 pc->pc_map[field] |= 1UL << bit;
2787 pmap_unuse_pt(pmap, va, *pde, &free);
2792 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2793 mtx_lock(&pv_chunks_mutex);
2796 /* Every freed mapping is for a 4 KB page. */
2797 pmap_resident_count_dec(pmap, freed);
2798 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
2799 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
2800 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
2801 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2802 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
2803 pc->pc_map[2] == PC_FREE2) {
2804 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2805 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2806 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2807 /* Entire chunk is free; return it. */
2808 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2809 dump_drop_page(m_pc->phys_addr);
2810 mtx_lock(&pv_chunks_mutex);
2813 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2814 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2815 mtx_lock(&pv_chunks_mutex);
2816 /* One freed pv entry in locked_pmap is sufficient. */
2817 if (pmap == locked_pmap)
2820 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2821 mtx_unlock(&pv_chunks_mutex);
2823 pmap_invalidate_all(pmap);
2824 if (pmap != locked_pmap)
2827 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
2828 m_pc = SLIST_FIRST(&free);
2829 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2830 /* Recycle a freed page table page. */
2831 m_pc->wire_count = 1;
2832 atomic_add_int(&cnt.v_wire_count, 1);
2834 pmap_free_zero_pages(&free);
2839 * free the pv_entry back to the free list
2842 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2844 struct pv_chunk *pc;
2845 int idx, field, bit;
2847 rw_assert(&pvh_global_lock, RA_LOCKED);
2848 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2849 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
2850 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
2851 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
2852 pc = pv_to_chunk(pv);
2853 idx = pv - &pc->pc_pventry[0];
2856 pc->pc_map[field] |= 1ul << bit;
2857 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
2858 pc->pc_map[2] != PC_FREE2) {
2859 /* 98% of the time, pc is already at the head of the list. */
2860 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
2861 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2862 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2866 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2871 free_pv_chunk(struct pv_chunk *pc)
2875 mtx_lock(&pv_chunks_mutex);
2876 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2877 mtx_unlock(&pv_chunks_mutex);
2878 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
2879 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
2880 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
2881 /* entire chunk is free, return it */
2882 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
2883 dump_drop_page(m->phys_addr);
2884 vm_page_unwire(m, 0);
2889 * Returns a new PV entry, allocating a new PV chunk from the system when
2890 * needed. If this PV chunk allocation fails and a PV list lock pointer was
2891 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
2894 * The given PV list lock may be released.
2897 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
2901 struct pv_chunk *pc;
2904 rw_assert(&pvh_global_lock, RA_LOCKED);
2905 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2906 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
2908 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2910 for (field = 0; field < _NPCM; field++) {
2911 if (pc->pc_map[field]) {
2912 bit = bsfq(pc->pc_map[field]);
2916 if (field < _NPCM) {
2917 pv = &pc->pc_pventry[field * 64 + bit];
2918 pc->pc_map[field] &= ~(1ul << bit);
2919 /* If this was the last item, move it to tail */
2920 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2921 pc->pc_map[2] == 0) {
2922 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2923 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2926 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2927 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2931 /* No free items, allocate another chunk */
2932 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2935 if (lockp == NULL) {
2936 PV_STAT(pc_chunk_tryfail++);
2939 m = reclaim_pv_chunk(pmap, lockp);
2943 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2944 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2945 dump_add_page(m->phys_addr);
2946 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2948 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2949 pc->pc_map[1] = PC_FREE1;
2950 pc->pc_map[2] = PC_FREE2;
2951 mtx_lock(&pv_chunks_mutex);
2952 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2953 mtx_unlock(&pv_chunks_mutex);
2954 pv = &pc->pc_pventry[0];
2955 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2956 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2957 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2962 * Returns the number of one bits within the given PV chunk map element.
2965 popcnt_pc_map_elem(uint64_t elem)
2970 * This simple method of counting the one bits performs well because
2971 * the given element typically contains more zero bits than one bits.
2974 for (; elem != 0; elem &= elem - 1)
2980 * Ensure that the number of spare PV entries in the specified pmap meets or
2981 * exceeds the given count, "needed".
2983 * The given PV list lock may be released.
2986 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2988 struct pch new_tail;
2989 struct pv_chunk *pc;
2993 rw_assert(&pvh_global_lock, RA_LOCKED);
2994 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2995 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2998 * Newly allocated PV chunks must be stored in a private list until
2999 * the required number of PV chunks have been allocated. Otherwise,
3000 * reclaim_pv_chunk() could recycle one of these chunks. In
3001 * contrast, these chunks must be added to the pmap upon allocation.
3003 TAILQ_INIT(&new_tail);
3006 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
3007 if ((cpu_feature2 & CPUID2_POPCNT) == 0) {
3008 free = popcnt_pc_map_elem(pc->pc_map[0]);
3009 free += popcnt_pc_map_elem(pc->pc_map[1]);
3010 free += popcnt_pc_map_elem(pc->pc_map[2]);
3012 free = popcntq(pc->pc_map[0]);
3013 free += popcntq(pc->pc_map[1]);
3014 free += popcntq(pc->pc_map[2]);
3019 if (avail >= needed)
3022 for (; avail < needed; avail += _NPCPV) {
3023 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3026 m = reclaim_pv_chunk(pmap, lockp);
3030 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
3031 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
3032 dump_add_page(m->phys_addr);
3033 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
3035 pc->pc_map[0] = PC_FREE0;
3036 pc->pc_map[1] = PC_FREE1;
3037 pc->pc_map[2] = PC_FREE2;
3038 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
3039 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
3040 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
3042 if (!TAILQ_EMPTY(&new_tail)) {
3043 mtx_lock(&pv_chunks_mutex);
3044 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
3045 mtx_unlock(&pv_chunks_mutex);
3050 * First find and then remove the pv entry for the specified pmap and virtual
3051 * address from the specified pv list. Returns the pv entry if found and NULL
3052 * otherwise. This operation can be performed on pv lists for either 4KB or
3053 * 2MB page mappings.
3055 static __inline pv_entry_t
3056 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3060 rw_assert(&pvh_global_lock, RA_LOCKED);
3061 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3062 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
3063 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
3072 * After demotion from a 2MB page mapping to 512 4KB page mappings,
3073 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
3074 * entries for each of the 4KB page mappings.
3077 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3078 struct rwlock **lockp)
3080 struct md_page *pvh;
3081 struct pv_chunk *pc;
3083 vm_offset_t va_last;
3087 rw_assert(&pvh_global_lock, RA_LOCKED);
3088 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3089 KASSERT((pa & PDRMASK) == 0,
3090 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
3091 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3094 * Transfer the 2mpage's pv entry for this mapping to the first
3095 * page's pv list. Once this transfer begins, the pv list lock
3096 * must not be released until the last pv entry is reinstantiated.
3098 pvh = pa_to_pvh(pa);
3099 va = trunc_2mpage(va);
3100 pv = pmap_pvh_remove(pvh, pmap, va);
3101 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
3102 m = PHYS_TO_VM_PAGE(pa);
3103 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3105 /* Instantiate the remaining NPTEPG - 1 pv entries. */
3106 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
3107 va_last = va + NBPDR - PAGE_SIZE;
3109 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
3110 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
3111 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
3112 for (field = 0; field < _NPCM; field++) {
3113 while (pc->pc_map[field]) {
3114 bit = bsfq(pc->pc_map[field]);
3115 pc->pc_map[field] &= ~(1ul << bit);
3116 pv = &pc->pc_pventry[field * 64 + bit];
3120 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3121 ("pmap_pv_demote_pde: page %p is not managed", m));
3122 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3128 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3129 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3132 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
3133 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3134 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
3136 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
3137 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
3141 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
3142 * replace the many pv entries for the 4KB page mappings by a single pv entry
3143 * for the 2MB page mapping.
3146 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3147 struct rwlock **lockp)
3149 struct md_page *pvh;
3151 vm_offset_t va_last;
3154 rw_assert(&pvh_global_lock, RA_LOCKED);
3155 KASSERT((pa & PDRMASK) == 0,
3156 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
3157 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3160 * Transfer the first page's pv entry for this mapping to the 2mpage's
3161 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
3162 * a transfer avoids the possibility that get_pv_entry() calls
3163 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
3164 * mappings that is being promoted.
3166 m = PHYS_TO_VM_PAGE(pa);
3167 va = trunc_2mpage(va);
3168 pv = pmap_pvh_remove(&m->md, pmap, va);
3169 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
3170 pvh = pa_to_pvh(pa);
3171 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3173 /* Free the remaining NPTEPG - 1 pv entries. */
3174 va_last = va + NBPDR - PAGE_SIZE;
3178 pmap_pvh_free(&m->md, pmap, va);
3179 } while (va < va_last);
3183 * First find and then destroy the pv entry for the specified pmap and virtual
3184 * address. This operation can be performed on pv lists for either 4KB or 2MB
3188 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
3192 pv = pmap_pvh_remove(pvh, pmap, va);
3193 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
3194 free_pv_entry(pmap, pv);
3198 * Conditionally create the PV entry for a 4KB page mapping if the required
3199 * memory can be allocated without resorting to reclamation.
3202 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
3203 struct rwlock **lockp)
3207 rw_assert(&pvh_global_lock, RA_LOCKED);
3208 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3209 /* Pass NULL instead of the lock pointer to disable reclamation. */
3210 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3212 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3213 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3221 * Conditionally create the PV entry for a 2MB page mapping if the required
3222 * memory can be allocated without resorting to reclamation.
3225 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
3226 struct rwlock **lockp)
3228 struct md_page *pvh;
3231 rw_assert(&pvh_global_lock, RA_LOCKED);
3232 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3233 /* Pass NULL instead of the lock pointer to disable reclamation. */
3234 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
3236 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
3237 pvh = pa_to_pvh(pa);
3238 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
3246 * Fills a page table page with mappings to consecutive physical pages.
3249 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
3253 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
3255 newpte += PAGE_SIZE;
3260 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
3261 * mapping is invalidated.
3264 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3266 struct rwlock *lock;
3270 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
3277 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3278 struct rwlock **lockp)
3280 pd_entry_t newpde, oldpde;
3281 pt_entry_t *firstpte, newpte;
3282 pt_entry_t PG_A, PG_G, PG_M, PG_RW, PG_V;
3285 struct spglist free;
3288 PG_G = pmap_global_bit(pmap);
3289 PG_A = pmap_accessed_bit(pmap);
3290 PG_M = pmap_modified_bit(pmap);
3291 PG_RW = pmap_rw_bit(pmap);
3292 PG_V = pmap_valid_bit(pmap);
3293 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
3295 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3297 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
3298 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
3299 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
3301 pmap_remove_pt_page(pmap, mpte);
3303 KASSERT((oldpde & PG_W) == 0,
3304 ("pmap_demote_pde: page table page for a wired mapping"
3308 * Invalidate the 2MB page mapping and return "failure" if the
3309 * mapping was never accessed or the allocation of the new
3310 * page table page fails. If the 2MB page mapping belongs to
3311 * the direct map region of the kernel's address space, then
3312 * the page allocation request specifies the highest possible
3313 * priority (VM_ALLOC_INTERRUPT). Otherwise, the priority is
3314 * normal. Page table pages are preallocated for every other
3315 * part of the kernel address space, so the direct map region
3316 * is the only part of the kernel address space that must be
3319 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
3320 pmap_pde_pindex(va), (va >= DMAP_MIN_ADDRESS && va <
3321 DMAP_MAX_ADDRESS ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
3322 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
3324 pmap_remove_pde(pmap, pde, trunc_2mpage(va), &free,
3326 pmap_invalidate_page(pmap, trunc_2mpage(va));
3327 pmap_free_zero_pages(&free);
3328 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx"
3329 " in pmap %p", va, pmap);
3332 if (va < VM_MAXUSER_ADDRESS)
3333 pmap_resident_count_inc(pmap, 1);
3335 mptepa = VM_PAGE_TO_PHYS(mpte);
3336 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
3337 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
3338 KASSERT((oldpde & PG_A) != 0,
3339 ("pmap_demote_pde: oldpde is missing PG_A"));
3340 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
3341 ("pmap_demote_pde: oldpde is missing PG_M"));
3342 newpte = oldpde & ~PG_PS;
3343 newpte = pmap_swap_pat(pmap, newpte);
3346 * If the page table page is new, initialize it.
3348 if (mpte->wire_count == 1) {
3349 mpte->wire_count = NPTEPG;
3350 pmap_fill_ptp(firstpte, newpte);
3352 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
3353 ("pmap_demote_pde: firstpte and newpte map different physical"
3357 * If the mapping has changed attributes, update the page table
3360 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
3361 pmap_fill_ptp(firstpte, newpte);
3364 * The spare PV entries must be reserved prior to demoting the
3365 * mapping, that is, prior to changing the PDE. Otherwise, the state
3366 * of the PDE and the PV lists will be inconsistent, which can result
3367 * in reclaim_pv_chunk() attempting to remove a PV entry from the
3368 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
3369 * PV entry for the 2MB page mapping that is being demoted.
3371 if ((oldpde & PG_MANAGED) != 0)
3372 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
3375 * Demote the mapping. This pmap is locked. The old PDE has
3376 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
3377 * set. Thus, there is no danger of a race with another
3378 * processor changing the setting of PG_A and/or PG_M between
3379 * the read above and the store below.
3381 if (workaround_erratum383)
3382 pmap_update_pde(pmap, va, pde, newpde);
3384 pde_store(pde, newpde);
3387 * Invalidate a stale recursive mapping of the page table page.
3389 if (va >= VM_MAXUSER_ADDRESS)
3390 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3393 * Demote the PV entry.
3395 if ((oldpde & PG_MANAGED) != 0)
3396 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
3398 atomic_add_long(&pmap_pde_demotions, 1);
3399 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx"
3400 " in pmap %p", va, pmap);
3405 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
3408 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3414 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
3415 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3416 mpte = pmap_lookup_pt_page(pmap, va);
3418 panic("pmap_remove_kernel_pde: Missing pt page.");
3420 pmap_remove_pt_page(pmap, mpte);
3421 mptepa = VM_PAGE_TO_PHYS(mpte);
3422 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
3425 * Initialize the page table page.
3427 pagezero((void *)PHYS_TO_DMAP(mptepa));
3430 * Demote the mapping.
3432 if (workaround_erratum383)
3433 pmap_update_pde(pmap, va, pde, newpde);
3435 pde_store(pde, newpde);
3438 * Invalidate a stale recursive mapping of the page table page.
3440 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
3444 * pmap_remove_pde: do the things to unmap a superpage in a process
3447 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
3448 struct spglist *free, struct rwlock **lockp)
3450 struct md_page *pvh;
3452 vm_offset_t eva, va;
3454 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
3456 PG_G = pmap_global_bit(pmap);
3457 PG_A = pmap_accessed_bit(pmap);
3458 PG_M = pmap_modified_bit(pmap);
3459 PG_RW = pmap_rw_bit(pmap);
3461 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3462 KASSERT((sva & PDRMASK) == 0,
3463 ("pmap_remove_pde: sva is not 2mpage aligned"));
3464 oldpde = pte_load_clear(pdq);
3466 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
3469 * Machines that don't support invlpg, also don't support
3473 pmap_invalidate_page(kernel_pmap, sva);
3474 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
3475 if (oldpde & PG_MANAGED) {
3476 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
3477 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
3478 pmap_pvh_free(pvh, pmap, sva);
3480 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3481 va < eva; va += PAGE_SIZE, m++) {
3482 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3485 vm_page_aflag_set(m, PGA_REFERENCED);
3486 if (TAILQ_EMPTY(&m->md.pv_list) &&
3487 TAILQ_EMPTY(&pvh->pv_list))
3488 vm_page_aflag_clear(m, PGA_WRITEABLE);
3491 if (pmap == kernel_pmap) {
3492 pmap_remove_kernel_pde(pmap, pdq, sva);
3494 mpte = pmap_lookup_pt_page(pmap, sva);
3496 pmap_remove_pt_page(pmap, mpte);
3497 pmap_resident_count_dec(pmap, 1);
3498 KASSERT(mpte->wire_count == NPTEPG,
3499 ("pmap_remove_pde: pte page wire count error"));
3500 mpte->wire_count = 0;
3501 pmap_add_delayed_free_list(mpte, free, FALSE);
3502 atomic_subtract_int(&cnt.v_wire_count, 1);
3505 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
3509 * pmap_remove_pte: do the things to unmap a page in a process
3512 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3513 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
3515 struct md_page *pvh;
3516 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
3519 PG_A = pmap_accessed_bit(pmap);
3520 PG_M = pmap_modified_bit(pmap);
3521 PG_RW = pmap_rw_bit(pmap);
3523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3524 oldpte = pte_load_clear(ptq);
3526 pmap->pm_stats.wired_count -= 1;
3527 pmap_resident_count_dec(pmap, 1);
3528 if (oldpte & PG_MANAGED) {
3529 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3530 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3533 vm_page_aflag_set(m, PGA_REFERENCED);
3534 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
3535 pmap_pvh_free(&m->md, pmap, va);
3536 if (TAILQ_EMPTY(&m->md.pv_list) &&
3537 (m->flags & PG_FICTITIOUS) == 0) {
3538 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3539 if (TAILQ_EMPTY(&pvh->pv_list))
3540 vm_page_aflag_clear(m, PGA_WRITEABLE);
3543 return (pmap_unuse_pt(pmap, va, ptepde, free));
3547 * Remove a single page from a process address space
3550 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
3551 struct spglist *free)
3553 struct rwlock *lock;
3554 pt_entry_t *pte, PG_V;
3556 PG_V = pmap_valid_bit(pmap);
3557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3558 if ((*pde & PG_V) == 0)
3560 pte = pmap_pde_to_pte(pde, va);
3561 if ((*pte & PG_V) == 0)
3564 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
3567 pmap_invalidate_page(pmap, va);
3571 * Remove the given range of addresses from the specified map.
3573 * It is assumed that the start and end are properly
3574 * rounded to the page size.
3577 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3579 struct rwlock *lock;
3580 vm_offset_t va, va_next;
3581 pml4_entry_t *pml4e;
3583 pd_entry_t ptpaddr, *pde;
3584 pt_entry_t *pte, PG_G, PG_V;
3585 struct spglist free;
3588 PG_G = pmap_global_bit(pmap);
3589 PG_V = pmap_valid_bit(pmap);
3592 * Perform an unsynchronized read. This is, however, safe.
3594 if (pmap->pm_stats.resident_count == 0)
3600 rw_rlock(&pvh_global_lock);
3604 * special handling of removing one page. a very
3605 * common operation and easy to short circuit some
3608 if (sva + PAGE_SIZE == eva) {
3609 pde = pmap_pde(pmap, sva);
3610 if (pde && (*pde & PG_PS) == 0) {
3611 pmap_remove_page(pmap, sva, pde, &free);
3617 for (; sva < eva; sva = va_next) {
3619 if (pmap->pm_stats.resident_count == 0)
3622 pml4e = pmap_pml4e(pmap, sva);
3623 if ((*pml4e & PG_V) == 0) {
3624 va_next = (sva + NBPML4) & ~PML4MASK;
3630 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3631 if ((*pdpe & PG_V) == 0) {
3632 va_next = (sva + NBPDP) & ~PDPMASK;
3639 * Calculate index for next page table.
3641 va_next = (sva + NBPDR) & ~PDRMASK;
3645 pde = pmap_pdpe_to_pde(pdpe, sva);
3649 * Weed out invalid mappings.
3655 * Check for large page.
3657 if ((ptpaddr & PG_PS) != 0) {
3659 * Are we removing the entire large page? If not,
3660 * demote the mapping and fall through.
3662 if (sva + NBPDR == va_next && eva >= va_next) {
3664 * The TLB entry for a PG_G mapping is
3665 * invalidated by pmap_remove_pde().
3667 if ((ptpaddr & PG_G) == 0)
3669 pmap_remove_pde(pmap, pde, sva, &free, &lock);
3671 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
3673 /* The large page mapping was destroyed. */
3680 * Limit our scan to either the end of the va represented
3681 * by the current page table page, or to the end of the
3682 * range being removed.
3688 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3691 if (va != va_next) {
3692 pmap_invalidate_range(pmap, va, sva);
3697 if ((*pte & PG_G) == 0)
3699 else if (va == va_next)
3701 if (pmap_remove_pte(pmap, pte, sva, ptpaddr, &free,
3708 pmap_invalidate_range(pmap, va, sva);
3714 pmap_invalidate_all(pmap);
3715 rw_runlock(&pvh_global_lock);
3717 pmap_free_zero_pages(&free);
3721 * Routine: pmap_remove_all
3723 * Removes this physical page from
3724 * all physical maps in which it resides.
3725 * Reflects back modify bits to the pager.
3728 * Original versions of this routine were very
3729 * inefficient because they iteratively called
3730 * pmap_remove (slow...)
3734 pmap_remove_all(vm_page_t m)
3736 struct md_page *pvh;
3739 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
3742 struct spglist free;
3744 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3745 ("pmap_remove_all: page %p is not managed", m));
3747 rw_wlock(&pvh_global_lock);
3748 if ((m->flags & PG_FICTITIOUS) != 0)
3749 goto small_mappings;
3750 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3751 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3755 pde = pmap_pde(pmap, va);
3756 (void)pmap_demote_pde(pmap, pde, va);
3760 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3763 PG_A = pmap_accessed_bit(pmap);
3764 PG_M = pmap_modified_bit(pmap);
3765 PG_RW = pmap_rw_bit(pmap);
3766 pmap_resident_count_dec(pmap, 1);
3767 pde = pmap_pde(pmap, pv->pv_va);
3768 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3769 " a 2mpage in page %p's pv list", m));
3770 pte = pmap_pde_to_pte(pde, pv->pv_va);
3771 tpte = pte_load_clear(pte);
3773 pmap->pm_stats.wired_count--;
3775 vm_page_aflag_set(m, PGA_REFERENCED);
3778 * Update the vm_page_t clean and reference bits.
3780 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3782 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
3783 pmap_invalidate_page(pmap, pv->pv_va);
3784 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3786 free_pv_entry(pmap, pv);
3789 vm_page_aflag_clear(m, PGA_WRITEABLE);
3790 rw_wunlock(&pvh_global_lock);
3791 pmap_free_zero_pages(&free);
3795 * pmap_protect_pde: do the things to protect a 2mpage in a process
3798 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3800 pd_entry_t newpde, oldpde;
3801 vm_offset_t eva, va;
3803 boolean_t anychanged;
3804 pt_entry_t PG_G, PG_M, PG_RW;
3806 PG_G = pmap_global_bit(pmap);
3807 PG_M = pmap_modified_bit(pmap);
3808 PG_RW = pmap_rw_bit(pmap);
3810 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3811 KASSERT((sva & PDRMASK) == 0,
3812 ("pmap_protect_pde: sva is not 2mpage aligned"));
3815 oldpde = newpde = *pde;
3816 if (oldpde & PG_MANAGED) {
3818 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3819 va < eva; va += PAGE_SIZE, m++)
3820 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3823 if ((prot & VM_PROT_WRITE) == 0)
3824 newpde &= ~(PG_RW | PG_M);
3825 if ((prot & VM_PROT_EXECUTE) == 0)
3827 if (newpde != oldpde) {
3828 if (!atomic_cmpset_long(pde, oldpde, newpde))
3831 pmap_invalidate_page(pmap, sva);
3835 return (anychanged);
3839 * Set the physical protection on the
3840 * specified range of this map as requested.
3843 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3845 vm_offset_t va_next;
3846 pml4_entry_t *pml4e;
3848 pd_entry_t ptpaddr, *pde;
3849 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
3850 boolean_t anychanged, pv_lists_locked;
3852 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3853 if (prot == VM_PROT_NONE) {
3854 pmap_remove(pmap, sva, eva);
3858 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3859 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3862 PG_G = pmap_global_bit(pmap);
3863 PG_M = pmap_modified_bit(pmap);
3864 PG_V = pmap_valid_bit(pmap);
3865 PG_RW = pmap_rw_bit(pmap);
3866 pv_lists_locked = FALSE;
3871 for (; sva < eva; sva = va_next) {
3873 pml4e = pmap_pml4e(pmap, sva);
3874 if ((*pml4e & PG_V) == 0) {
3875 va_next = (sva + NBPML4) & ~PML4MASK;
3881 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
3882 if ((*pdpe & PG_V) == 0) {
3883 va_next = (sva + NBPDP) & ~PDPMASK;
3889 va_next = (sva + NBPDR) & ~PDRMASK;
3893 pde = pmap_pdpe_to_pde(pdpe, sva);
3897 * Weed out invalid mappings.
3903 * Check for large page.
3905 if ((ptpaddr & PG_PS) != 0) {
3907 * Are we protecting the entire large page? If not,
3908 * demote the mapping and fall through.
3910 if (sva + NBPDR == va_next && eva >= va_next) {
3912 * The TLB entry for a PG_G mapping is
3913 * invalidated by pmap_protect_pde().
3915 if (pmap_protect_pde(pmap, pde, sva, prot))
3919 if (!pv_lists_locked) {
3920 pv_lists_locked = TRUE;
3921 if (!rw_try_rlock(&pvh_global_lock)) {
3923 pmap_invalidate_all(
3926 rw_rlock(&pvh_global_lock);
3930 if (!pmap_demote_pde(pmap, pde, sva)) {
3932 * The large page mapping was
3943 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3945 pt_entry_t obits, pbits;
3949 obits = pbits = *pte;
3950 if ((pbits & PG_V) == 0)
3953 if ((prot & VM_PROT_WRITE) == 0) {
3954 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3955 (PG_MANAGED | PG_M | PG_RW)) {
3956 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3959 pbits &= ~(PG_RW | PG_M);
3961 if ((prot & VM_PROT_EXECUTE) == 0)
3964 if (pbits != obits) {
3965 if (!atomic_cmpset_long(pte, obits, pbits))
3968 pmap_invalidate_page(pmap, sva);
3975 pmap_invalidate_all(pmap);
3976 if (pv_lists_locked)
3977 rw_runlock(&pvh_global_lock);
3982 * Tries to promote the 512, contiguous 4KB page mappings that are within a
3983 * single page table page (PTP) to a single 2MB page mapping. For promotion
3984 * to occur, two conditions must be met: (1) the 4KB page mappings must map
3985 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
3986 * identical characteristics.
3989 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
3990 struct rwlock **lockp)
3993 pt_entry_t *firstpte, oldpte, pa, *pte;
3994 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V;
3995 vm_offset_t oldpteva;
3999 PG_A = pmap_accessed_bit(pmap);
4000 PG_G = pmap_global_bit(pmap);
4001 PG_M = pmap_modified_bit(pmap);
4002 PG_V = pmap_valid_bit(pmap);
4003 PG_RW = pmap_rw_bit(pmap);
4004 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4006 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4009 * Examine the first PTE in the specified PTP. Abort if this PTE is
4010 * either invalid, unused, or does not map the first 4KB physical page
4011 * within a 2MB page.
4013 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
4016 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
4017 atomic_add_long(&pmap_pde_p_failures, 1);
4018 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4019 " in pmap %p", va, pmap);
4022 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
4024 * When PG_M is already clear, PG_RW can be cleared without
4025 * a TLB invalidation.
4027 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
4033 * Examine each of the other PTEs in the specified PTP. Abort if this
4034 * PTE maps an unexpected 4KB physical page or does not have identical
4035 * characteristics to the first PTE.
4037 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
4038 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
4041 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
4042 atomic_add_long(&pmap_pde_p_failures, 1);
4043 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4044 " in pmap %p", va, pmap);
4047 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
4049 * When PG_M is already clear, PG_RW can be cleared
4050 * without a TLB invalidation.
4052 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
4055 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
4057 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
4058 " in pmap %p", oldpteva, pmap);
4060 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
4061 atomic_add_long(&pmap_pde_p_failures, 1);
4062 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
4063 " in pmap %p", va, pmap);
4070 * Save the page table page in its current state until the PDE
4071 * mapping the superpage is demoted by pmap_demote_pde() or
4072 * destroyed by pmap_remove_pde().
4074 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4075 KASSERT(mpte >= vm_page_array &&
4076 mpte < &vm_page_array[vm_page_array_size],
4077 ("pmap_promote_pde: page table page is out of range"));
4078 KASSERT(mpte->pindex == pmap_pde_pindex(va),
4079 ("pmap_promote_pde: page table page's pindex is wrong"));
4080 if (pmap_insert_pt_page(pmap, mpte)) {
4081 atomic_add_long(&pmap_pde_p_failures, 1);
4083 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
4089 * Promote the pv entries.
4091 if ((newpde & PG_MANAGED) != 0)
4092 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
4095 * Propagate the PAT index to its proper position.
4097 newpde = pmap_swap_pat(pmap, newpde);
4100 * Map the superpage.
4102 if (workaround_erratum383)
4103 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
4105 pde_store(pde, PG_PS | newpde);
4107 atomic_add_long(&pmap_pde_promotions, 1);
4108 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
4109 " in pmap %p", va, pmap);
4113 * Insert the given physical page (p) at
4114 * the specified virtual address (v) in the
4115 * target physical map with the protection requested.
4117 * If specified, the page will be wired down, meaning
4118 * that the related pte can not be reclaimed.
4120 * NB: This is the only routine which MAY NOT lazy-evaluate
4121 * or lose information. That is, this routine must actually
4122 * insert this page into the given map NOW.
4125 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4126 u_int flags, int8_t psind __unused)
4128 struct rwlock *lock;
4130 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
4131 pt_entry_t newpte, origpte;
4137 PG_A = pmap_accessed_bit(pmap);
4138 PG_G = pmap_global_bit(pmap);
4139 PG_M = pmap_modified_bit(pmap);
4140 PG_V = pmap_valid_bit(pmap);
4141 PG_RW = pmap_rw_bit(pmap);
4143 va = trunc_page(va);
4144 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
4145 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
4146 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
4148 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
4149 va >= kmi.clean_eva,
4150 ("pmap_enter: managed mapping within the clean submap"));
4151 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
4152 VM_OBJECT_ASSERT_LOCKED(m->object);
4153 pa = VM_PAGE_TO_PHYS(m);
4154 newpte = (pt_entry_t)(pa | PG_A | PG_V);
4155 if ((flags & VM_PROT_WRITE) != 0)
4157 if ((prot & VM_PROT_WRITE) != 0)
4159 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
4160 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
4161 if ((prot & VM_PROT_EXECUTE) == 0)
4163 if ((flags & PMAP_ENTER_WIRED) != 0)
4165 if (va < VM_MAXUSER_ADDRESS)
4167 if (pmap == kernel_pmap)
4169 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, 0);
4172 * Set modified bit gratuitously for writeable mappings if
4173 * the page is unmanaged. We do not want to take a fault
4174 * to do the dirty bit accounting for these mappings.
4176 if ((m->oflags & VPO_UNMANAGED) != 0) {
4177 if ((newpte & PG_RW) != 0)
4184 rw_rlock(&pvh_global_lock);
4188 * In the case that a page table page is not
4189 * resident, we are creating it here.
4192 pde = pmap_pde(pmap, va);
4193 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
4194 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
4195 pte = pmap_pde_to_pte(pde, va);
4196 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
4197 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4200 } else if (va < VM_MAXUSER_ADDRESS) {
4202 * Here if the pte page isn't mapped, or if it has been
4205 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
4206 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
4207 nosleep ? NULL : &lock);
4208 if (mpte == NULL && nosleep) {
4211 rw_runlock(&pvh_global_lock);
4213 return (KERN_RESOURCE_SHORTAGE);
4217 panic("pmap_enter: invalid page directory va=%#lx", va);
4222 * Is the specified virtual address already mapped?
4224 if ((origpte & PG_V) != 0) {
4226 * Wiring change, just update stats. We don't worry about
4227 * wiring PT pages as they remain resident as long as there
4228 * are valid mappings in them. Hence, if a user page is wired,
4229 * the PT page will be also.
4231 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
4232 pmap->pm_stats.wired_count++;
4233 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
4234 pmap->pm_stats.wired_count--;
4237 * Remove the extra PT page reference.
4241 KASSERT(mpte->wire_count > 0,
4242 ("pmap_enter: missing reference to page table page,"
4247 * Has the physical page changed?
4249 opa = origpte & PG_FRAME;
4252 * No, might be a protection or wiring change.
4254 if ((origpte & PG_MANAGED) != 0) {
4255 newpte |= PG_MANAGED;
4256 if ((newpte & PG_RW) != 0)
4257 vm_page_aflag_set(m, PGA_WRITEABLE);
4259 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
4265 * Increment the counters.
4267 if ((newpte & PG_W) != 0)
4268 pmap->pm_stats.wired_count++;
4269 pmap_resident_count_inc(pmap, 1);
4273 * Enter on the PV list if part of our managed memory.
4275 if ((m->oflags & VPO_UNMANAGED) == 0) {
4276 newpte |= PG_MANAGED;
4277 pv = get_pv_entry(pmap, &lock);
4279 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
4280 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4282 if ((newpte & PG_RW) != 0)
4283 vm_page_aflag_set(m, PGA_WRITEABLE);
4289 if ((origpte & PG_V) != 0) {
4291 origpte = pte_load_store(pte, newpte);
4292 opa = origpte & PG_FRAME;
4294 if ((origpte & PG_MANAGED) != 0) {
4295 om = PHYS_TO_VM_PAGE(opa);
4296 if ((origpte & (PG_M | PG_RW)) == (PG_M |
4299 if ((origpte & PG_A) != 0)
4300 vm_page_aflag_set(om, PGA_REFERENCED);
4301 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
4302 pmap_pvh_free(&om->md, pmap, va);
4303 if ((om->aflags & PGA_WRITEABLE) != 0 &&
4304 TAILQ_EMPTY(&om->md.pv_list) &&
4305 ((om->flags & PG_FICTITIOUS) != 0 ||
4306 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
4307 vm_page_aflag_clear(om, PGA_WRITEABLE);
4309 } else if ((newpte & PG_M) == 0 && (origpte & (PG_M |
4310 PG_RW)) == (PG_M | PG_RW)) {
4311 if ((origpte & PG_MANAGED) != 0)
4315 * Although the PTE may still have PG_RW set, TLB
4316 * invalidation may nonetheless be required because
4317 * the PTE no longer has PG_M set.
4319 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
4321 * This PTE change does not require TLB invalidation.
4325 if ((origpte & PG_A) != 0)
4326 pmap_invalidate_page(pmap, va);
4328 pte_store(pte, newpte);
4333 * If both the page table page and the reservation are fully
4334 * populated, then attempt promotion.
4336 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
4337 pmap_ps_enabled(pmap) &&
4338 (m->flags & PG_FICTITIOUS) == 0 &&
4339 vm_reserv_level_iffullpop(m) == 0)
4340 pmap_promote_pde(pmap, pde, va, &lock);
4344 rw_runlock(&pvh_global_lock);
4346 return (KERN_SUCCESS);
4350 * Tries to create a 2MB page mapping. Returns TRUE if successful and FALSE
4351 * otherwise. Fails if (1) a page table page cannot be allocated without
4352 * blocking, (2) a mapping already exists at the specified virtual address, or
4353 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
4356 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
4357 struct rwlock **lockp)
4359 pd_entry_t *pde, newpde;
4362 struct spglist free;
4364 PG_V = pmap_valid_bit(pmap);
4365 rw_assert(&pvh_global_lock, RA_LOCKED);
4366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4368 if ((mpde = pmap_allocpde(pmap, va, NULL)) == NULL) {
4369 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4370 " in pmap %p", va, pmap);
4373 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpde));
4374 pde = &pde[pmap_pde_index(va)];
4375 if ((*pde & PG_V) != 0) {
4376 KASSERT(mpde->wire_count > 1,
4377 ("pmap_enter_pde: mpde's wire count is too low"));
4379 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4380 " in pmap %p", va, pmap);
4383 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
4385 if ((m->oflags & VPO_UNMANAGED) == 0) {
4386 newpde |= PG_MANAGED;
4389 * Abort this mapping if its PV entry could not be created.
4391 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m),
4394 if (pmap_unwire_ptp(pmap, va, mpde, &free)) {
4395 pmap_invalidate_page(pmap, va);
4396 pmap_free_zero_pages(&free);
4398 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4399 " in pmap %p", va, pmap);
4403 if ((prot & VM_PROT_EXECUTE) == 0)
4405 if (va < VM_MAXUSER_ADDRESS)
4409 * Increment counters.
4411 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4414 * Map the superpage.
4416 pde_store(pde, newpde);
4418 atomic_add_long(&pmap_pde_mappings, 1);
4419 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
4420 " in pmap %p", va, pmap);
4425 * Maps a sequence of resident pages belonging to the same object.
4426 * The sequence begins with the given page m_start. This page is
4427 * mapped at the given virtual address start. Each subsequent page is
4428 * mapped at a virtual address that is offset from start by the same
4429 * amount as the page is offset from m_start within the object. The
4430 * last page in the sequence is the page with the largest offset from
4431 * m_start that can be mapped at a virtual address less than the given
4432 * virtual address end. Not every virtual page between start and end
4433 * is mapped; only those for which a resident page exists with the
4434 * corresponding offset from m_start are mapped.
4437 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4438 vm_page_t m_start, vm_prot_t prot)
4440 struct rwlock *lock;
4443 vm_pindex_t diff, psize;
4445 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4447 psize = atop(end - start);
4451 rw_rlock(&pvh_global_lock);
4453 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
4454 va = start + ptoa(diff);
4455 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4456 m->psind == 1 && pmap_ps_enabled(pmap) &&
4457 pmap_enter_pde(pmap, va, m, prot, &lock))
4458 m = &m[NBPDR / PAGE_SIZE - 1];
4460 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
4462 m = TAILQ_NEXT(m, listq);
4466 rw_runlock(&pvh_global_lock);
4471 * this code makes some *MAJOR* assumptions:
4472 * 1. Current pmap & pmap exists.
4475 * 4. No page table pages.
4476 * but is *MUCH* faster than pmap_enter...
4480 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
4482 struct rwlock *lock;
4485 rw_rlock(&pvh_global_lock);
4487 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
4490 rw_runlock(&pvh_global_lock);
4495 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4496 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
4498 struct spglist free;
4499 pt_entry_t *pte, PG_V;
4502 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
4503 (m->oflags & VPO_UNMANAGED) != 0,
4504 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4505 PG_V = pmap_valid_bit(pmap);
4506 rw_assert(&pvh_global_lock, RA_LOCKED);
4507 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4510 * In the case that a page table page is not
4511 * resident, we are creating it here.
4513 if (va < VM_MAXUSER_ADDRESS) {
4514 vm_pindex_t ptepindex;
4518 * Calculate pagetable page index
4520 ptepindex = pmap_pde_pindex(va);
4521 if (mpte && (mpte->pindex == ptepindex)) {
4525 * Get the page directory entry
4527 ptepa = pmap_pde(pmap, va);
4530 * If the page table page is mapped, we just increment
4531 * the hold count, and activate it. Otherwise, we
4532 * attempt to allocate a page table page. If this
4533 * attempt fails, we don't retry. Instead, we give up.
4535 if (ptepa && (*ptepa & PG_V) != 0) {
4538 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
4542 * Pass NULL instead of the PV list lock
4543 * pointer, because we don't intend to sleep.
4545 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
4550 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
4551 pte = &pte[pmap_pte_index(va)];
4565 * Enter on the PV list if part of our managed memory.
4567 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4568 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
4571 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
4572 pmap_invalidate_page(pmap, va);
4573 pmap_free_zero_pages(&free);
4581 * Increment counters
4583 pmap_resident_count_inc(pmap, 1);
4585 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 0);
4586 if ((prot & VM_PROT_EXECUTE) == 0)
4590 * Now validate mapping with RO protection
4592 if ((m->oflags & VPO_UNMANAGED) != 0)
4593 pte_store(pte, pa | PG_V | PG_U);
4595 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
4600 * Make a temporary mapping for a physical address. This is only intended
4601 * to be used for panic dumps.
4604 pmap_kenter_temporary(vm_paddr_t pa, int i)
4608 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4609 pmap_kenter(va, pa);
4611 return ((void *)crashdumpmap);
4615 * This code maps large physical mmap regions into the
4616 * processor address space. Note that some shortcuts
4617 * are taken, but the code works.
4620 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
4621 vm_pindex_t pindex, vm_size_t size)
4624 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4625 vm_paddr_t pa, ptepa;
4629 PG_A = pmap_accessed_bit(pmap);
4630 PG_M = pmap_modified_bit(pmap);
4631 PG_V = pmap_valid_bit(pmap);
4632 PG_RW = pmap_rw_bit(pmap);
4634 VM_OBJECT_ASSERT_WLOCKED(object);
4635 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4636 ("pmap_object_init_pt: non-device object"));
4637 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4638 if (!pmap_ps_enabled(pmap))
4640 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4642 p = vm_page_lookup(object, pindex);
4643 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4644 ("pmap_object_init_pt: invalid page %p", p));
4645 pat_mode = p->md.pat_mode;
4648 * Abort the mapping if the first page is not physically
4649 * aligned to a 2MB page boundary.
4651 ptepa = VM_PAGE_TO_PHYS(p);
4652 if (ptepa & (NBPDR - 1))
4656 * Skip the first page. Abort the mapping if the rest of
4657 * the pages are not physically contiguous or have differing
4658 * memory attributes.
4660 p = TAILQ_NEXT(p, listq);
4661 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4663 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4664 ("pmap_object_init_pt: invalid page %p", p));
4665 if (pa != VM_PAGE_TO_PHYS(p) ||
4666 pat_mode != p->md.pat_mode)
4668 p = TAILQ_NEXT(p, listq);
4672 * Map using 2MB pages. Since "ptepa" is 2M aligned and
4673 * "size" is a multiple of 2M, adding the PAT setting to "pa"
4674 * will not affect the termination of this loop.
4677 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
4678 pa < ptepa + size; pa += NBPDR) {
4679 pdpg = pmap_allocpde(pmap, addr, NULL);
4682 * The creation of mappings below is only an
4683 * optimization. If a page directory page
4684 * cannot be allocated without blocking,
4685 * continue on to the next mapping rather than
4691 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4692 pde = &pde[pmap_pde_index(addr)];
4693 if ((*pde & PG_V) == 0) {
4694 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4695 PG_U | PG_RW | PG_V);
4696 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
4697 atomic_add_long(&pmap_pde_mappings, 1);
4699 /* Continue on if the PDE is already valid. */
4701 KASSERT(pdpg->wire_count > 0,
4702 ("pmap_object_init_pt: missing reference "
4703 "to page directory page, va: 0x%lx", addr));
4712 * Clear the wired attribute from the mappings for the specified range of
4713 * addresses in the given pmap. Every valid mapping within that range
4714 * must have the wired attribute set. In contrast, invalid mappings
4715 * cannot have the wired attribute set, so they are ignored.
4717 * The wired attribute of the page table entry is not a hardware feature,
4718 * so there is no need to invalidate any TLB entries.
4721 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4723 vm_offset_t va_next;
4724 pml4_entry_t *pml4e;
4727 pt_entry_t *pte, PG_V;
4728 boolean_t pv_lists_locked;
4730 PG_V = pmap_valid_bit(pmap);
4731 pv_lists_locked = FALSE;
4734 for (; sva < eva; sva = va_next) {
4735 pml4e = pmap_pml4e(pmap, sva);
4736 if ((*pml4e & PG_V) == 0) {
4737 va_next = (sva + NBPML4) & ~PML4MASK;
4742 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
4743 if ((*pdpe & PG_V) == 0) {
4744 va_next = (sva + NBPDP) & ~PDPMASK;
4749 va_next = (sva + NBPDR) & ~PDRMASK;
4752 pde = pmap_pdpe_to_pde(pdpe, sva);
4753 if ((*pde & PG_V) == 0)
4755 if ((*pde & PG_PS) != 0) {
4756 if ((*pde & PG_W) == 0)
4757 panic("pmap_unwire: pde %#jx is missing PG_W",
4761 * Are we unwiring the entire large page? If not,
4762 * demote the mapping and fall through.
4764 if (sva + NBPDR == va_next && eva >= va_next) {
4765 atomic_clear_long(pde, PG_W);
4766 pmap->pm_stats.wired_count -= NBPDR /
4770 if (!pv_lists_locked) {
4771 pv_lists_locked = TRUE;
4772 if (!rw_try_rlock(&pvh_global_lock)) {
4774 rw_rlock(&pvh_global_lock);
4779 if (!pmap_demote_pde(pmap, pde, sva))
4780 panic("pmap_unwire: demotion failed");
4785 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
4787 if ((*pte & PG_V) == 0)
4789 if ((*pte & PG_W) == 0)
4790 panic("pmap_unwire: pte %#jx is missing PG_W",
4794 * PG_W must be cleared atomically. Although the pmap
4795 * lock synchronizes access to PG_W, another processor
4796 * could be setting PG_M and/or PG_A concurrently.
4798 atomic_clear_long(pte, PG_W);
4799 pmap->pm_stats.wired_count--;
4802 if (pv_lists_locked)
4803 rw_runlock(&pvh_global_lock);
4808 * Copy the range specified by src_addr/len
4809 * from the source map to the range dst_addr/len
4810 * in the destination map.
4812 * This routine is only advisory and need not do anything.
4816 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4817 vm_offset_t src_addr)
4819 struct rwlock *lock;
4820 struct spglist free;
4822 vm_offset_t end_addr = src_addr + len;
4823 vm_offset_t va_next;
4824 pt_entry_t PG_A, PG_M, PG_V;
4826 if (dst_addr != src_addr)
4829 if (dst_pmap->pm_type != src_pmap->pm_type)
4833 * EPT page table entries that require emulation of A/D bits are
4834 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
4835 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
4836 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
4837 * implementations flag an EPT misconfiguration for exec-only
4838 * mappings we skip this function entirely for emulated pmaps.
4840 if (pmap_emulate_ad_bits(dst_pmap))
4844 rw_rlock(&pvh_global_lock);
4845 if (dst_pmap < src_pmap) {
4846 PMAP_LOCK(dst_pmap);
4847 PMAP_LOCK(src_pmap);
4849 PMAP_LOCK(src_pmap);
4850 PMAP_LOCK(dst_pmap);
4853 PG_A = pmap_accessed_bit(dst_pmap);
4854 PG_M = pmap_modified_bit(dst_pmap);
4855 PG_V = pmap_valid_bit(dst_pmap);
4857 for (addr = src_addr; addr < end_addr; addr = va_next) {
4858 pt_entry_t *src_pte, *dst_pte;
4859 vm_page_t dstmpde, dstmpte, srcmpte;
4860 pml4_entry_t *pml4e;
4862 pd_entry_t srcptepaddr, *pde;
4864 KASSERT(addr < UPT_MIN_ADDRESS,
4865 ("pmap_copy: invalid to pmap_copy page tables"));
4867 pml4e = pmap_pml4e(src_pmap, addr);
4868 if ((*pml4e & PG_V) == 0) {
4869 va_next = (addr + NBPML4) & ~PML4MASK;
4875 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
4876 if ((*pdpe & PG_V) == 0) {
4877 va_next = (addr + NBPDP) & ~PDPMASK;
4883 va_next = (addr + NBPDR) & ~PDRMASK;
4887 pde = pmap_pdpe_to_pde(pdpe, addr);
4889 if (srcptepaddr == 0)
4892 if (srcptepaddr & PG_PS) {
4893 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4895 dstmpde = pmap_allocpde(dst_pmap, addr, NULL);
4896 if (dstmpde == NULL)
4898 pde = (pd_entry_t *)
4899 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpde));
4900 pde = &pde[pmap_pde_index(addr)];
4901 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
4902 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4903 PG_PS_FRAME, &lock))) {
4904 *pde = srcptepaddr & ~PG_W;
4905 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
4907 dstmpde->wire_count--;
4911 srcptepaddr &= PG_FRAME;
4912 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
4913 KASSERT(srcmpte->wire_count > 0,
4914 ("pmap_copy: source page table page is unused"));
4916 if (va_next > end_addr)
4919 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
4920 src_pte = &src_pte[pmap_pte_index(addr)];
4922 while (addr < va_next) {
4926 * we only virtual copy managed pages
4928 if ((ptetemp & PG_MANAGED) != 0) {
4929 if (dstmpte != NULL &&
4930 dstmpte->pindex == pmap_pde_pindex(addr))
4931 dstmpte->wire_count++;
4932 else if ((dstmpte = pmap_allocpte(dst_pmap,
4933 addr, NULL)) == NULL)
4935 dst_pte = (pt_entry_t *)
4936 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
4937 dst_pte = &dst_pte[pmap_pte_index(addr)];
4938 if (*dst_pte == 0 &&
4939 pmap_try_insert_pv_entry(dst_pmap, addr,
4940 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
4943 * Clear the wired, modified, and
4944 * accessed (referenced) bits
4947 *dst_pte = ptetemp & ~(PG_W | PG_M |
4949 pmap_resident_count_inc(dst_pmap, 1);
4952 if (pmap_unwire_ptp(dst_pmap, addr,
4954 pmap_invalidate_page(dst_pmap,
4956 pmap_free_zero_pages(&free);
4960 if (dstmpte->wire_count >= srcmpte->wire_count)
4970 rw_runlock(&pvh_global_lock);
4971 PMAP_UNLOCK(src_pmap);
4972 PMAP_UNLOCK(dst_pmap);
4976 * pmap_zero_page zeros the specified hardware page by mapping
4977 * the page into KVM and using bzero to clear its contents.
4980 pmap_zero_page(vm_page_t m)
4982 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4984 pagezero((void *)va);
4988 * pmap_zero_page_area zeros the specified hardware page by mapping
4989 * the page into KVM and using bzero to clear its contents.
4991 * off and size may not cover an area beyond a single hardware page.
4994 pmap_zero_page_area(vm_page_t m, int off, int size)
4996 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
4998 if (off == 0 && size == PAGE_SIZE)
4999 pagezero((void *)va);
5001 bzero((char *)va + off, size);
5005 * pmap_zero_page_idle zeros the specified hardware page by mapping
5006 * the page into KVM and using bzero to clear its contents. This
5007 * is intended to be called from the vm_pagezero process only and
5011 pmap_zero_page_idle(vm_page_t m)
5013 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
5015 pagezero((void *)va);
5019 * pmap_copy_page copies the specified (machine independent)
5020 * page by mapping the page into virtual memory and using
5021 * bcopy to copy the page, one machine dependent page at a
5025 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
5027 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
5028 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
5030 pagecopy((void *)src, (void *)dst);
5033 int unmapped_buf_allowed = 1;
5036 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
5037 vm_offset_t b_offset, int xfersize)
5041 vm_paddr_t p_a, p_b;
5043 vm_offset_t a_pg_offset, b_pg_offset;
5048 * NB: The sequence of updating a page table followed by accesses
5049 * to the corresponding pages used in the !DMAP case is subject to
5050 * the situation described in the "AMD64 Architecture Programmer's
5051 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
5052 * Coherency Considerations". Therefore, issuing the INVLPG right
5053 * after modifying the PTE bits is crucial.
5056 while (xfersize > 0) {
5057 a_pg_offset = a_offset & PAGE_MASK;
5058 m_a = ma[a_offset >> PAGE_SHIFT];
5059 p_a = m_a->phys_addr;
5060 b_pg_offset = b_offset & PAGE_MASK;
5061 m_b = mb[b_offset >> PAGE_SHIFT];
5062 p_b = m_b->phys_addr;
5063 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
5064 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
5065 if (__predict_false(p_a < DMAP_MIN_ADDRESS ||
5066 p_a > DMAP_MIN_ADDRESS + dmaplimit)) {
5067 mtx_lock(&cpage_lock);
5070 pte = vtopte(cpage_a);
5071 *pte = p_a | X86_PG_A | X86_PG_V |
5072 pmap_cache_bits(kernel_pmap, m_a->md.pat_mode, 0);
5074 a_cp = (char *)cpage_a + a_pg_offset;
5076 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
5078 if (__predict_false(p_b < DMAP_MIN_ADDRESS ||
5079 p_b > DMAP_MIN_ADDRESS + dmaplimit)) {
5081 mtx_lock(&cpage_lock);
5085 pte = vtopte(cpage_b);
5086 *pte = p_b | X86_PG_A | X86_PG_M | X86_PG_RW |
5087 X86_PG_V | pmap_cache_bits(kernel_pmap,
5088 m_b->md.pat_mode, 0);
5090 b_cp = (char *)cpage_b + b_pg_offset;
5092 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
5094 bcopy(a_cp, b_cp, cnt);
5095 if (__predict_false(pinned)) {
5097 mtx_unlock(&cpage_lock);
5107 * Returns true if the pmap's pv is one of the first
5108 * 16 pvs linked to from this page. This count may
5109 * be changed upwards or downwards in the future; it
5110 * is only necessary that true be returned for a small
5111 * subset of pmaps for proper page aging.
5114 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
5116 struct md_page *pvh;
5117 struct rwlock *lock;
5122 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5123 ("pmap_page_exists_quick: page %p is not managed", m));
5125 rw_rlock(&pvh_global_lock);
5126 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5128 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5129 if (PV_PMAP(pv) == pmap) {
5137 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
5138 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5139 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5140 if (PV_PMAP(pv) == pmap) {
5150 rw_runlock(&pvh_global_lock);
5155 * pmap_page_wired_mappings:
5157 * Return the number of managed mappings to the given physical page
5161 pmap_page_wired_mappings(vm_page_t m)
5163 struct rwlock *lock;
5164 struct md_page *pvh;
5168 int count, md_gen, pvh_gen;
5170 if ((m->oflags & VPO_UNMANAGED) != 0)
5172 rw_rlock(&pvh_global_lock);
5173 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5177 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5179 if (!PMAP_TRYLOCK(pmap)) {
5180 md_gen = m->md.pv_gen;
5184 if (md_gen != m->md.pv_gen) {
5189 pte = pmap_pte(pmap, pv->pv_va);
5190 if ((*pte & PG_W) != 0)
5194 if ((m->flags & PG_FICTITIOUS) == 0) {
5195 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5196 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5198 if (!PMAP_TRYLOCK(pmap)) {
5199 md_gen = m->md.pv_gen;
5200 pvh_gen = pvh->pv_gen;
5204 if (md_gen != m->md.pv_gen ||
5205 pvh_gen != pvh->pv_gen) {
5210 pte = pmap_pde(pmap, pv->pv_va);
5211 if ((*pte & PG_W) != 0)
5217 rw_runlock(&pvh_global_lock);
5222 * Returns TRUE if the given page is mapped individually or as part of
5223 * a 2mpage. Otherwise, returns FALSE.
5226 pmap_page_is_mapped(vm_page_t m)
5228 struct rwlock *lock;
5231 if ((m->oflags & VPO_UNMANAGED) != 0)
5233 rw_rlock(&pvh_global_lock);
5234 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5236 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
5237 ((m->flags & PG_FICTITIOUS) == 0 &&
5238 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
5240 rw_runlock(&pvh_global_lock);
5245 * Destroy all managed, non-wired mappings in the given user-space
5246 * pmap. This pmap cannot be active on any processor besides the
5249 * This function cannot be applied to the kernel pmap. Moreover, it
5250 * is not intended for general use. It is only to be used during
5251 * process termination. Consequently, it can be implemented in ways
5252 * that make it faster than pmap_remove(). First, it can more quickly
5253 * destroy mappings by iterating over the pmap's collection of PV
5254 * entries, rather than searching the page table. Second, it doesn't
5255 * have to test and clear the page table entries atomically, because
5256 * no processor is currently accessing the user address space. In
5257 * particular, a page table entry's dirty bit won't change state once
5258 * this function starts.
5261 pmap_remove_pages(pmap_t pmap)
5264 pt_entry_t *pte, tpte;
5265 pt_entry_t PG_M, PG_RW, PG_V;
5266 struct spglist free;
5267 vm_page_t m, mpte, mt;
5269 struct md_page *pvh;
5270 struct pv_chunk *pc, *npc;
5271 struct rwlock *lock;
5273 uint64_t inuse, bitmask;
5274 int allfree, field, freed, idx;
5275 boolean_t superpage;
5279 * Assert that the given pmap is only active on the current
5280 * CPU. Unfortunately, we cannot block another CPU from
5281 * activating the pmap while this function is executing.
5283 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
5286 cpuset_t other_cpus;
5288 other_cpus = all_cpus;
5290 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
5291 CPU_AND(&other_cpus, &pmap->pm_active);
5293 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
5298 PG_M = pmap_modified_bit(pmap);
5299 PG_V = pmap_valid_bit(pmap);
5300 PG_RW = pmap_rw_bit(pmap);
5303 rw_rlock(&pvh_global_lock);
5305 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
5308 for (field = 0; field < _NPCM; field++) {
5309 inuse = ~pc->pc_map[field] & pc_freemask[field];
5310 while (inuse != 0) {
5312 bitmask = 1UL << bit;
5313 idx = field * 64 + bit;
5314 pv = &pc->pc_pventry[idx];
5317 pte = pmap_pdpe(pmap, pv->pv_va);
5319 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
5321 if ((tpte & (PG_PS | PG_V)) == PG_V) {
5324 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
5326 pte = &pte[pmap_pte_index(pv->pv_va)];
5330 * Keep track whether 'tpte' is a
5331 * superpage explicitly instead of
5332 * relying on PG_PS being set.
5334 * This is because PG_PS is numerically
5335 * identical to PG_PTE_PAT and thus a
5336 * regular page could be mistaken for
5342 if ((tpte & PG_V) == 0) {
5343 panic("bad pte va %lx pte %lx",
5348 * We cannot remove wired pages from a process' mapping at this time
5356 pa = tpte & PG_PS_FRAME;
5358 pa = tpte & PG_FRAME;
5360 m = PHYS_TO_VM_PAGE(pa);
5361 KASSERT(m->phys_addr == pa,
5362 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
5363 m, (uintmax_t)m->phys_addr,
5366 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
5367 m < &vm_page_array[vm_page_array_size],
5368 ("pmap_remove_pages: bad tpte %#jx",
5374 * Update the vm_page_t clean/reference bits.
5376 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5378 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5384 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
5387 pc->pc_map[field] |= bitmask;
5389 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5390 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
5391 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5393 if (TAILQ_EMPTY(&pvh->pv_list)) {
5394 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5395 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
5396 TAILQ_EMPTY(&mt->md.pv_list))
5397 vm_page_aflag_clear(mt, PGA_WRITEABLE);
5399 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
5401 pmap_remove_pt_page(pmap, mpte);
5402 pmap_resident_count_dec(pmap, 1);
5403 KASSERT(mpte->wire_count == NPTEPG,
5404 ("pmap_remove_pages: pte page wire count error"));
5405 mpte->wire_count = 0;
5406 pmap_add_delayed_free_list(mpte, &free, FALSE);
5407 atomic_subtract_int(&cnt.v_wire_count, 1);
5410 pmap_resident_count_dec(pmap, 1);
5411 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5413 if ((m->aflags & PGA_WRITEABLE) != 0 &&
5414 TAILQ_EMPTY(&m->md.pv_list) &&
5415 (m->flags & PG_FICTITIOUS) == 0) {
5416 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5417 if (TAILQ_EMPTY(&pvh->pv_list))
5418 vm_page_aflag_clear(m, PGA_WRITEABLE);
5421 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
5425 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
5426 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
5427 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
5429 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5435 pmap_invalidate_all(pmap);
5436 rw_runlock(&pvh_global_lock);
5438 pmap_free_zero_pages(&free);
5442 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
5444 struct rwlock *lock;
5446 struct md_page *pvh;
5447 pt_entry_t *pte, mask;
5448 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
5450 int md_gen, pvh_gen;
5454 rw_rlock(&pvh_global_lock);
5455 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5458 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5460 if (!PMAP_TRYLOCK(pmap)) {
5461 md_gen = m->md.pv_gen;
5465 if (md_gen != m->md.pv_gen) {
5470 pte = pmap_pte(pmap, pv->pv_va);
5473 PG_M = pmap_modified_bit(pmap);
5474 PG_RW = pmap_rw_bit(pmap);
5475 mask |= PG_RW | PG_M;
5478 PG_A = pmap_accessed_bit(pmap);
5479 PG_V = pmap_valid_bit(pmap);
5480 mask |= PG_V | PG_A;
5482 rv = (*pte & mask) == mask;
5487 if ((m->flags & PG_FICTITIOUS) == 0) {
5488 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5489 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5491 if (!PMAP_TRYLOCK(pmap)) {
5492 md_gen = m->md.pv_gen;
5493 pvh_gen = pvh->pv_gen;
5497 if (md_gen != m->md.pv_gen ||
5498 pvh_gen != pvh->pv_gen) {
5503 pte = pmap_pde(pmap, pv->pv_va);
5506 PG_M = pmap_modified_bit(pmap);
5507 PG_RW = pmap_rw_bit(pmap);
5508 mask |= PG_RW | PG_M;
5511 PG_A = pmap_accessed_bit(pmap);
5512 PG_V = pmap_valid_bit(pmap);
5513 mask |= PG_V | PG_A;
5515 rv = (*pte & mask) == mask;
5523 rw_runlock(&pvh_global_lock);
5530 * Return whether or not the specified physical page was modified
5531 * in any physical maps.
5534 pmap_is_modified(vm_page_t m)
5537 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5538 ("pmap_is_modified: page %p is not managed", m));
5541 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5542 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
5543 * is clear, no PTEs can have PG_M set.
5545 VM_OBJECT_ASSERT_WLOCKED(m->object);
5546 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5548 return (pmap_page_test_mappings(m, FALSE, TRUE));
5552 * pmap_is_prefaultable:
5554 * Return whether or not the specified virtual address is eligible
5558 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
5561 pt_entry_t *pte, PG_V;
5564 PG_V = pmap_valid_bit(pmap);
5567 pde = pmap_pde(pmap, addr);
5568 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
5569 pte = pmap_pde_to_pte(pde, addr);
5570 rv = (*pte & PG_V) == 0;
5577 * pmap_is_referenced:
5579 * Return whether or not the specified physical page was referenced
5580 * in any physical maps.
5583 pmap_is_referenced(vm_page_t m)
5586 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5587 ("pmap_is_referenced: page %p is not managed", m));
5588 return (pmap_page_test_mappings(m, TRUE, FALSE));
5592 * Clear the write and modified bits in each of the given page's mappings.
5595 pmap_remove_write(vm_page_t m)
5597 struct md_page *pvh;
5599 struct rwlock *lock;
5600 pv_entry_t next_pv, pv;
5602 pt_entry_t oldpte, *pte, PG_M, PG_RW;
5604 int pvh_gen, md_gen;
5606 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5607 ("pmap_remove_write: page %p is not managed", m));
5610 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
5611 * set by another thread while the object is locked. Thus,
5612 * if PGA_WRITEABLE is clear, no page table entries need updating.
5614 VM_OBJECT_ASSERT_WLOCKED(m->object);
5615 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
5617 rw_rlock(&pvh_global_lock);
5618 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5619 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5622 if ((m->flags & PG_FICTITIOUS) != 0)
5623 goto small_mappings;
5624 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5626 if (!PMAP_TRYLOCK(pmap)) {
5627 pvh_gen = pvh->pv_gen;
5631 if (pvh_gen != pvh->pv_gen) {
5637 PG_RW = pmap_rw_bit(pmap);
5639 pde = pmap_pde(pmap, va);
5640 if ((*pde & PG_RW) != 0)
5641 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5642 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5643 ("inconsistent pv lock %p %p for page %p",
5644 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5648 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5650 if (!PMAP_TRYLOCK(pmap)) {
5651 pvh_gen = pvh->pv_gen;
5652 md_gen = m->md.pv_gen;
5656 if (pvh_gen != pvh->pv_gen ||
5657 md_gen != m->md.pv_gen) {
5663 PG_M = pmap_modified_bit(pmap);
5664 PG_RW = pmap_rw_bit(pmap);
5665 pde = pmap_pde(pmap, pv->pv_va);
5666 KASSERT((*pde & PG_PS) == 0,
5667 ("pmap_remove_write: found a 2mpage in page %p's pv list",
5669 pte = pmap_pde_to_pte(pde, pv->pv_va);
5672 if (oldpte & PG_RW) {
5673 if (!atomic_cmpset_long(pte, oldpte, oldpte &
5676 if ((oldpte & PG_M) != 0)
5678 pmap_invalidate_page(pmap, pv->pv_va);
5683 vm_page_aflag_clear(m, PGA_WRITEABLE);
5684 rw_runlock(&pvh_global_lock);
5687 static __inline boolean_t
5688 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
5691 if (!pmap_emulate_ad_bits(pmap))
5694 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
5697 * RWX = 010 or 110 will cause an unconditional EPT misconfiguration
5698 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
5699 * if the EPT_PG_WRITE bit is set.
5701 if ((pte & EPT_PG_WRITE) != 0)
5705 * RWX = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
5707 if ((pte & EPT_PG_EXECUTE) == 0 ||
5708 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
5714 #define PMAP_TS_REFERENCED_MAX 5
5717 * pmap_ts_referenced:
5719 * Return a count of reference bits for a page, clearing those bits.
5720 * It is not necessary for every reference bit to be cleared, but it
5721 * is necessary that 0 only be returned when there are truly no
5722 * reference bits set.
5724 * XXX: The exact number of bits to check and clear is a matter that
5725 * should be tested and standardized at some point in the future for
5726 * optimal aging of shared pages.
5729 pmap_ts_referenced(vm_page_t m)
5731 struct md_page *pvh;
5734 struct rwlock *lock;
5735 pd_entry_t oldpde, *pde;
5736 pt_entry_t *pte, PG_A;
5739 int cleared, md_gen, not_cleared, pvh_gen;
5740 struct spglist free;
5743 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5744 ("pmap_ts_referenced: page %p is not managed", m));
5747 pa = VM_PAGE_TO_PHYS(m);
5748 lock = PHYS_TO_PV_LIST_LOCK(pa);
5749 pvh = pa_to_pvh(pa);
5750 rw_rlock(&pvh_global_lock);
5754 if ((m->flags & PG_FICTITIOUS) != 0 ||
5755 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5756 goto small_mappings;
5762 if (!PMAP_TRYLOCK(pmap)) {
5763 pvh_gen = pvh->pv_gen;
5767 if (pvh_gen != pvh->pv_gen) {
5772 PG_A = pmap_accessed_bit(pmap);
5774 pde = pmap_pde(pmap, pv->pv_va);
5776 if ((*pde & PG_A) != 0) {
5778 * Since this reference bit is shared by 512 4KB
5779 * pages, it should not be cleared every time it is
5780 * tested. Apply a simple "hash" function on the
5781 * physical page number, the virtual superpage number,
5782 * and the pmap address to select one 4KB page out of
5783 * the 512 on which testing the reference bit will
5784 * result in clearing that reference bit. This
5785 * function is designed to avoid the selection of the
5786 * same 4KB page for every 2MB page mapping.
5788 * On demotion, a mapping that hasn't been referenced
5789 * is simply destroyed. To avoid the possibility of a
5790 * subsequent page fault on a demoted wired mapping,
5791 * always leave its reference bit set. Moreover,
5792 * since the superpage is wired, the current state of
5793 * its reference bit won't affect page replacement.
5795 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5796 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5797 (*pde & PG_W) == 0) {
5798 if (safe_to_clear_referenced(pmap, oldpde)) {
5799 atomic_clear_long(pde, PG_A);
5800 pmap_invalidate_page(pmap, pv->pv_va);
5802 } else if (pmap_demote_pde_locked(pmap, pde,
5803 pv->pv_va, &lock)) {
5805 * Remove the mapping to a single page
5806 * so that a subsequent access may
5807 * repromote. Since the underlying
5808 * page table page is fully populated,
5809 * this removal never frees a page
5813 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5815 pte = pmap_pde_to_pte(pde, va);
5816 pmap_remove_pte(pmap, pte, va, *pde,
5818 pmap_invalidate_page(pmap, va);
5824 * The superpage mapping was removed
5825 * entirely and therefore 'pv' is no
5833 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5834 ("inconsistent pv lock %p %p for page %p",
5835 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5840 /* Rotate the PV list if it has more than one entry. */
5841 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5842 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5843 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5846 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
5848 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5850 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5857 if (!PMAP_TRYLOCK(pmap)) {
5858 pvh_gen = pvh->pv_gen;
5859 md_gen = m->md.pv_gen;
5863 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5868 PG_A = pmap_accessed_bit(pmap);
5869 pde = pmap_pde(pmap, pv->pv_va);
5870 KASSERT((*pde & PG_PS) == 0,
5871 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
5873 pte = pmap_pde_to_pte(pde, pv->pv_va);
5874 if ((*pte & PG_A) != 0) {
5875 if (safe_to_clear_referenced(pmap, *pte)) {
5876 atomic_clear_long(pte, PG_A);
5877 pmap_invalidate_page(pmap, pv->pv_va);
5879 } else if ((*pte & PG_W) == 0) {
5881 * Wired pages cannot be paged out so
5882 * doing accessed bit emulation for
5883 * them is wasted effort. We do the
5884 * hard work for unwired pages only.
5886 pmap_remove_pte(pmap, pte, pv->pv_va,
5887 *pde, &free, &lock);
5888 pmap_invalidate_page(pmap, pv->pv_va);
5893 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
5894 ("inconsistent pv lock %p %p for page %p",
5895 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
5900 /* Rotate the PV list if it has more than one entry. */
5901 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
5902 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5903 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5906 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
5907 not_cleared < PMAP_TS_REFERENCED_MAX);
5910 rw_runlock(&pvh_global_lock);
5911 pmap_free_zero_pages(&free);
5912 return (cleared + not_cleared);
5916 * Apply the given advice to the specified range of addresses within the
5917 * given pmap. Depending on the advice, clear the referenced and/or
5918 * modified flags in each mapping and set the mapped page's dirty field.
5921 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
5923 struct rwlock *lock;
5924 pml4_entry_t *pml4e;
5926 pd_entry_t oldpde, *pde;
5927 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
5928 vm_offset_t va_next;
5930 boolean_t anychanged, pv_lists_locked;
5932 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5936 * A/D bit emulation requires an alternate code path when clearing
5937 * the modified and accessed bits below. Since this function is
5938 * advisory in nature we skip it entirely for pmaps that require
5939 * A/D bit emulation.
5941 if (pmap_emulate_ad_bits(pmap))
5944 PG_A = pmap_accessed_bit(pmap);
5945 PG_G = pmap_global_bit(pmap);
5946 PG_M = pmap_modified_bit(pmap);
5947 PG_V = pmap_valid_bit(pmap);
5948 PG_RW = pmap_rw_bit(pmap);
5950 pv_lists_locked = FALSE;
5954 for (; sva < eva; sva = va_next) {
5955 pml4e = pmap_pml4e(pmap, sva);
5956 if ((*pml4e & PG_V) == 0) {
5957 va_next = (sva + NBPML4) & ~PML4MASK;
5962 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5963 if ((*pdpe & PG_V) == 0) {
5964 va_next = (sva + NBPDP) & ~PDPMASK;
5969 va_next = (sva + NBPDR) & ~PDRMASK;
5972 pde = pmap_pdpe_to_pde(pdpe, sva);
5974 if ((oldpde & PG_V) == 0)
5976 else if ((oldpde & PG_PS) != 0) {
5977 if ((oldpde & PG_MANAGED) == 0)
5979 if (!pv_lists_locked) {
5980 pv_lists_locked = TRUE;
5981 if (!rw_try_rlock(&pvh_global_lock)) {
5983 pmap_invalidate_all(pmap);
5985 rw_rlock(&pvh_global_lock);
5990 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
5995 * The large page mapping was destroyed.
6001 * Unless the page mappings are wired, remove the
6002 * mapping to a single page so that a subsequent
6003 * access may repromote. Since the underlying page
6004 * table page is fully populated, this removal never
6005 * frees a page table page.
6007 if ((oldpde & PG_W) == 0) {
6008 pte = pmap_pde_to_pte(pde, sva);
6009 KASSERT((*pte & PG_V) != 0,
6010 ("pmap_advise: invalid PTE"));
6011 pmap_remove_pte(pmap, pte, sva, *pde, NULL,
6020 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6022 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
6025 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6026 if (advice == MADV_DONTNEED) {
6028 * Future calls to pmap_is_modified()
6029 * can be avoided by making the page
6032 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6035 atomic_clear_long(pte, PG_M | PG_A);
6036 } else if ((*pte & PG_A) != 0)
6037 atomic_clear_long(pte, PG_A);
6040 if ((*pte & PG_G) != 0)
6041 pmap_invalidate_page(pmap, sva);
6047 pmap_invalidate_all(pmap);
6048 if (pv_lists_locked)
6049 rw_runlock(&pvh_global_lock);
6054 * Clear the modify bits on the specified physical page.
6057 pmap_clear_modify(vm_page_t m)
6059 struct md_page *pvh;
6061 pv_entry_t next_pv, pv;
6062 pd_entry_t oldpde, *pde;
6063 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
6064 struct rwlock *lock;
6066 int md_gen, pvh_gen;
6068 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6069 ("pmap_clear_modify: page %p is not managed", m));
6070 VM_OBJECT_ASSERT_WLOCKED(m->object);
6071 KASSERT(!vm_page_xbusied(m),
6072 ("pmap_clear_modify: page %p is exclusive busied", m));
6075 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
6076 * If the object containing the page is locked and the page is not
6077 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
6079 if ((m->aflags & PGA_WRITEABLE) == 0)
6081 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6082 rw_rlock(&pvh_global_lock);
6083 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6086 if ((m->flags & PG_FICTITIOUS) != 0)
6087 goto small_mappings;
6088 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
6090 if (!PMAP_TRYLOCK(pmap)) {
6091 pvh_gen = pvh->pv_gen;
6095 if (pvh_gen != pvh->pv_gen) {
6100 PG_M = pmap_modified_bit(pmap);
6101 PG_V = pmap_valid_bit(pmap);
6102 PG_RW = pmap_rw_bit(pmap);
6104 pde = pmap_pde(pmap, va);
6106 if ((oldpde & PG_RW) != 0) {
6107 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
6108 if ((oldpde & PG_W) == 0) {
6110 * Write protect the mapping to a
6111 * single page so that a subsequent
6112 * write access may repromote.
6114 va += VM_PAGE_TO_PHYS(m) - (oldpde &
6116 pte = pmap_pde_to_pte(pde, va);
6118 if ((oldpte & PG_V) != 0) {
6119 while (!atomic_cmpset_long(pte,
6121 oldpte & ~(PG_M | PG_RW)))
6124 pmap_invalidate_page(pmap, va);
6132 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6134 if (!PMAP_TRYLOCK(pmap)) {
6135 md_gen = m->md.pv_gen;
6136 pvh_gen = pvh->pv_gen;
6140 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6145 PG_M = pmap_modified_bit(pmap);
6146 PG_RW = pmap_rw_bit(pmap);
6147 pde = pmap_pde(pmap, pv->pv_va);
6148 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
6149 " a 2mpage in page %p's pv list", m));
6150 pte = pmap_pde_to_pte(pde, pv->pv_va);
6151 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6152 atomic_clear_long(pte, PG_M);
6153 pmap_invalidate_page(pmap, pv->pv_va);
6158 rw_runlock(&pvh_global_lock);
6162 * Miscellaneous support routines follow
6165 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
6166 static __inline void
6167 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
6172 * The cache mode bits are all in the low 32-bits of the
6173 * PTE, so we can just spin on updating the low 32-bits.
6176 opte = *(u_int *)pte;
6177 npte = opte & ~mask;
6179 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
6182 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
6183 static __inline void
6184 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
6189 * The cache mode bits are all in the low 32-bits of the
6190 * PDE, so we can just spin on updating the low 32-bits.
6193 opde = *(u_int *)pde;
6194 npde = opde & ~mask;
6196 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
6200 * Map a set of physical memory pages into the kernel virtual
6201 * address space. Return a pointer to where it is mapped. This
6202 * routine is intended to be used for mapping device memory,
6206 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
6208 vm_offset_t va, offset;
6212 * If the specified range of physical addresses fits within the direct
6213 * map window, use the direct map.
6215 if (pa < dmaplimit && pa + size < dmaplimit) {
6216 va = PHYS_TO_DMAP(pa);
6217 if (!pmap_change_attr(va, size, mode))
6218 return ((void *)va);
6220 offset = pa & PAGE_MASK;
6221 size = round_page(offset + size);
6222 va = kva_alloc(size);
6224 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
6225 pa = trunc_page(pa);
6226 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
6227 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
6228 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
6229 pmap_invalidate_cache_range(va, va + tmpsize, FALSE);
6230 return ((void *)(va + offset));
6234 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
6237 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
6241 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
6244 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
6248 pmap_unmapdev(vm_offset_t va, vm_size_t size)
6250 vm_offset_t base, offset;
6252 /* If we gave a direct map region in pmap_mapdev, do nothing */
6253 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
6255 base = trunc_page(va);
6256 offset = va & PAGE_MASK;
6257 size = round_page(offset + size);
6258 kva_free(base, size);
6262 * Tries to demote a 1GB page mapping.
6265 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
6267 pdp_entry_t newpdpe, oldpdpe;
6268 pd_entry_t *firstpde, newpde, *pde;
6269 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6273 PG_A = pmap_accessed_bit(pmap);
6274 PG_M = pmap_modified_bit(pmap);
6275 PG_V = pmap_valid_bit(pmap);
6276 PG_RW = pmap_rw_bit(pmap);
6278 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6280 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
6281 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
6282 if ((mpde = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
6283 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
6284 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
6285 " in pmap %p", va, pmap);
6288 mpdepa = VM_PAGE_TO_PHYS(mpde);
6289 firstpde = (pd_entry_t *)PHYS_TO_DMAP(mpdepa);
6290 newpdpe = mpdepa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
6291 KASSERT((oldpdpe & PG_A) != 0,
6292 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
6293 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
6294 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
6298 * Initialize the page directory page.
6300 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
6306 * Demote the mapping.
6311 * Invalidate a stale recursive mapping of the page directory page.
6313 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
6315 pmap_pdpe_demotions++;
6316 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
6317 " in pmap %p", va, pmap);
6322 * Sets the memory attribute for the specified page.
6325 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
6328 m->md.pat_mode = ma;
6331 * If "m" is a normal page, update its direct mapping. This update
6332 * can be relied upon to perform any cache operations that are
6333 * required for data coherence.
6335 if ((m->flags & PG_FICTITIOUS) == 0 &&
6336 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
6338 panic("memory attribute change on the direct map failed");
6342 * Changes the specified virtual address range's memory type to that given by
6343 * the parameter "mode". The specified virtual address range must be
6344 * completely contained within either the direct map or the kernel map. If
6345 * the virtual address range is contained within the kernel map, then the
6346 * memory type for each of the corresponding ranges of the direct map is also
6347 * changed. (The corresponding ranges of the direct map are those ranges that
6348 * map the same physical pages as the specified virtual address range.) These
6349 * changes to the direct map are necessary because Intel describes the
6350 * behavior of their processors as "undefined" if two or more mappings to the
6351 * same physical page have different memory types.
6353 * Returns zero if the change completed successfully, and either EINVAL or
6354 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
6355 * of the virtual address range was not mapped, and ENOMEM is returned if
6356 * there was insufficient memory available to complete the change. In the
6357 * latter case, the memory type may have been changed on some part of the
6358 * virtual address range or the direct map.
6361 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
6365 PMAP_LOCK(kernel_pmap);
6366 error = pmap_change_attr_locked(va, size, mode);
6367 PMAP_UNLOCK(kernel_pmap);
6372 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
6374 vm_offset_t base, offset, tmpva;
6375 vm_paddr_t pa_start, pa_end;
6379 int cache_bits_pte, cache_bits_pde, error;
6382 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
6383 base = trunc_page(va);
6384 offset = va & PAGE_MASK;
6385 size = round_page(offset + size);
6388 * Only supported on kernel virtual addresses, including the direct
6389 * map but excluding the recursive map.
6391 if (base < DMAP_MIN_ADDRESS)
6394 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
6395 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
6399 * Pages that aren't mapped aren't supported. Also break down 2MB pages
6400 * into 4KB pages if required.
6402 for (tmpva = base; tmpva < base + size; ) {
6403 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6406 if (*pdpe & PG_PS) {
6408 * If the current 1GB page already has the required
6409 * memory type, then we need not demote this page. Just
6410 * increment tmpva to the next 1GB page frame.
6412 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
6413 tmpva = trunc_1gpage(tmpva) + NBPDP;
6418 * If the current offset aligns with a 1GB page frame
6419 * and there is at least 1GB left within the range, then
6420 * we need not break down this page into 2MB pages.
6422 if ((tmpva & PDPMASK) == 0 &&
6423 tmpva + PDPMASK < base + size) {
6427 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
6430 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6435 * If the current 2MB page already has the required
6436 * memory type, then we need not demote this page. Just
6437 * increment tmpva to the next 2MB page frame.
6439 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
6440 tmpva = trunc_2mpage(tmpva) + NBPDR;
6445 * If the current offset aligns with a 2MB page frame
6446 * and there is at least 2MB left within the range, then
6447 * we need not break down this page into 4KB pages.
6449 if ((tmpva & PDRMASK) == 0 &&
6450 tmpva + PDRMASK < base + size) {
6454 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
6457 pte = pmap_pde_to_pte(pde, tmpva);
6465 * Ok, all the pages exist, so run through them updating their
6466 * cache mode if required.
6468 pa_start = pa_end = 0;
6469 for (tmpva = base; tmpva < base + size; ) {
6470 pdpe = pmap_pdpe(kernel_pmap, tmpva);
6471 if (*pdpe & PG_PS) {
6472 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
6473 pmap_pde_attr(pdpe, cache_bits_pde,
6477 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6478 if (pa_start == pa_end) {
6479 /* Start physical address run. */
6480 pa_start = *pdpe & PG_PS_FRAME;
6481 pa_end = pa_start + NBPDP;
6482 } else if (pa_end == (*pdpe & PG_PS_FRAME))
6485 /* Run ended, update direct map. */
6486 error = pmap_change_attr_locked(
6487 PHYS_TO_DMAP(pa_start),
6488 pa_end - pa_start, mode);
6491 /* Start physical address run. */
6492 pa_start = *pdpe & PG_PS_FRAME;
6493 pa_end = pa_start + NBPDP;
6496 tmpva = trunc_1gpage(tmpva) + NBPDP;
6499 pde = pmap_pdpe_to_pde(pdpe, tmpva);
6501 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
6502 pmap_pde_attr(pde, cache_bits_pde,
6506 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6507 if (pa_start == pa_end) {
6508 /* Start physical address run. */
6509 pa_start = *pde & PG_PS_FRAME;
6510 pa_end = pa_start + NBPDR;
6511 } else if (pa_end == (*pde & PG_PS_FRAME))
6514 /* Run ended, update direct map. */
6515 error = pmap_change_attr_locked(
6516 PHYS_TO_DMAP(pa_start),
6517 pa_end - pa_start, mode);
6520 /* Start physical address run. */
6521 pa_start = *pde & PG_PS_FRAME;
6522 pa_end = pa_start + NBPDR;
6525 tmpva = trunc_2mpage(tmpva) + NBPDR;
6527 pte = pmap_pde_to_pte(pde, tmpva);
6528 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
6529 pmap_pte_attr(pte, cache_bits_pte,
6533 if (tmpva >= VM_MIN_KERNEL_ADDRESS) {
6534 if (pa_start == pa_end) {
6535 /* Start physical address run. */
6536 pa_start = *pte & PG_FRAME;
6537 pa_end = pa_start + PAGE_SIZE;
6538 } else if (pa_end == (*pte & PG_FRAME))
6539 pa_end += PAGE_SIZE;
6541 /* Run ended, update direct map. */
6542 error = pmap_change_attr_locked(
6543 PHYS_TO_DMAP(pa_start),
6544 pa_end - pa_start, mode);
6547 /* Start physical address run. */
6548 pa_start = *pte & PG_FRAME;
6549 pa_end = pa_start + PAGE_SIZE;
6555 if (error == 0 && pa_start != pa_end)
6556 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
6557 pa_end - pa_start, mode);
6560 * Flush CPU caches if required to make sure any data isn't cached that
6561 * shouldn't be, etc.
6564 pmap_invalidate_range(kernel_pmap, base, tmpva);
6565 pmap_invalidate_cache_range(base, tmpva, FALSE);
6571 * Demotes any mapping within the direct map region that covers more than the
6572 * specified range of physical addresses. This range's size must be a power
6573 * of two and its starting address must be a multiple of its size. Since the
6574 * demotion does not change any attributes of the mapping, a TLB invalidation
6575 * is not mandatory. The caller may, however, request a TLB invalidation.
6578 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
6587 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
6588 KASSERT((base & (len - 1)) == 0,
6589 ("pmap_demote_DMAP: base is not a multiple of len"));
6590 if (len < NBPDP && base < dmaplimit) {
6591 va = PHYS_TO_DMAP(base);
6593 PMAP_LOCK(kernel_pmap);
6594 pdpe = pmap_pdpe(kernel_pmap, va);
6595 if ((*pdpe & X86_PG_V) == 0)
6596 panic("pmap_demote_DMAP: invalid PDPE");
6597 if ((*pdpe & PG_PS) != 0) {
6598 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
6599 panic("pmap_demote_DMAP: PDPE failed");
6603 pde = pmap_pdpe_to_pde(pdpe, va);
6604 if ((*pde & X86_PG_V) == 0)
6605 panic("pmap_demote_DMAP: invalid PDE");
6606 if ((*pde & PG_PS) != 0) {
6607 if (!pmap_demote_pde(kernel_pmap, pde, va))
6608 panic("pmap_demote_DMAP: PDE failed");
6612 if (changed && invalidate)
6613 pmap_invalidate_page(kernel_pmap, va);
6614 PMAP_UNLOCK(kernel_pmap);
6619 * perform the pmap work for mincore
6622 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
6625 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
6629 PG_A = pmap_accessed_bit(pmap);
6630 PG_M = pmap_modified_bit(pmap);
6631 PG_V = pmap_valid_bit(pmap);
6632 PG_RW = pmap_rw_bit(pmap);
6636 pdep = pmap_pde(pmap, addr);
6637 if (pdep != NULL && (*pdep & PG_V)) {
6638 if (*pdep & PG_PS) {
6640 /* Compute the physical address of the 4KB page. */
6641 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
6643 val = MINCORE_SUPER;
6645 pte = *pmap_pde_to_pte(pdep, addr);
6646 pa = pte & PG_FRAME;
6654 if ((pte & PG_V) != 0) {
6655 val |= MINCORE_INCORE;
6656 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6657 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
6658 if ((pte & PG_A) != 0)
6659 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
6661 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
6662 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
6663 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
6664 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
6665 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
6668 PA_UNLOCK_COND(*locked_pa);
6674 pmap_activate(struct thread *td)
6676 pmap_t pmap, oldpmap;
6680 pmap = vmspace_pmap(td->td_proc->p_vmspace);
6681 oldpmap = PCPU_GET(curpmap);
6682 cpuid = PCPU_GET(cpuid);
6684 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
6685 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
6686 CPU_SET_ATOMIC(cpuid, &pmap->pm_save);
6688 CPU_CLR(cpuid, &oldpmap->pm_active);
6689 CPU_SET(cpuid, &pmap->pm_active);
6690 CPU_SET(cpuid, &pmap->pm_save);
6692 td->td_pcb->pcb_cr3 = pmap->pm_cr3;
6693 load_cr3(pmap->pm_cr3);
6694 PCPU_SET(curpmap, pmap);
6699 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
6704 * Increase the starting virtual address of the given mapping if a
6705 * different alignment might result in more superpage mappings.
6708 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
6709 vm_offset_t *addr, vm_size_t size)
6711 vm_offset_t superpage_offset;
6715 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
6716 offset += ptoa(object->pg_color);
6717 superpage_offset = offset & PDRMASK;
6718 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
6719 (*addr & PDRMASK) == superpage_offset)
6721 if ((*addr & PDRMASK) < superpage_offset)
6722 *addr = (*addr & ~PDRMASK) + superpage_offset;
6724 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
6728 static unsigned long num_dirty_emulations;
6729 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
6730 &num_dirty_emulations, 0, NULL);
6732 static unsigned long num_accessed_emulations;
6733 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
6734 &num_accessed_emulations, 0, NULL);
6736 static unsigned long num_superpage_accessed_emulations;
6737 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
6738 &num_superpage_accessed_emulations, 0, NULL);
6740 static unsigned long ad_emulation_superpage_promotions;
6741 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
6742 &ad_emulation_superpage_promotions, 0, NULL);
6743 #endif /* INVARIANTS */
6746 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
6749 struct rwlock *lock;
6752 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
6753 boolean_t pv_lists_locked;
6755 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
6756 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
6758 if (!pmap_emulate_ad_bits(pmap))
6761 PG_A = pmap_accessed_bit(pmap);
6762 PG_M = pmap_modified_bit(pmap);
6763 PG_V = pmap_valid_bit(pmap);
6764 PG_RW = pmap_rw_bit(pmap);
6768 pv_lists_locked = FALSE;
6772 pde = pmap_pde(pmap, va);
6773 if (pde == NULL || (*pde & PG_V) == 0)
6776 if ((*pde & PG_PS) != 0) {
6777 if (ftype == VM_PROT_READ) {
6779 atomic_add_long(&num_superpage_accessed_emulations, 1);
6787 pte = pmap_pde_to_pte(pde, va);
6788 if ((*pte & PG_V) == 0)
6791 if (ftype == VM_PROT_WRITE) {
6792 if ((*pte & PG_RW) == 0)
6795 * Set the modified and accessed bits simultaneously.
6797 * Intel EPT PTEs that do software emulation of A/D bits map
6798 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
6799 * An EPT misconfiguration is triggered if the PTE is writable
6800 * but not readable (WR=10). This is avoided by setting PG_A
6801 * and PG_M simultaneously.
6803 *pte |= PG_M | PG_A;
6808 /* try to promote the mapping */
6809 if (va < VM_MAXUSER_ADDRESS)
6810 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6814 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
6816 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
6817 pmap_ps_enabled(pmap) &&
6818 (m->flags & PG_FICTITIOUS) == 0 &&
6819 vm_reserv_level_iffullpop(m) == 0) {
6820 if (!pv_lists_locked) {
6821 pv_lists_locked = TRUE;
6822 if (!rw_try_rlock(&pvh_global_lock)) {
6824 rw_rlock(&pvh_global_lock);
6828 pmap_promote_pde(pmap, pde, va, &lock);
6830 atomic_add_long(&ad_emulation_superpage_promotions, 1);
6834 if (ftype == VM_PROT_WRITE)
6835 atomic_add_long(&num_dirty_emulations, 1);
6837 atomic_add_long(&num_accessed_emulations, 1);
6839 rv = 0; /* success */
6843 if (pv_lists_locked)
6844 rw_runlock(&pvh_global_lock);
6850 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
6855 pt_entry_t *pte, PG_V;
6859 PG_V = pmap_valid_bit(pmap);
6862 pml4 = pmap_pml4e(pmap, va);
6864 if ((*pml4 & PG_V) == 0)
6867 pdp = pmap_pml4e_to_pdpe(pml4, va);
6869 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
6872 pde = pmap_pdpe_to_pde(pdp, va);
6874 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
6877 pte = pmap_pde_to_pte(pde, va);
6885 #include "opt_ddb.h"
6887 #include <ddb/ddb.h>
6889 DB_SHOW_COMMAND(pte, pmap_print_pte)
6895 pt_entry_t *pte, PG_V;
6899 va = (vm_offset_t)addr;
6900 pmap = PCPU_GET(curpmap); /* XXX */
6902 db_printf("show pte addr\n");
6905 PG_V = pmap_valid_bit(pmap);
6906 pml4 = pmap_pml4e(pmap, va);
6907 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
6908 if ((*pml4 & PG_V) == 0) {
6912 pdp = pmap_pml4e_to_pdpe(pml4, va);
6913 db_printf(" pdpe %#016lx", *pdp);
6914 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
6918 pde = pmap_pdpe_to_pde(pdp, va);
6919 db_printf(" pde %#016lx", *pde);
6920 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
6924 pte = pmap_pde_to_pte(pde, va);
6925 db_printf(" pte %#016lx\n", *pte);
6928 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
6933 a = (vm_paddr_t)addr;
6934 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
6936 db_printf("show phys2dmap addr\n");