2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_APICVAR_H_
30 #define _MACHINE_APICVAR_H_
32 #include <machine/segments.h>
35 * Local && I/O APIC variable definitions.
39 * Layout of local APIC interrupt vectors:
41 * 0xff (255) +-------------+
42 * | | 15 (Spurious / IPIs / Local Interrupts)
43 * 0xf0 (240) +-------------+
44 * | | 14 (I/O Interrupts / Timer)
45 * 0xe0 (224) +-------------+
46 * | | 13 (I/O Interrupts)
47 * 0xd0 (208) +-------------+
48 * | | 12 (I/O Interrupts)
49 * 0xc0 (192) +-------------+
50 * | | 11 (I/O Interrupts)
51 * 0xb0 (176) +-------------+
52 * | | 10 (I/O Interrupts)
53 * 0xa0 (160) +-------------+
54 * | | 9 (I/O Interrupts)
55 * 0x90 (144) +-------------+
56 * | | 8 (I/O Interrupts / System Calls)
57 * 0x80 (128) +-------------+
58 * | | 7 (I/O Interrupts)
59 * 0x70 (112) +-------------+
60 * | | 6 (I/O Interrupts)
61 * 0x60 (96) +-------------+
62 * | | 5 (I/O Interrupts)
63 * 0x50 (80) +-------------+
64 * | | 4 (I/O Interrupts)
65 * 0x40 (64) +-------------+
66 * | | 3 (I/O Interrupts)
67 * 0x30 (48) +-------------+
68 * | | 2 (ATPIC Interrupts)
69 * 0x20 (32) +-------------+
70 * | | 1 (Exceptions, traps, faults, etc.)
71 * 0x10 (16) +-------------+
72 * | | 0 (Exceptions, traps, faults, etc.)
73 * 0x00 (0) +-------------+
75 * Note: 0x80 needs to be handled specially and not allocated to an
79 #define MAX_APIC_ID 0xfe
80 #define APIC_ID_ALL 0xff
82 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
83 #define APIC_IO_INTS (IDT_IO_INTS + 16)
84 #define APIC_NUM_IOINTS 191
86 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
87 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
90 ********************* !!! WARNING !!! ******************************
91 * Each local apic has an interrupt receive fifo that is two entries deep
92 * for each interrupt priority class (higher 4 bits of interrupt vector).
93 * Once the fifo is full the APIC can no longer receive interrupts for this
94 * class and sending IPIs from other CPUs will be blocked.
95 * To avoid deadlocks there should be no more than two IPI interrupts
96 * pending at the same time.
97 * Currently this is guaranteed by dividing the IPIs in two groups that have
98 * each at most one IPI interrupt pending. The first group is protected by the
99 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
100 * at a time) The second group uses a single interrupt and a bitmap to avoid
101 * redundant IPI interrupts.
104 /* Interrupts for local APIC LVT entries other than the timer. */
105 #define APIC_LOCAL_INTS 240
106 #define APIC_ERROR_INT APIC_LOCAL_INTS
107 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
108 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
110 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
111 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
112 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
113 #define IPI_INVLPG (APIC_IPI_INTS + 2)
114 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
115 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
116 /* Vector to handle bitmap based IPIs */
117 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6)
119 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
120 #define IPI_AST 0 /* Generate software trap. */
121 #define IPI_PREEMPT 1
122 #define IPI_HARDCLOCK 2
123 #define IPI_BITMAP_LAST IPI_HARDCLOCK
124 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
126 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
127 #define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */
128 #define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */
131 * The spurious interrupt can share the priority class with the IPIs since
132 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
134 #define APIC_SPURIOUS_INT 255
141 #define LVT_THERMAL 5
143 #define LVT_MAX LVT_CMCI
147 #define APIC_IPI_DEST_SELF -1
148 #define APIC_IPI_DEST_ALL -2
149 #define APIC_IPI_DEST_OTHERS -3
151 #define APIC_BUS_UNKNOWN -1
152 #define APIC_BUS_ISA 0
153 #define APIC_BUS_EISA 1
154 #define APIC_BUS_PCI 2
155 #define APIC_BUS_MAX APIC_BUS_PCI
158 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
159 * CPU's and I/O APIC's.
161 struct apic_enumerator {
162 const char *apic_name;
163 int (*apic_probe)(void);
164 int (*apic_probe_cpus)(void);
165 int (*apic_setup_local)(void);
166 int (*apic_setup_io)(void);
167 SLIST_ENTRY(apic_enumerator) apic_next;
171 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
172 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
173 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
174 IDTVEC(spuriousint), IDTVEC(timerint);
176 extern vm_paddr_t lapic_paddr;
177 extern int apic_cpuids[];
179 u_int apic_alloc_vector(u_int apic_id, u_int irq);
180 u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count,
182 void apic_disable_vector(u_int apic_id, u_int vector);
183 void apic_enable_vector(u_int apic_id, u_int vector);
184 void apic_free_vector(u_int apic_id, u_int vector, u_int irq);
185 u_int apic_idt_to_irq(u_int apic_id, u_int vector);
186 void apic_register_enumerator(struct apic_enumerator *enumerator);
187 u_int apic_cpuid(u_int apic_id);
188 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
189 int ioapic_disable_pin(void *cookie, u_int pin);
190 int ioapic_get_vector(void *cookie, u_int pin);
191 void ioapic_register(void *cookie);
192 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
193 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
194 int ioapic_set_extint(void *cookie, u_int pin);
195 int ioapic_set_nmi(void *cookie, u_int pin);
196 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
197 int ioapic_set_triggermode(void *cookie, u_int pin,
198 enum intr_trigger trigger);
199 int ioapic_set_smi(void *cookie, u_int pin);
200 void lapic_create(u_int apic_id, int boot_cpu);
201 void lapic_disable(void);
202 void lapic_disable_pmc(void);
203 void lapic_dump(const char *str);
204 void lapic_enable_cmc(void);
205 int lapic_enable_pmc(void);
206 void lapic_eoi(void);
208 void lapic_init(vm_paddr_t addr);
209 int lapic_intr_pending(u_int vector);
210 void lapic_ipi_raw(register_t icrlo, u_int dest);
211 void lapic_ipi_vectored(u_int vector, int dest);
212 int lapic_ipi_wait(int delay);
213 void lapic_handle_cmc(void);
214 void lapic_handle_error(void);
215 void lapic_handle_intr(int vector, struct trapframe *frame);
216 void lapic_handle_timer(struct trapframe *frame);
217 void lapic_reenable_pmc(void);
218 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
219 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
220 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
221 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
222 enum intr_polarity pol);
223 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
224 enum intr_trigger trigger);
225 void lapic_set_tpr(u_int vector);
226 void lapic_setup(int boot);
229 #endif /* _MACHINE_APICVAR_H_ */