2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
39 #ifndef _MACHINE_CPUFUNC_H_
40 #define _MACHINE_CPUFUNC_H_
43 #error this file needs sys/cdefs.h as a prerequisite
46 struct region_descriptor;
48 #define readb(va) (*(volatile uint8_t *) (va))
49 #define readw(va) (*(volatile uint16_t *) (va))
50 #define readl(va) (*(volatile uint32_t *) (va))
51 #define readq(va) (*(volatile uint64_t *) (va))
53 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
58 #if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
63 __asm __volatile("int $3");
71 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
75 static __inline u_long
80 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
89 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
93 static __inline u_long
98 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
106 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
113 __asm __volatile("clts");
119 __asm __volatile("cli" : : : "memory");
123 do_cpuid(u_int ax, u_int *p)
125 __asm __volatile("cpuid"
126 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
131 cpuid_count(u_int ax, u_int cx, u_int *p)
133 __asm __volatile("cpuid"
134 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
135 : "0" (ax), "c" (cx));
141 __asm __volatile("sti");
146 #define HAVE_INLINE_FFS
147 #define ffs(x) __builtin_ffs(x)
149 #define HAVE_INLINE_FFSL
154 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
157 #define HAVE_INLINE_FLS
162 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
165 #define HAVE_INLINE_FLSL
170 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
178 __asm __volatile("hlt");
181 static __inline u_char
186 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
190 static __inline u_int
195 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
200 insb(u_int port, void *addr, size_t count)
202 __asm __volatile("cld; rep; insb"
203 : "+D" (addr), "+c" (count)
209 insw(u_int port, void *addr, size_t count)
211 __asm __volatile("cld; rep; insw"
212 : "+D" (addr), "+c" (count)
218 insl(u_int port, void *addr, size_t count)
220 __asm __volatile("cld; rep; insl"
221 : "+D" (addr), "+c" (count)
229 __asm __volatile("invd");
232 static __inline u_short
237 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
242 outb(u_int port, u_char data)
244 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
248 outl(u_int port, u_int data)
250 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
254 outsb(u_int port, const void *addr, size_t count)
256 __asm __volatile("cld; rep; outsb"
257 : "+S" (addr), "+c" (count)
262 outsw(u_int port, const void *addr, size_t count)
264 __asm __volatile("cld; rep; outsw"
265 : "+S" (addr), "+c" (count)
270 outsl(u_int port, const void *addr, size_t count)
272 __asm __volatile("cld; rep; outsl"
273 : "+S" (addr), "+c" (count)
278 outw(u_int port, u_short data)
280 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
283 static __inline u_long
288 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
296 __asm __volatile("lfence" : : : "memory");
303 __asm __volatile("mfence" : : : "memory");
309 __asm __volatile("pause");
312 static __inline u_long
317 __asm __volatile("pushfq; popq %0" : "=r" (rf));
321 static __inline uint64_t
326 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
327 return (low | ((uint64_t)high << 32));
330 static __inline uint64_t
335 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
336 return (low | ((uint64_t)high << 32));
339 static __inline uint64_t
344 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
345 return (low | ((uint64_t)high << 32));
348 static __inline uint32_t
353 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
360 __asm __volatile("wbinvd");
364 write_rflags(u_long rf)
366 __asm __volatile("pushq %0; popfq" : : "r" (rf));
370 wrmsr(u_int msr, uint64_t newval)
376 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
380 load_cr0(u_long data)
383 __asm __volatile("movq %0,%%cr0" : : "r" (data));
386 static __inline u_long
391 __asm __volatile("movq %%cr0,%0" : "=r" (data));
395 static __inline u_long
400 __asm __volatile("movq %%cr2,%0" : "=r" (data));
405 load_cr3(u_long data)
408 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
411 static __inline u_long
416 __asm __volatile("movq %%cr3,%0" : "=r" (data));
421 load_cr4(u_long data)
423 __asm __volatile("movq %0,%%cr4" : : "r" (data));
426 static __inline u_long
431 __asm __volatile("movq %%cr4,%0" : "=r" (data));
435 static __inline u_long
440 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
441 return (low | ((uint64_t)high << 32));
445 load_xcr(u_int reg, u_long val)
451 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
455 * Global TLB flush (except for thise for pages marked PG_G)
465 #define CR4_PGE 0x00000080 /* Page global enable */
469 * Perform the guaranteed invalidation of all TLB entries. This
470 * includes the global entries, and entries in all PCIDs, not only the
471 * current context. The function works both on non-PCID CPUs and CPUs
472 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
473 * Operations that Invalidate TLBs and Paging-Structure Caches.
476 invltlb_globpcid(void)
481 load_cr4(cr4 & ~CR4_PGE);
483 * Although preemption at this point could be detrimental to
484 * performance, it would not lead to an error. PG_G is simply
485 * ignored if CR4.PGE is clear. Moreover, in case this block
486 * is re-entered, the load_cr4() either above or below will
487 * modify CR4.PGE flushing the TLB.
489 load_cr4(cr4 | CR4_PGE);
493 * TLB flush for an individual page (even if it has PG_G).
494 * Only works on 486+ CPUs (i386 does not have PG_G).
500 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
503 #define INVPCID_ADDR 0
504 #define INVPCID_CTX 1
505 #define INVPCID_CTXGLOB 2
506 #define INVPCID_ALLCTX 3
508 struct invpcid_descr {
509 uint64_t pcid:12 __packed;
510 uint64_t pad:52 __packed;
515 invpcid(struct invpcid_descr *d, int type)
518 /* invpcid (%rdx),%rax */
519 __asm __volatile(".byte 0x66,0x0f,0x38,0x82,0x02"
520 : : "d" (d), "a" ((u_long)type) : "memory");
523 static __inline u_short
527 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
531 static __inline u_short
535 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
539 static __inline u_short
543 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
550 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
556 __asm __volatile("movw %0,%%es" : : "rm" (sel));
560 cpu_monitor(const void *addr, u_long extensions, u_int hints)
563 __asm __volatile("monitor"
564 : : "a" (addr), "c" (extensions), "d" (hints));
568 cpu_mwait(u_long extensions, u_int hints)
571 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
575 /* This is defined in <machine/specialreg.h> but is too painful to get to */
577 #define MSR_FSBASE 0xc0000100
582 /* Preserve the fsbase value across the selector load */
583 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
584 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
588 #define MSR_GSBASE 0xc0000101
594 * Preserve the gsbase value across the selector load.
595 * Note that we have to disable interrupts because the gsbase
596 * being trashed happens to be the kernel gsbase at the time.
598 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
599 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
602 /* Usable by userland */
606 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
612 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
617 lidt(struct region_descriptor *addr)
619 __asm __volatile("lidt (%0)" : : "r" (addr));
625 __asm __volatile("lldt %0" : : "r" (sel));
631 __asm __volatile("ltr %0" : : "r" (sel));
634 static __inline uint64_t
638 __asm __volatile("movq %%dr0,%0" : "=r" (data));
643 load_dr0(uint64_t dr0)
645 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
648 static __inline uint64_t
652 __asm __volatile("movq %%dr1,%0" : "=r" (data));
657 load_dr1(uint64_t dr1)
659 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
662 static __inline uint64_t
666 __asm __volatile("movq %%dr2,%0" : "=r" (data));
671 load_dr2(uint64_t dr2)
673 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
676 static __inline uint64_t
680 __asm __volatile("movq %%dr3,%0" : "=r" (data));
685 load_dr3(uint64_t dr3)
687 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
690 static __inline uint64_t
694 __asm __volatile("movq %%dr4,%0" : "=r" (data));
699 load_dr4(uint64_t dr4)
701 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
704 static __inline uint64_t
708 __asm __volatile("movq %%dr5,%0" : "=r" (data));
713 load_dr5(uint64_t dr5)
715 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
718 static __inline uint64_t
722 __asm __volatile("movq %%dr6,%0" : "=r" (data));
727 load_dr6(uint64_t dr6)
729 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
732 static __inline uint64_t
736 __asm __volatile("movq %%dr7,%0" : "=r" (data));
741 load_dr7(uint64_t dr7)
743 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
746 static __inline register_t
751 rflags = read_rflags();
757 intr_restore(register_t rflags)
759 write_rflags(rflags);
762 #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
764 int breakpoint(void);
765 u_int bsfl(u_int mask);
766 u_int bsrl(u_int mask);
767 void clflush(u_long addr);
769 void cpuid_count(u_int ax, u_int cx, u_int *p);
770 void disable_intr(void);
771 void do_cpuid(u_int ax, u_int *p);
772 void enable_intr(void);
774 void ia32_pause(void);
775 u_char inb(u_int port);
776 u_int inl(u_int port);
777 void insb(u_int port, void *addr, size_t count);
778 void insl(u_int port, void *addr, size_t count);
779 void insw(u_int port, void *addr, size_t count);
780 register_t intr_disable(void);
781 void intr_restore(register_t rf);
783 void invlpg(u_int addr);
785 u_short inw(u_int port);
786 void lidt(struct region_descriptor *addr);
787 void lldt(u_short sel);
788 void load_cr0(u_long cr0);
789 void load_cr3(u_long cr3);
790 void load_cr4(u_long cr4);
791 void load_dr0(uint64_t dr0);
792 void load_dr1(uint64_t dr1);
793 void load_dr2(uint64_t dr2);
794 void load_dr3(uint64_t dr3);
795 void load_dr4(uint64_t dr4);
796 void load_dr5(uint64_t dr5);
797 void load_dr6(uint64_t dr6);
798 void load_dr7(uint64_t dr7);
799 void load_fs(u_short sel);
800 void load_gs(u_short sel);
801 void ltr(u_short sel);
802 void outb(u_int port, u_char data);
803 void outl(u_int port, u_int data);
804 void outsb(u_int port, const void *addr, size_t count);
805 void outsl(u_int port, const void *addr, size_t count);
806 void outsw(u_int port, const void *addr, size_t count);
807 void outw(u_int port, u_short data);
812 uint64_t rdmsr(u_int msr);
813 uint64_t rdpmc(u_int pmc);
822 uint64_t rdtsc(void);
823 u_long read_rflags(void);
827 void write_rflags(u_int rf);
828 void wrmsr(u_int msr, uint64_t newval);
830 #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
832 void reset_dbregs(void);
835 int rdmsr_safe(u_int msr, uint64_t *val);
836 int wrmsr_safe(u_int msr, uint64_t newval);
839 #endif /* !_MACHINE_CPUFUNC_H_ */