2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
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17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
55 #define CR3_PCID_SAVE 0x8000000000000000
58 * Bits in PPro special registers
60 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
61 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
62 #define CR4_TSD 0x00000004 /* Time stamp disable */
63 #define CR4_DE 0x00000008 /* Debugging extensions */
64 #define CR4_PSE 0x00000010 /* Page size extensions */
65 #define CR4_PAE 0x00000020 /* Physical address extension */
66 #define CR4_MCE 0x00000040 /* Machine check enable */
67 #define CR4_PGE 0x00000080 /* Page global enable */
68 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
69 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
70 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
72 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */
73 #define CR4_PCIDE 0x00020000 /* Enable Context ID */
74 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
75 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
78 * Bits in AMD64 special registers. EFER is 64 bits wide.
80 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
81 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
82 #define EFER_LMA 0x000000400 /* Long mode active (R) */
83 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
86 * Intel Extended Features registers
88 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */
90 #define XFEATURE_ENABLED_X87 0x00000001
91 #define XFEATURE_ENABLED_SSE 0x00000002
92 #define XFEATURE_ENABLED_AVX 0x00000004
94 #define XFEATURE_AVX \
95 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
98 * CPUID instruction features register
100 #define CPUID_FPU 0x00000001
101 #define CPUID_VME 0x00000002
102 #define CPUID_DE 0x00000004
103 #define CPUID_PSE 0x00000008
104 #define CPUID_TSC 0x00000010
105 #define CPUID_MSR 0x00000020
106 #define CPUID_PAE 0x00000040
107 #define CPUID_MCE 0x00000080
108 #define CPUID_CX8 0x00000100
109 #define CPUID_APIC 0x00000200
110 #define CPUID_B10 0x00000400
111 #define CPUID_SEP 0x00000800
112 #define CPUID_MTRR 0x00001000
113 #define CPUID_PGE 0x00002000
114 #define CPUID_MCA 0x00004000
115 #define CPUID_CMOV 0x00008000
116 #define CPUID_PAT 0x00010000
117 #define CPUID_PSE36 0x00020000
118 #define CPUID_PSN 0x00040000
119 #define CPUID_CLFSH 0x00080000
120 #define CPUID_B20 0x00100000
121 #define CPUID_DS 0x00200000
122 #define CPUID_ACPI 0x00400000
123 #define CPUID_MMX 0x00800000
124 #define CPUID_FXSR 0x01000000
125 #define CPUID_SSE 0x02000000
126 #define CPUID_XMM 0x02000000
127 #define CPUID_SSE2 0x04000000
128 #define CPUID_SS 0x08000000
129 #define CPUID_HTT 0x10000000
130 #define CPUID_TM 0x20000000
131 #define CPUID_IA64 0x40000000
132 #define CPUID_PBE 0x80000000
134 #define CPUID2_SSE3 0x00000001
135 #define CPUID2_PCLMULQDQ 0x00000002
136 #define CPUID2_DTES64 0x00000004
137 #define CPUID2_MON 0x00000008
138 #define CPUID2_DS_CPL 0x00000010
139 #define CPUID2_VMX 0x00000020
140 #define CPUID2_SMX 0x00000040
141 #define CPUID2_EST 0x00000080
142 #define CPUID2_TM2 0x00000100
143 #define CPUID2_SSSE3 0x00000200
144 #define CPUID2_CNXTID 0x00000400
145 #define CPUID2_FMA 0x00001000
146 #define CPUID2_CX16 0x00002000
147 #define CPUID2_XTPR 0x00004000
148 #define CPUID2_PDCM 0x00008000
149 #define CPUID2_PCID 0x00020000
150 #define CPUID2_DCA 0x00040000
151 #define CPUID2_SSE41 0x00080000
152 #define CPUID2_SSE42 0x00100000
153 #define CPUID2_X2APIC 0x00200000
154 #define CPUID2_MOVBE 0x00400000
155 #define CPUID2_POPCNT 0x00800000
156 #define CPUID2_TSCDLT 0x01000000
157 #define CPUID2_AESNI 0x02000000
158 #define CPUID2_XSAVE 0x04000000
159 #define CPUID2_OSXSAVE 0x08000000
160 #define CPUID2_AVX 0x10000000
161 #define CPUID2_F16C 0x20000000
162 #define CPUID2_RDRAND 0x40000000
163 #define CPUID2_HV 0x80000000
166 * Important bits in the Thermal and Power Management flags
167 * CPUID.6 EAX and ECX.
169 #define CPUTPM1_SENSOR 0x00000001
170 #define CPUTPM1_TURBO 0x00000002
171 #define CPUTPM1_ARAT 0x00000004
172 #define CPUTPM2_EFFREQ 0x00000001
175 * Important bits in the AMD extended cpuid flags
177 #define AMDID_SYSCALL 0x00000800
178 #define AMDID_MP 0x00080000
179 #define AMDID_NX 0x00100000
180 #define AMDID_EXT_MMX 0x00400000
181 #define AMDID_FFXSR 0x01000000
182 #define AMDID_PAGE1GB 0x04000000
183 #define AMDID_RDTSCP 0x08000000
184 #define AMDID_LM 0x20000000
185 #define AMDID_EXT_3DNOW 0x40000000
186 #define AMDID_3DNOW 0x80000000
188 #define AMDID2_LAHF 0x00000001
189 #define AMDID2_CMP 0x00000002
190 #define AMDID2_SVM 0x00000004
191 #define AMDID2_EXT_APIC 0x00000008
192 #define AMDID2_CR8 0x00000010
193 #define AMDID2_ABM 0x00000020
194 #define AMDID2_SSE4A 0x00000040
195 #define AMDID2_MAS 0x00000080
196 #define AMDID2_PREFETCH 0x00000100
197 #define AMDID2_OSVW 0x00000200
198 #define AMDID2_IBS 0x00000400
199 #define AMDID2_XOP 0x00000800
200 #define AMDID2_SKINIT 0x00001000
201 #define AMDID2_WDT 0x00002000
202 #define AMDID2_LWP 0x00008000
203 #define AMDID2_FMA4 0x00010000
204 #define AMDID2_TCE 0x00020000
205 #define AMDID2_NODE_ID 0x00080000
206 #define AMDID2_TBM 0x00200000
207 #define AMDID2_TOPOLOGY 0x00400000
208 #define AMDID2_PCXC 0x00800000
209 #define AMDID2_PNXC 0x01000000
210 #define AMDID2_DBE 0x04000000
211 #define AMDID2_PTSC 0x08000000
212 #define AMDID2_PTSCEL2I 0x10000000
215 * CPUID instruction 1 eax info
217 #define CPUID_STEPPING 0x0000000f
218 #define CPUID_MODEL 0x000000f0
219 #define CPUID_FAMILY 0x00000f00
220 #define CPUID_EXT_MODEL 0x000f0000
221 #define CPUID_EXT_FAMILY 0x0ff00000
222 #define CPUID_TO_MODEL(id) \
223 ((((id) & CPUID_MODEL) >> 4) | \
224 (((id) & CPUID_EXT_MODEL) >> 12))
225 #define CPUID_TO_FAMILY(id) \
226 ((((id) & CPUID_FAMILY) >> 8) + \
227 (((id) & CPUID_EXT_FAMILY) >> 20))
230 * CPUID instruction 1 ebx info
232 #define CPUID_BRAND_INDEX 0x000000ff
233 #define CPUID_CLFUSH_SIZE 0x0000ff00
234 #define CPUID_HTT_CORES 0x00ff0000
235 #define CPUID_LOCAL_APIC_ID 0xff000000
238 * CPUID instruction 6 ecx info
240 #define CPUID_PERF_STAT 0x00000001
241 #define CPUID_PERF_BIAS 0x00000008
244 * CPUID instruction 0xb ebx info.
246 #define CPUID_TYPE_INVAL 0
247 #define CPUID_TYPE_SMT 1
248 #define CPUID_TYPE_CORE 2
251 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
253 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001
256 * AMD extended function 8000_0007h edx info
258 #define AMDPM_TS 0x00000001
259 #define AMDPM_FID 0x00000002
260 #define AMDPM_VID 0x00000004
261 #define AMDPM_TTP 0x00000008
262 #define AMDPM_TM 0x00000010
263 #define AMDPM_STC 0x00000020
264 #define AMDPM_100MHZ_STEPS 0x00000040
265 #define AMDPM_HW_PSTATE 0x00000080
266 #define AMDPM_TSC_INVARIANT 0x00000100
267 #define AMDPM_CPB 0x00000200
270 * AMD extended function 8000_0008h ecx info
272 #define AMDID_CMP_CORES 0x000000ff
273 #define AMDID_COREID_SIZE 0x0000f000
274 #define AMDID_COREID_SIZE_SHIFT 12
276 #define CPUID_STDEXT_FSGSBASE 0x00000001
277 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
278 #define CPUID_STDEXT_SMEP 0x00000080
279 #define CPUID_STDEXT_ENH_MOVSB 0x00000200
280 #define CPUID_STDEXT_INVPCID 0x00000400
283 * CPUID manufacturers identifiers
285 #define AMD_VENDOR_ID "AuthenticAMD"
286 #define CENTAUR_VENDOR_ID "CentaurHauls"
287 #define INTEL_VENDOR_ID "GenuineIntel"
290 * Model-specific registers for the i386 family
292 #define MSR_P5_MC_ADDR 0x000
293 #define MSR_P5_MC_TYPE 0x001
294 #define MSR_TSC 0x010
295 #define MSR_P5_CESR 0x011
296 #define MSR_P5_CTR0 0x012
297 #define MSR_P5_CTR1 0x013
298 #define MSR_IA32_PLATFORM_ID 0x017
299 #define MSR_APICBASE 0x01b
300 #define MSR_EBL_CR_POWERON 0x02a
301 #define MSR_TEST_CTL 0x033
302 #define MSR_IA32_FEATURE_CONTROL 0x03a
303 #define MSR_BIOS_UPDT_TRIG 0x079
304 #define MSR_BBL_CR_D0 0x088
305 #define MSR_BBL_CR_D1 0x089
306 #define MSR_BBL_CR_D2 0x08a
307 #define MSR_BIOS_SIGN 0x08b
308 #define MSR_PERFCTR0 0x0c1
309 #define MSR_PERFCTR1 0x0c2
310 #define MSR_MPERF 0x0e7
311 #define MSR_APERF 0x0e8
312 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
313 #define MSR_MTRRcap 0x0fe
314 #define MSR_BBL_CR_ADDR 0x116
315 #define MSR_BBL_CR_DECC 0x118
316 #define MSR_BBL_CR_CTL 0x119
317 #define MSR_BBL_CR_TRIG 0x11a
318 #define MSR_BBL_CR_BUSY 0x11b
319 #define MSR_BBL_CR_CTL3 0x11e
320 #define MSR_SYSENTER_CS_MSR 0x174
321 #define MSR_SYSENTER_ESP_MSR 0x175
322 #define MSR_SYSENTER_EIP_MSR 0x176
323 #define MSR_MCG_CAP 0x179
324 #define MSR_MCG_STATUS 0x17a
325 #define MSR_MCG_CTL 0x17b
326 #define MSR_EVNTSEL0 0x186
327 #define MSR_EVNTSEL1 0x187
328 #define MSR_THERM_CONTROL 0x19a
329 #define MSR_THERM_INTERRUPT 0x19b
330 #define MSR_THERM_STATUS 0x19c
331 #define MSR_IA32_MISC_ENABLE 0x1a0
332 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
333 #define MSR_DEBUGCTLMSR 0x1d9
334 #define MSR_LASTBRANCHFROMIP 0x1db
335 #define MSR_LASTBRANCHTOIP 0x1dc
336 #define MSR_LASTINTFROMIP 0x1dd
337 #define MSR_LASTINTTOIP 0x1de
338 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
339 #define MSR_MTRRVarBase 0x200
340 #define MSR_MTRR64kBase 0x250
341 #define MSR_MTRR16kBase 0x258
342 #define MSR_MTRR4kBase 0x268
343 #define MSR_PAT 0x277
344 #define MSR_MC0_CTL2 0x280
345 #define MSR_MTRRdefType 0x2ff
346 #define MSR_MC0_CTL 0x400
347 #define MSR_MC0_STATUS 0x401
348 #define MSR_MC0_ADDR 0x402
349 #define MSR_MC0_MISC 0x403
350 #define MSR_MC1_CTL 0x404
351 #define MSR_MC1_STATUS 0x405
352 #define MSR_MC1_ADDR 0x406
353 #define MSR_MC1_MISC 0x407
354 #define MSR_MC2_CTL 0x408
355 #define MSR_MC2_STATUS 0x409
356 #define MSR_MC2_ADDR 0x40a
357 #define MSR_MC2_MISC 0x40b
358 #define MSR_MC3_CTL 0x40c
359 #define MSR_MC3_STATUS 0x40d
360 #define MSR_MC3_ADDR 0x40e
361 #define MSR_MC3_MISC 0x40f
362 #define MSR_MC4_CTL 0x410
363 #define MSR_MC4_STATUS 0x411
364 #define MSR_MC4_ADDR 0x412
365 #define MSR_MC4_MISC 0x413
368 * Constants related to MSR's.
370 #define APICBASE_RESERVED 0x000006ff
371 #define APICBASE_BSP 0x00000100
372 #define APICBASE_ENABLED 0x00000800
373 #define APICBASE_ADDRESS 0xfffff000
378 #define PAT_UNCACHEABLE 0x00
379 #define PAT_WRITE_COMBINING 0x01
380 #define PAT_WRITE_THROUGH 0x04
381 #define PAT_WRITE_PROTECTED 0x05
382 #define PAT_WRITE_BACK 0x06
383 #define PAT_UNCACHED 0x07
384 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
385 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
388 * Constants related to MTRRs
390 #define MTRR_UNCACHEABLE 0x00
391 #define MTRR_WRITE_COMBINING 0x01
392 #define MTRR_WRITE_THROUGH 0x04
393 #define MTRR_WRITE_PROTECTED 0x05
394 #define MTRR_WRITE_BACK 0x06
395 #define MTRR_N64K 8 /* numbers of fixed-size entries */
398 #define MTRR_CAP_WC 0x0000000000000400
399 #define MTRR_CAP_FIXED 0x0000000000000100
400 #define MTRR_CAP_VCNT 0x00000000000000ff
401 #define MTRR_DEF_ENABLE 0x0000000000000800
402 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
403 #define MTRR_DEF_TYPE 0x00000000000000ff
404 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
405 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
406 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
407 #define MTRR_PHYSMASK_VALID 0x0000000000000800
409 /* Performance Control Register (5x86 only). */
411 #define PCR0_RSTK 0x01 /* Enables return stack */
412 #define PCR0_BTB 0x02 /* Enables branch target buffer */
413 #define PCR0_LOOP 0x04 /* Enables loop */
414 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
416 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
417 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
418 #define PCR0_LSSER 0x80 /* Disable reorder */
420 /* Device Identification Registers */
425 * Machine Check register constants.
427 #define MCG_CAP_COUNT 0x000000ff
428 #define MCG_CAP_CTL_P 0x00000100
429 #define MCG_CAP_EXT_P 0x00000200
430 #define MCG_CAP_CMCI_P 0x00000400
431 #define MCG_CAP_TES_P 0x00000800
432 #define MCG_CAP_EXT_CNT 0x00ff0000
433 #define MCG_CAP_SER_P 0x01000000
434 #define MCG_STATUS_RIPV 0x00000001
435 #define MCG_STATUS_EIPV 0x00000002
436 #define MCG_STATUS_MCIP 0x00000004
437 #define MCG_CTL_ENABLE 0xffffffffffffffff
438 #define MCG_CTL_DISABLE 0x0000000000000000
439 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
440 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
441 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
442 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
443 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
444 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
445 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
446 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
447 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
448 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
449 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
450 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
451 #define MC_STATUS_PCC 0x0200000000000000
452 #define MC_STATUS_ADDRV 0x0400000000000000
453 #define MC_STATUS_MISCV 0x0800000000000000
454 #define MC_STATUS_EN 0x1000000000000000
455 #define MC_STATUS_UC 0x2000000000000000
456 #define MC_STATUS_OVER 0x4000000000000000
457 #define MC_STATUS_VAL 0x8000000000000000
458 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
459 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
460 #define MC_CTL2_THRESHOLD 0x0000000000007fff
461 #define MC_CTL2_CMCI_EN 0x0000000040000000
464 * The following four 3-byte registers control the non-cacheable regions.
465 * These registers must be written as three separate bytes.
467 * NCRx+0: A31-A24 of starting address
468 * NCRx+1: A23-A16 of starting address
469 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
471 * The non-cacheable region's starting address must be aligned to the
472 * size indicated by the NCR_SIZE_xx field.
479 #define NCR_SIZE_0K 0
480 #define NCR_SIZE_4K 1
481 #define NCR_SIZE_8K 2
482 #define NCR_SIZE_16K 3
483 #define NCR_SIZE_32K 4
484 #define NCR_SIZE_64K 5
485 #define NCR_SIZE_128K 6
486 #define NCR_SIZE_256K 7
487 #define NCR_SIZE_512K 8
488 #define NCR_SIZE_1M 9
489 #define NCR_SIZE_2M 10
490 #define NCR_SIZE_4M 11
491 #define NCR_SIZE_8M 12
492 #define NCR_SIZE_16M 13
493 #define NCR_SIZE_32M 14
494 #define NCR_SIZE_4G 15
497 * The address region registers are used to specify the location and
498 * size for the eight address regions.
500 * ARRx + 0: A31-A24 of start address
501 * ARRx + 1: A23-A16 of start address
502 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
513 #define ARR_SIZE_0K 0
514 #define ARR_SIZE_4K 1
515 #define ARR_SIZE_8K 2
516 #define ARR_SIZE_16K 3
517 #define ARR_SIZE_32K 4
518 #define ARR_SIZE_64K 5
519 #define ARR_SIZE_128K 6
520 #define ARR_SIZE_256K 7
521 #define ARR_SIZE_512K 8
522 #define ARR_SIZE_1M 9
523 #define ARR_SIZE_2M 10
524 #define ARR_SIZE_4M 11
525 #define ARR_SIZE_8M 12
526 #define ARR_SIZE_16M 13
527 #define ARR_SIZE_32M 14
528 #define ARR_SIZE_4G 15
531 * The region control registers specify the attributes associated with
532 * the ARRx addres regions.
543 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
544 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
545 #define RCR_WWO 0x02 /* Weak write ordering. */
546 #define RCR_WL 0x04 /* Weak locking. */
547 #define RCR_WG 0x08 /* Write gathering. */
548 #define RCR_WT 0x10 /* Write-through. */
549 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
551 /* AMD Write Allocate Top-Of-Memory and Control Register */
552 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
553 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
554 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
557 #define MSR_EFER 0xc0000080 /* extended features */
558 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
559 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
560 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
561 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
562 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
563 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
564 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
565 #define MSR_PERFEVSEL0 0xc0010000
566 #define MSR_PERFEVSEL1 0xc0010001
567 #define MSR_PERFEVSEL2 0xc0010002
568 #define MSR_PERFEVSEL3 0xc0010003
571 #define MSR_PERFCTR0 0xc0010004
572 #define MSR_PERFCTR1 0xc0010005
573 #define MSR_PERFCTR2 0xc0010006
574 #define MSR_PERFCTR3 0xc0010007
575 #define MSR_SYSCFG 0xc0010010
576 #define MSR_HWCR 0xc0010015
577 #define MSR_IORRBASE0 0xc0010016
578 #define MSR_IORRMASK0 0xc0010017
579 #define MSR_IORRBASE1 0xc0010018
580 #define MSR_IORRMASK1 0xc0010019
581 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
582 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
583 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
584 #define MSR_MC0_CTL_MASK 0xc0010044
586 /* VIA ACE crypto featureset: for via_feature_rng */
587 #define VIA_HAS_RNG 1 /* cpu has RNG */
589 /* VIA ACE crypto featureset: for via_feature_xcrypt */
590 #define VIA_HAS_AES 1 /* cpu has AES */
591 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
592 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
593 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
595 /* Centaur Extended Feature flags */
596 #define VIA_CPUID_HAS_RNG 0x000004
597 #define VIA_CPUID_DO_RNG 0x000008
598 #define VIA_CPUID_HAS_ACE 0x000040
599 #define VIA_CPUID_DO_ACE 0x000080
600 #define VIA_CPUID_HAS_ACE2 0x000100
601 #define VIA_CPUID_DO_ACE2 0x000200
602 #define VIA_CPUID_HAS_PHE 0x000400
603 #define VIA_CPUID_DO_PHE 0x000800
604 #define VIA_CPUID_HAS_PMM 0x001000
605 #define VIA_CPUID_DO_PMM 0x002000
607 /* VIA ACE xcrypt-* instruction context control options */
608 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
609 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
610 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
611 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
612 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
613 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
614 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
615 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
616 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
617 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
618 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
619 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
620 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
622 #endif /* !_MACHINE_SPECIALREG_H_ */