2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
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17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in PPro special registers
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 * Bits in AMD64 special registers. EFER is 64 bits wide.
73 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
74 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
75 #define EFER_LMA 0x000000400 /* Long mode active (R) */
76 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
79 * CPUID instruction features register
81 #define CPUID_FPU 0x00000001
82 #define CPUID_VME 0x00000002
83 #define CPUID_DE 0x00000004
84 #define CPUID_PSE 0x00000008
85 #define CPUID_TSC 0x00000010
86 #define CPUID_MSR 0x00000020
87 #define CPUID_PAE 0x00000040
88 #define CPUID_MCE 0x00000080
89 #define CPUID_CX8 0x00000100
90 #define CPUID_APIC 0x00000200
91 #define CPUID_B10 0x00000400
92 #define CPUID_SEP 0x00000800
93 #define CPUID_MTRR 0x00001000
94 #define CPUID_PGE 0x00002000
95 #define CPUID_MCA 0x00004000
96 #define CPUID_CMOV 0x00008000
97 #define CPUID_PAT 0x00010000
98 #define CPUID_PSE36 0x00020000
99 #define CPUID_PSN 0x00040000
100 #define CPUID_CLFSH 0x00080000
101 #define CPUID_B20 0x00100000
102 #define CPUID_DS 0x00200000
103 #define CPUID_ACPI 0x00400000
104 #define CPUID_MMX 0x00800000
105 #define CPUID_FXSR 0x01000000
106 #define CPUID_SSE 0x02000000
107 #define CPUID_XMM 0x02000000
108 #define CPUID_SSE2 0x04000000
109 #define CPUID_SS 0x08000000
110 #define CPUID_HTT 0x10000000
111 #define CPUID_TM 0x20000000
112 #define CPUID_IA64 0x40000000
113 #define CPUID_PBE 0x80000000
115 #define CPUID2_SSE3 0x00000001
116 #define CPUID2_DTES64 0x00000004
117 #define CPUID2_MON 0x00000008
118 #define CPUID2_DS_CPL 0x00000010
119 #define CPUID2_VMX 0x00000020
120 #define CPUID2_SMX 0x00000040
121 #define CPUID2_EST 0x00000080
122 #define CPUID2_TM2 0x00000100
123 #define CPUID2_SSSE3 0x00000200
124 #define CPUID2_CNXTID 0x00000400
125 #define CPUID2_CX16 0x00002000
126 #define CPUID2_XTPR 0x00004000
127 #define CPUID2_PDCM 0x00008000
128 #define CPUID2_DCA 0x00040000
129 #define CPUID2_SSE41 0x00080000
130 #define CPUID2_SSE42 0x00100000
131 #define CPUID2_X2APIC 0x00200000
132 #define CPUID2_MOVBE 0x00400000
133 #define CPUID2_POPCNT 0x00800000
136 * Important bits in the AMD extended cpuid flags
138 #define AMDID_SYSCALL 0x00000800
139 #define AMDID_MP 0x00080000
140 #define AMDID_NX 0x00100000
141 #define AMDID_EXT_MMX 0x00400000
142 #define AMDID_FFXSR 0x01000000
143 #define AMDID_PAGE1GB 0x04000000
144 #define AMDID_RDTSCP 0x08000000
145 #define AMDID_LM 0x20000000
146 #define AMDID_EXT_3DNOW 0x40000000
147 #define AMDID_3DNOW 0x80000000
149 #define AMDID2_LAHF 0x00000001
150 #define AMDID2_CMP 0x00000002
151 #define AMDID2_SVM 0x00000004
152 #define AMDID2_EXT_APIC 0x00000008
153 #define AMDID2_CR8 0x00000010
154 #define AMDID2_ABM 0x00000020
155 #define AMDID2_SSE4A 0x00000040
156 #define AMDID2_MAS 0x00000080
157 #define AMDID2_PREFETCH 0x00000100
158 #define AMDID2_OSVW 0x00000200
159 #define AMDID2_IBS 0x00000400
160 #define AMDID2_SSE5 0x00000800
161 #define AMDID2_SKINIT 0x00001000
162 #define AMDID2_WDT 0x00002000
165 * CPUID instruction 1 eax info
167 #define CPUID_STEPPING 0x0000000f
168 #define CPUID_MODEL 0x000000f0
169 #define CPUID_FAMILY 0x00000f00
170 #define CPUID_EXT_MODEL 0x000f0000
171 #define CPUID_EXT_FAMILY 0x0ff00000
172 #define CPUID_TO_MODEL(id) \
173 ((((id) & CPUID_MODEL) >> 4) | \
174 (((id) & CPUID_EXT_MODEL) >> 12))
175 #define CPUID_TO_FAMILY(id) \
176 ((((id) & CPUID_FAMILY) >> 8) + \
177 (((id) & CPUID_EXT_FAMILY) >> 20))
180 * CPUID instruction 1 ebx info
182 #define CPUID_BRAND_INDEX 0x000000ff
183 #define CPUID_CLFUSH_SIZE 0x0000ff00
184 #define CPUID_HTT_CORES 0x00ff0000
185 #define CPUID_LOCAL_APIC_ID 0xff000000
188 * CPUID instruction 0xb ebx info.
190 #define CPUID_TYPE_INVAL 0
191 #define CPUID_TYPE_SMT 1
192 #define CPUID_TYPE_CORE 2
195 * AMD extended function 8000_0007h edx info
197 #define AMDPM_TS 0x00000001
198 #define AMDPM_FID 0x00000002
199 #define AMDPM_VID 0x00000004
200 #define AMDPM_TTP 0x00000008
201 #define AMDPM_TM 0x00000010
202 #define AMDPM_STC 0x00000020
203 #define AMDPM_100MHZ_STEPS 0x00000040
204 #define AMDPM_HW_PSTATE 0x00000080
205 #define AMDPM_TSC_INVARIANT 0x00000100
208 * AMD extended function 8000_0008h ecx info
210 #define AMDID_CMP_CORES 0x000000ff
213 * CPUID manufacturers identifiers
215 #define AMD_VENDOR_ID "AuthenticAMD"
216 #define CENTAUR_VENDOR_ID "CentaurHauls"
217 #define INTEL_VENDOR_ID "GenuineIntel"
220 * Model-specific registers for the i386 family
222 #define MSR_P5_MC_ADDR 0x000
223 #define MSR_P5_MC_TYPE 0x001
224 #define MSR_TSC 0x010
225 #define MSR_P5_CESR 0x011
226 #define MSR_P5_CTR0 0x012
227 #define MSR_P5_CTR1 0x013
228 #define MSR_IA32_PLATFORM_ID 0x017
229 #define MSR_APICBASE 0x01b
230 #define MSR_EBL_CR_POWERON 0x02a
231 #define MSR_TEST_CTL 0x033
232 #define MSR_BIOS_UPDT_TRIG 0x079
233 #define MSR_BBL_CR_D0 0x088
234 #define MSR_BBL_CR_D1 0x089
235 #define MSR_BBL_CR_D2 0x08a
236 #define MSR_BIOS_SIGN 0x08b
237 #define MSR_PERFCTR0 0x0c1
238 #define MSR_PERFCTR1 0x0c2
239 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
240 #define MSR_MTRRcap 0x0fe
241 #define MSR_BBL_CR_ADDR 0x116
242 #define MSR_BBL_CR_DECC 0x118
243 #define MSR_BBL_CR_CTL 0x119
244 #define MSR_BBL_CR_TRIG 0x11a
245 #define MSR_BBL_CR_BUSY 0x11b
246 #define MSR_BBL_CR_CTL3 0x11e
247 #define MSR_SYSENTER_CS_MSR 0x174
248 #define MSR_SYSENTER_ESP_MSR 0x175
249 #define MSR_SYSENTER_EIP_MSR 0x176
250 #define MSR_MCG_CAP 0x179
251 #define MSR_MCG_STATUS 0x17a
252 #define MSR_MCG_CTL 0x17b
253 #define MSR_EVNTSEL0 0x186
254 #define MSR_EVNTSEL1 0x187
255 #define MSR_THERM_CONTROL 0x19a
256 #define MSR_THERM_INTERRUPT 0x19b
257 #define MSR_THERM_STATUS 0x19c
258 #define MSR_IA32_MISC_ENABLE 0x1a0
259 #define MSR_DEBUGCTLMSR 0x1d9
260 #define MSR_LASTBRANCHFROMIP 0x1db
261 #define MSR_LASTBRANCHTOIP 0x1dc
262 #define MSR_LASTINTFROMIP 0x1dd
263 #define MSR_LASTINTTOIP 0x1de
264 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
265 #define MSR_MTRRVarBase 0x200
266 #define MSR_MTRR64kBase 0x250
267 #define MSR_MTRR16kBase 0x258
268 #define MSR_MTRR4kBase 0x268
269 #define MSR_PAT 0x277
270 #define MSR_MC0_CTL2 0x280
271 #define MSR_MTRRdefType 0x2ff
272 #define MSR_MC0_CTL 0x400
273 #define MSR_MC0_STATUS 0x401
274 #define MSR_MC0_ADDR 0x402
275 #define MSR_MC0_MISC 0x403
276 #define MSR_MC1_CTL 0x404
277 #define MSR_MC1_STATUS 0x405
278 #define MSR_MC1_ADDR 0x406
279 #define MSR_MC1_MISC 0x407
280 #define MSR_MC2_CTL 0x408
281 #define MSR_MC2_STATUS 0x409
282 #define MSR_MC2_ADDR 0x40a
283 #define MSR_MC2_MISC 0x40b
284 #define MSR_MC3_CTL 0x40c
285 #define MSR_MC3_STATUS 0x40d
286 #define MSR_MC3_ADDR 0x40e
287 #define MSR_MC3_MISC 0x40f
288 #define MSR_MC4_CTL 0x410
289 #define MSR_MC4_STATUS 0x411
290 #define MSR_MC4_ADDR 0x412
291 #define MSR_MC4_MISC 0x413
294 * Constants related to MSR's.
296 #define APICBASE_RESERVED 0x000006ff
297 #define APICBASE_BSP 0x00000100
298 #define APICBASE_ENABLED 0x00000800
299 #define APICBASE_ADDRESS 0xfffff000
304 #define PAT_UNCACHEABLE 0x00
305 #define PAT_WRITE_COMBINING 0x01
306 #define PAT_WRITE_THROUGH 0x04
307 #define PAT_WRITE_PROTECTED 0x05
308 #define PAT_WRITE_BACK 0x06
309 #define PAT_UNCACHED 0x07
310 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
311 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
314 * Constants related to MTRRs
316 #define MTRR_UNCACHEABLE 0x00
317 #define MTRR_WRITE_COMBINING 0x01
318 #define MTRR_WRITE_THROUGH 0x04
319 #define MTRR_WRITE_PROTECTED 0x05
320 #define MTRR_WRITE_BACK 0x06
321 #define MTRR_N64K 8 /* numbers of fixed-size entries */
324 #define MTRR_CAP_WC 0x0000000000000400
325 #define MTRR_CAP_FIXED 0x0000000000000100
326 #define MTRR_CAP_VCNT 0x00000000000000ff
327 #define MTRR_DEF_ENABLE 0x0000000000000800
328 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
329 #define MTRR_DEF_TYPE 0x00000000000000ff
330 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
331 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
332 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
333 #define MTRR_PHYSMASK_VALID 0x0000000000000800
335 /* Performance Control Register (5x86 only). */
337 #define PCR0_RSTK 0x01 /* Enables return stack */
338 #define PCR0_BTB 0x02 /* Enables branch target buffer */
339 #define PCR0_LOOP 0x04 /* Enables loop */
340 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
342 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
343 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
344 #define PCR0_LSSER 0x80 /* Disable reorder */
346 /* Device Identification Registers */
351 * Machine Check register constants.
353 #define MCG_CAP_COUNT 0x000000ff
354 #define MCG_CAP_CTL_P 0x00000100
355 #define MCG_CAP_EXT_P 0x00000200
356 #define MCG_CAP_CMCI_P 0x00000400
357 #define MCG_CAP_TES_P 0x00000800
358 #define MCG_CAP_EXT_CNT 0x00ff0000
359 #define MCG_CAP_SER_P 0x01000000
360 #define MCG_STATUS_RIPV 0x00000001
361 #define MCG_STATUS_EIPV 0x00000002
362 #define MCG_STATUS_MCIP 0x00000004
363 #define MCG_CTL_ENABLE 0xffffffffffffffff
364 #define MCG_CTL_DISABLE 0x0000000000000000
365 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
366 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
367 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
368 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
369 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
370 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
371 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
372 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
373 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_TES_P */
374 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
375 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_CMCI_P */
376 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_CMCI_P */
377 #define MC_STATUS_PCC 0x0200000000000000
378 #define MC_STATUS_ADDRV 0x0400000000000000
379 #define MC_STATUS_MISCV 0x0800000000000000
380 #define MC_STATUS_EN 0x1000000000000000
381 #define MC_STATUS_UC 0x2000000000000000
382 #define MC_STATUS_OVER 0x4000000000000000
383 #define MC_STATUS_VAL 0x8000000000000000
384 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
385 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
386 #define MC_CTL2_THRESHOLD 0x0000000000003fff
387 #define MC_CTL2_CMCI_EN 0x0000000040000000
390 * The following four 3-byte registers control the non-cacheable regions.
391 * These registers must be written as three separate bytes.
393 * NCRx+0: A31-A24 of starting address
394 * NCRx+1: A23-A16 of starting address
395 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
397 * The non-cacheable region's starting address must be aligned to the
398 * size indicated by the NCR_SIZE_xx field.
405 #define NCR_SIZE_0K 0
406 #define NCR_SIZE_4K 1
407 #define NCR_SIZE_8K 2
408 #define NCR_SIZE_16K 3
409 #define NCR_SIZE_32K 4
410 #define NCR_SIZE_64K 5
411 #define NCR_SIZE_128K 6
412 #define NCR_SIZE_256K 7
413 #define NCR_SIZE_512K 8
414 #define NCR_SIZE_1M 9
415 #define NCR_SIZE_2M 10
416 #define NCR_SIZE_4M 11
417 #define NCR_SIZE_8M 12
418 #define NCR_SIZE_16M 13
419 #define NCR_SIZE_32M 14
420 #define NCR_SIZE_4G 15
423 * The address region registers are used to specify the location and
424 * size for the eight address regions.
426 * ARRx + 0: A31-A24 of start address
427 * ARRx + 1: A23-A16 of start address
428 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
439 #define ARR_SIZE_0K 0
440 #define ARR_SIZE_4K 1
441 #define ARR_SIZE_8K 2
442 #define ARR_SIZE_16K 3
443 #define ARR_SIZE_32K 4
444 #define ARR_SIZE_64K 5
445 #define ARR_SIZE_128K 6
446 #define ARR_SIZE_256K 7
447 #define ARR_SIZE_512K 8
448 #define ARR_SIZE_1M 9
449 #define ARR_SIZE_2M 10
450 #define ARR_SIZE_4M 11
451 #define ARR_SIZE_8M 12
452 #define ARR_SIZE_16M 13
453 #define ARR_SIZE_32M 14
454 #define ARR_SIZE_4G 15
457 * The region control registers specify the attributes associated with
458 * the ARRx addres regions.
469 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
470 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
471 #define RCR_WWO 0x02 /* Weak write ordering. */
472 #define RCR_WL 0x04 /* Weak locking. */
473 #define RCR_WG 0x08 /* Write gathering. */
474 #define RCR_WT 0x10 /* Write-through. */
475 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
477 /* AMD Write Allocate Top-Of-Memory and Control Register */
478 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
479 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
480 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
483 #define MSR_EFER 0xc0000080 /* extended features */
484 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
485 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
486 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
487 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
488 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
489 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
490 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
491 #define MSR_PERFEVSEL0 0xc0010000
492 #define MSR_PERFEVSEL1 0xc0010001
493 #define MSR_PERFEVSEL2 0xc0010002
494 #define MSR_PERFEVSEL3 0xc0010003
497 #define MSR_PERFCTR0 0xc0010004
498 #define MSR_PERFCTR1 0xc0010005
499 #define MSR_PERFCTR2 0xc0010006
500 #define MSR_PERFCTR3 0xc0010007
501 #define MSR_SYSCFG 0xc0010010
502 #define MSR_IORRBASE0 0xc0010016
503 #define MSR_IORRMASK0 0xc0010017
504 #define MSR_IORRBASE1 0xc0010018
505 #define MSR_IORRMASK1 0xc0010019
506 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
507 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
508 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
509 #define MSR_MC0_CTL_MASK 0xc0010044
511 /* VIA ACE crypto featureset: for via_feature_rng */
512 #define VIA_HAS_RNG 1 /* cpu has RNG */
514 /* VIA ACE crypto featureset: for via_feature_xcrypt */
515 #define VIA_HAS_AES 1 /* cpu has AES */
516 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
517 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
518 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
520 /* Centaur Extended Feature flags */
521 #define VIA_CPUID_HAS_RNG 0x000004
522 #define VIA_CPUID_DO_RNG 0x000008
523 #define VIA_CPUID_HAS_ACE 0x000040
524 #define VIA_CPUID_DO_ACE 0x000080
525 #define VIA_CPUID_HAS_ACE2 0x000100
526 #define VIA_CPUID_DO_ACE2 0x000200
527 #define VIA_CPUID_HAS_PHE 0x000400
528 #define VIA_CPUID_DO_PHE 0x000800
529 #define VIA_CPUID_HAS_PMM 0x001000
530 #define VIA_CPUID_DO_PMM 0x002000
532 /* VIA ACE xcrypt-* instruction context control options */
533 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
534 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
535 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
536 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
537 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
538 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
539 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
540 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
541 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
542 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
543 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
544 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
545 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
547 #endif /* !_MACHINE_SPECIALREG_H_ */