2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/mutex.h>
38 #include <sys/sysctl.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
43 #include <machine/pci_cfgreg.h>
51 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
53 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
54 unsigned reg, unsigned bytes);
55 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
56 unsigned reg, int data, unsigned bytes);
57 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
58 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
63 static vm_offset_t pcie_base;
64 static int pcie_minbus, pcie_maxbus;
65 static uint32_t pcie_badslots;
66 static struct mtx pcicfg_mtx;
67 static int mcfg_enable = 1;
68 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
69 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
70 "Enable support for PCI-e memory mapped config access");
73 * Initialise access to PCI configuration space
83 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
87 if (cfgmech != CFGMECH_NONE)
92 * Grope around in the PCI config space to see if this is a
93 * chipset that is capable of doing memory-mapped config cycles.
94 * This also implies that it can do PCIe extended config cycles.
97 /* Check for supported chipsets */
98 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
99 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
105 /* Intel 7520 or 7320 */
106 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
107 pcie_cfgregopen(pciebar, 0, 255);
112 /* Intel 915, 925, or 915GM */
113 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
114 pcie_cfgregopen(pciebar, 0, 255);
123 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
126 if (cfgmech == CFGMECH_PCIE &&
127 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
128 (bus != 0 || !(1 << slot & pcie_badslots)))
129 return (pciereg_cfgread(bus, slot, func, reg, bytes));
131 return (pcireg_cfgread(bus, slot, func, reg, bytes));
135 * Read configuration space register
138 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
143 * Some BIOS writers seem to want to ignore the spec and put
144 * 0 in the intline rather than 255 to indicate none. Some use
145 * numbers in the range 128-254 to indicate something strange and
146 * apparently undocumented anywhere. Assume these are completely bogus
147 * and map them to 255, which the rest of the PCI code recognizes as
150 if (reg == PCIR_INTLINE && bytes == 1) {
151 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
152 if (line == 0 || line >= 128)
153 line = PCI_INVALID_IRQ;
156 return (pci_docfgregread(bus, slot, func, reg, bytes));
160 * Write configuration space register
163 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
166 if (cfgmech == CFGMECH_PCIE &&
167 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
168 (bus != 0 || !(1 << slot & pcie_badslots)))
169 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
171 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
175 * Configuration space access using direct register operations
178 /* enable configuration space accesses and return data port address */
180 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
184 if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
185 (unsigned)reg <= PCI_REGMAX && bytes != 3 &&
186 (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
187 outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11)
188 | (func << 8) | (reg & ~0x03));
189 dataport = CONF1_DATA_PORT + (reg & 0x03);
194 /* disable configuration space accesses */
200 * Do nothing. Writing a 0 to the address port can apparently
201 * confuse some bridges and cause spurious access failures.
206 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
211 mtx_lock_spin(&pcicfg_mtx);
212 port = pci_cfgenable(bus, slot, func, reg, bytes);
227 mtx_unlock_spin(&pcicfg_mtx);
232 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
236 mtx_lock_spin(&pcicfg_mtx);
237 port = pci_cfgenable(bus, slot, func, reg, bytes);
252 mtx_unlock_spin(&pcicfg_mtx);
256 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
268 printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
271 /* XXX: We should make sure this really fits into the direct map. */
272 pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
273 pcie_minbus = minbus;
274 pcie_maxbus = maxbus;
275 cfgmech = CFGMECH_PCIE;
278 * On some AMD systems, some of the devices on bus 0 are
279 * inaccessible using memory-mapped PCI config access. Walk
280 * bus 0 looking for such devices. For these devices, we will
281 * fall back to using type 1 config access instead.
283 if (pci_cfgregopen() != 0) {
284 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
285 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
286 if (val1 == 0xffffffff)
289 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
291 pcie_badslots |= (1 << slot);
298 #define PCIE_VADDR(base, reg, bus, slot, func) \
300 ((((bus) & 0xff) << 20) | \
301 (((slot) & 0x1f) << 15) | \
302 (((func) & 0x7) << 12) | \
306 * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
307 * have a requirement that all accesses to the memory mapped PCI configuration
308 * space are done using AX class of registers.
309 * Since other vendors do not currently have any contradicting requirements
310 * the AMD access pattern is applied universally.
314 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
320 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
321 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
324 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
328 __asm("movl %1, %0" : "=a" (data)
329 : "m" (*(volatile uint32_t *)va));
332 __asm("movzwl %1, %0" : "=a" (data)
333 : "m" (*(volatile uint16_t *)va));
336 __asm("movzbl %1, %0" : "=a" (data)
337 : "m" (*(volatile uint8_t *)va));
345 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
350 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
351 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
354 va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
358 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
362 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
363 : "a" ((uint16_t)data));
366 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
367 : "a" ((uint8_t)data));