2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/systm.h>
38 #include <machine/clock.h>
39 #include <x86/specialreg.h>
40 #include <x86/apicreg.h>
42 #include <machine/vmm.h>
45 #include "vmm_lapic.h"
50 #define VLAPIC_CTR0(vlapic, format) \
51 VMM_CTR0((vlapic)->vm, (vlapic)->vcpuid, format)
53 #define VLAPIC_CTR1(vlapic, format, p1) \
54 VMM_CTR1((vlapic)->vm, (vlapic)->vcpuid, format, p1)
56 #define VLAPIC_CTR_IRR(vlapic, msg) \
58 uint32_t *irrptr = &(vlapic)->apic.irr0; \
59 irrptr[0] = irrptr[0]; /* silence compiler */ \
60 VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \
61 VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \
62 VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \
63 VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \
64 VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \
65 VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \
66 VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \
67 VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \
70 #define VLAPIC_CTR_ISR(vlapic, msg) \
72 uint32_t *isrptr = &(vlapic)->apic.isr0; \
73 isrptr[0] = isrptr[0]; /* silence compiler */ \
74 VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \
75 VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \
76 VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \
77 VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \
78 VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \
79 VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \
80 VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \
81 VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \
84 static MALLOC_DEFINE(M_VLAPIC, "vlapic", "vlapic");
86 #define PRIO(x) ((x) >> 4)
88 #define VLAPIC_VERSION (16)
89 #define VLAPIC_MAXLVT_ENTRIES (5)
91 #define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0)
103 struct io_region *mmio;
104 struct vdev_ops *ops;
113 * The 'isrvec_stk' is a stack of vectors injected by the local apic.
114 * A vector is popped from the stack when the processor does an EOI.
115 * The vector on the top of the stack is used to compute the
116 * Processor Priority in conjunction with the TPR.
118 uint8_t isrvec_stk[ISRVEC_STK_SIZE];
121 uint64_t msr_apicbase;
122 enum boot_state boot_state;
125 #define VLAPIC_BUS_FREQ tsc_freq
128 vlapic_timer_divisor(uint32_t dcr)
148 panic("vlapic_timer_divisor: invalid dcr 0x%08x", dcr);
153 vlapic_mask_lvts(uint32_t *lvts, int num_lvt)
156 for (i = 0; i < num_lvt; i++) {
164 vlapic_dump_lvt(uint32_t offset, uint32_t *lvt)
166 printf("Offset %x: lvt %08x (V:%02x DS:%x M:%x)\n", offset,
167 *lvt, *lvt & APIC_LVTT_VECTOR, *lvt & APIC_LVTT_DS,
173 vlapic_get_ccr(struct vlapic *vlapic)
175 struct LAPIC *lapic = &vlapic->apic;
176 return lapic->ccr_timer;
180 vlapic_update_errors(struct vlapic *vlapic)
182 struct LAPIC *lapic = &vlapic->apic;
183 lapic->esr = 0; // XXX
187 vlapic_init_ipi(struct vlapic *vlapic)
189 struct LAPIC *lapic = &vlapic->apic;
190 lapic->version = VLAPIC_VERSION;
191 lapic->version |= (VLAPIC_MAXLVT_ENTRIES < MAXLVTSHIFT);
192 lapic->dfr = 0xffffffff;
193 lapic->svr = APIC_SVR_VECTOR;
194 vlapic_mask_lvts(&lapic->lvt_timer, VLAPIC_MAXLVT_ENTRIES+1);
198 vlapic_op_reset(void* dev)
200 struct vlapic *vlapic = (struct vlapic*)dev;
201 struct LAPIC *lapic = &vlapic->apic;
203 memset(lapic, 0, sizeof(*lapic));
204 lapic->apr = vlapic->vcpuid;
205 vlapic_init_ipi(vlapic);
206 vlapic->divisor = vlapic_timer_divisor(lapic->dcr_timer);
208 if (vlapic->vcpuid == 0)
209 vlapic->boot_state = BS_RUNNING; /* BSP */
211 vlapic->boot_state = BS_INIT; /* AP */
218 vlapic_op_init(void* dev)
220 struct vlapic *vlapic = (struct vlapic*)dev;
221 vdev_register_region(vlapic->ops, vlapic, vlapic->mmio);
222 return vlapic_op_reset(dev);
226 vlapic_op_halt(void* dev)
228 struct vlapic *vlapic = (struct vlapic*)dev;
229 vdev_unregister_region(vlapic, vlapic->mmio);
235 vlapic_set_intr_ready(struct vlapic *vlapic, int vector)
237 struct LAPIC *lapic = &vlapic->apic;
241 if (vector < 0 || vector >= 256)
242 panic("vlapic_set_intr_ready: invalid vector %d\n", vector);
244 idx = (vector / 32) * 4;
245 irrptr = &lapic->irr0;
246 atomic_set_int(&irrptr[idx], 1 << (vector % 32));
247 VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready");
251 vlapic_start_timer(struct vlapic *vlapic, uint32_t elapsed)
255 icr_timer = vlapic->apic.icr_timer;
257 vlapic->ccr_ticks = ticks;
258 if (elapsed < icr_timer)
259 vlapic->apic.ccr_timer = icr_timer - elapsed;
262 * This can happen when the guest is trying to run its local
263 * apic timer higher that the setting of 'hz' in the host.
265 * We deal with this by running the guest local apic timer
266 * at the rate of the host's 'hz' setting.
268 vlapic->apic.ccr_timer = 0;
272 static __inline uint32_t *
273 vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset)
275 struct LAPIC *lapic = &vlapic->apic;
278 if (offset < APIC_OFFSET_TIMER_LVT || offset > APIC_OFFSET_ERROR_LVT) {
279 panic("vlapic_get_lvt: invalid LVT\n");
281 i = (offset - APIC_OFFSET_TIMER_LVT) >> 2;
282 return ((&lapic->lvt_timer) + i);;
287 dump_isrvec_stk(struct vlapic *vlapic)
292 isrptr = &vlapic->apic.isr0;
293 for (i = 0; i < 8; i++)
294 printf("ISR%d 0x%08x\n", i, isrptr[i * 4]);
296 for (i = 0; i <= vlapic->isrvec_stk_top; i++)
297 printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]);
302 * Algorithm adopted from section "Interrupt, Task and Processor Priority"
303 * in Intel Architecture Manual Vol 3a.
306 vlapic_update_ppr(struct vlapic *vlapic)
308 int isrvec, tpr, ppr;
311 * Note that the value on the stack at index 0 is always 0.
313 * This is a placeholder for the value of ISRV when none of the
314 * bits is set in the ISRx registers.
316 isrvec = vlapic->isrvec_stk[vlapic->isrvec_stk_top];
317 tpr = vlapic->apic.tpr;
321 int i, lastprio, curprio, vector, idx;
324 if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
325 panic("isrvec_stk is corrupted: %d", isrvec);
328 * Make sure that the priority of the nested interrupts is
332 for (i = 1; i <= vlapic->isrvec_stk_top; i++) {
333 curprio = PRIO(vlapic->isrvec_stk[i]);
334 if (curprio <= lastprio) {
335 dump_isrvec_stk(vlapic);
336 panic("isrvec_stk does not satisfy invariant");
342 * Make sure that each bit set in the ISRx registers has a
343 * corresponding entry on the isrvec stack.
346 isrptr = &vlapic->apic.isr0;
347 for (vector = 0; vector < 256; vector++) {
348 idx = (vector / 32) * 4;
349 if (isrptr[idx] & (1 << (vector % 32))) {
350 if (i > vlapic->isrvec_stk_top ||
351 vlapic->isrvec_stk[i] != vector) {
352 dump_isrvec_stk(vlapic);
353 panic("ISR and isrvec_stk out of sync");
361 if (PRIO(tpr) >= PRIO(isrvec))
366 vlapic->apic.ppr = ppr;
367 VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr);
371 vlapic_process_eoi(struct vlapic *vlapic)
373 struct LAPIC *lapic = &vlapic->apic;
377 isrptr = &lapic->isr0;
380 * The x86 architecture reserves the the first 32 vectors for use
383 for (i = 7; i > 0; i--) {
385 bitpos = fls(isrptr[idx]);
387 if (vlapic->isrvec_stk_top <= 0) {
388 panic("invalid vlapic isrvec_stk_top %d",
389 vlapic->isrvec_stk_top);
391 isrptr[idx] &= ~(1 << (bitpos - 1));
392 VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi");
393 vlapic->isrvec_stk_top--;
394 vlapic_update_ppr(vlapic);
401 vlapic_get_lvt_field(uint32_t *lvt, uint32_t mask)
403 return (*lvt & mask);
407 vlapic_periodic_timer(struct vlapic *vlapic)
411 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
413 return (vlapic_get_lvt_field(lvt, APIC_LVTT_TM_PERIODIC));
416 static VMM_STAT(VLAPIC_INTR_TIMER, "timer interrupts generated by vlapic");
419 vlapic_fire_timer(struct vlapic *vlapic)
424 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
426 if (!vlapic_get_lvt_field(lvt, APIC_LVTT_M)) {
427 vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_INTR_TIMER, 1);
428 vector = vlapic_get_lvt_field(lvt,APIC_LVTT_VECTOR);
429 vlapic_set_intr_ready(vlapic, vector);
433 static VMM_STAT_ARRAY(IPIS_SENT, VM_MAXCPU, "ipis sent to vcpu");
436 lapic_process_icr(struct vlapic *vlapic, uint64_t icrval)
440 uint32_t dest, vec, mode;
441 struct vlapic *vlapic2;
442 struct vm_exit *vmexit;
447 dest = icrval >> (32 + 24);
448 vec = icrval & APIC_VECTOR_MASK;
449 mode = icrval & APIC_DELMODE_MASK;
451 if (mode == APIC_DELMODE_FIXED || mode == APIC_DELMODE_NMI) {
452 switch (icrval & APIC_DEST_MASK) {
453 case APIC_DEST_DESTFLD:
454 CPU_SETOF(dest, &dmask);
457 CPU_SETOF(vlapic->vcpuid, &dmask);
459 case APIC_DEST_ALLISELF:
460 dmask = vm_active_cpus(vlapic->vm);
462 case APIC_DEST_ALLESELF:
463 dmask = vm_active_cpus(vlapic->vm);
464 CPU_CLR(vlapic->vcpuid, &dmask);
467 CPU_ZERO(&dmask); /* satisfy gcc */
471 while ((i = CPU_FFS(&dmask)) != 0) {
474 if (mode == APIC_DELMODE_FIXED) {
475 lapic_set_intr(vlapic->vm, i, vec);
476 vmm_stat_array_incr(vlapic->vm, vlapic->vcpuid,
479 vm_inject_nmi(vlapic->vm, i);
482 return (0); /* handled completely in the kernel */
485 if (mode == APIC_DELMODE_INIT) {
486 if ((icrval & APIC_LEVEL_MASK) == APIC_LEVEL_DEASSERT)
489 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) {
490 vlapic2 = vm_lapic(vlapic->vm, dest);
492 /* move from INIT to waiting-for-SIPI state */
493 if (vlapic2->boot_state == BS_INIT) {
494 vlapic2->boot_state = BS_SIPI;
501 if (mode == APIC_DELMODE_STARTUP) {
502 if (vlapic->vcpuid == 0 && dest != 0 && dest < VM_MAXCPU) {
503 vlapic2 = vm_lapic(vlapic->vm, dest);
506 * Ignore SIPIs in any state other than wait-for-SIPI
508 if (vlapic2->boot_state != BS_SIPI)
511 vmexit = vm_exitinfo(vlapic->vm, vlapic->vcpuid);
512 vmexit->exitcode = VM_EXITCODE_SPINUP_AP;
513 vmexit->u.spinup_ap.vcpu = dest;
514 vmexit->u.spinup_ap.rip = vec << PAGE_SHIFT;
517 * XXX this assumes that the startup IPI always succeeds
519 vlapic2->boot_state = BS_RUNNING;
520 vm_activate_cpu(vlapic2->vm, dest);
527 * This will cause a return to userland.
533 vlapic_pending_intr(struct vlapic *vlapic)
535 struct LAPIC *lapic = &vlapic->apic;
536 int idx, i, bitpos, vector;
537 uint32_t *irrptr, val;
539 irrptr = &lapic->irr0;
542 * The x86 architecture reserves the the first 32 vectors for use
545 for (i = 7; i > 0; i--) {
547 val = atomic_load_acq_int(&irrptr[idx]);
550 vector = i * 32 + (bitpos - 1);
551 if (PRIO(vector) > PRIO(lapic->ppr)) {
552 VLAPIC_CTR1(vlapic, "pending intr %d", vector);
558 VLAPIC_CTR0(vlapic, "no pending intr");
563 vlapic_intr_accepted(struct vlapic *vlapic, int vector)
565 struct LAPIC *lapic = &vlapic->apic;
566 uint32_t *irrptr, *isrptr;
570 * clear the ready bit for vector being accepted in irr
571 * and set the vector as in service in isr.
573 idx = (vector / 32) * 4;
575 irrptr = &lapic->irr0;
576 atomic_clear_int(&irrptr[idx], 1 << (vector % 32));
577 VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");
579 isrptr = &lapic->isr0;
580 isrptr[idx] |= 1 << (vector % 32);
581 VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");
586 vlapic->isrvec_stk_top++;
588 stk_top = vlapic->isrvec_stk_top;
589 if (stk_top >= ISRVEC_STK_SIZE)
590 panic("isrvec_stk_top overflow %d", stk_top);
592 vlapic->isrvec_stk[stk_top] = vector;
593 vlapic_update_ppr(vlapic);
597 vlapic_op_mem_read(void* dev, uint64_t gpa, opsize_t size, uint64_t *data)
599 struct vlapic *vlapic = (struct vlapic*)dev;
600 struct LAPIC *lapic = &vlapic->apic;
601 uint64_t offset = gpa & ~(PAGE_SIZE);
605 if (offset > sizeof(*lapic)) {
615 *data = vlapic->vcpuid;
617 *data = vlapic->vcpuid << 24;
619 case APIC_OFFSET_VER:
620 *data = lapic->version;
622 case APIC_OFFSET_TPR:
625 case APIC_OFFSET_APR:
628 case APIC_OFFSET_PPR:
631 case APIC_OFFSET_EOI:
634 case APIC_OFFSET_LDR:
637 case APIC_OFFSET_DFR:
640 case APIC_OFFSET_SVR:
643 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7:
644 i = (offset - APIC_OFFSET_ISR0) >> 2;
648 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7:
649 i = (offset - APIC_OFFSET_TMR0) >> 2;
653 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7:
654 i = (offset - APIC_OFFSET_IRR0) >> 2;
656 *data = atomic_load_acq_int(reg + i);
658 case APIC_OFFSET_ESR:
661 case APIC_OFFSET_ICR_LOW:
662 *data = lapic->icr_lo;
664 case APIC_OFFSET_ICR_HI:
665 *data = lapic->icr_hi;
667 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
668 reg = vlapic_get_lvt(vlapic, offset);
671 case APIC_OFFSET_ICR:
672 *data = lapic->icr_timer;
674 case APIC_OFFSET_CCR:
675 *data = vlapic_get_ccr(vlapic);
677 case APIC_OFFSET_DCR:
678 *data = lapic->dcr_timer;
680 case APIC_OFFSET_RRR:
689 vlapic_op_mem_write(void* dev, uint64_t gpa, opsize_t size, uint64_t data)
691 struct vlapic *vlapic = (struct vlapic*)dev;
692 struct LAPIC *lapic = &vlapic->apic;
693 uint64_t offset = gpa & ~(PAGE_SIZE);
697 if (offset > sizeof(*lapic)) {
707 case APIC_OFFSET_TPR:
708 lapic->tpr = data & 0xff;
709 vlapic_update_ppr(vlapic);
711 case APIC_OFFSET_EOI:
712 vlapic_process_eoi(vlapic);
714 case APIC_OFFSET_LDR:
716 case APIC_OFFSET_DFR:
718 case APIC_OFFSET_SVR:
721 case APIC_OFFSET_ICR_LOW:
722 if (!x2apic(vlapic)) {
724 data |= (uint64_t)lapic->icr_hi << 32;
726 retval = lapic_process_icr(vlapic, data);
728 case APIC_OFFSET_ICR_HI:
729 if (!x2apic(vlapic)) {
731 lapic->icr_hi = data;
734 case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
735 reg = vlapic_get_lvt(vlapic, offset);
736 if (!(lapic->svr & APIC_SVR_ENABLE)) {
740 // vlapic_dump_lvt(offset, reg);
742 case APIC_OFFSET_ICR:
743 lapic->icr_timer = data;
744 vlapic_start_timer(vlapic, 0);
747 case APIC_OFFSET_DCR:
748 lapic->dcr_timer = data;
749 vlapic->divisor = vlapic_timer_divisor(data);
752 case APIC_OFFSET_ESR:
753 vlapic_update_errors(vlapic);
755 case APIC_OFFSET_VER:
756 case APIC_OFFSET_APR:
757 case APIC_OFFSET_PPR:
758 case APIC_OFFSET_RRR:
759 case APIC_OFFSET_ISR0 ... APIC_OFFSET_ISR7:
760 case APIC_OFFSET_TMR0 ... APIC_OFFSET_TMR7:
761 case APIC_OFFSET_IRR0 ... APIC_OFFSET_IRR7:
762 case APIC_OFFSET_CCR:
772 vlapic_timer_tick(struct vlapic *vlapic)
774 int curticks, delta, periodic, fired;
776 uint32_t decrement, leftover;
780 delta = curticks - vlapic->ccr_ticks;
782 /* Local APIC timer is disabled */
783 if (vlapic->apic.icr_timer == 0)
786 /* One-shot mode and timer has already counted down to zero */
787 periodic = vlapic_periodic_timer(vlapic);
788 if (!periodic && vlapic->apic.ccr_timer == 0)
791 * The 'curticks' and 'ccr_ticks' are out of sync by more than
792 * 2^31 ticks. We deal with this by restarting the timer.
795 vlapic_start_timer(vlapic, 0);
800 decrement = (VLAPIC_BUS_FREQ / vlapic->divisor) / hz;
802 vlapic->ccr_ticks = curticks;
803 ccr = vlapic->apic.ccr_timer;
805 while (delta-- > 0) {
806 if (ccr > decrement) {
811 /* Trigger the local apic timer interrupt */
812 vlapic_fire_timer(vlapic);
814 leftover = decrement - ccr;
815 vlapic_start_timer(vlapic, leftover);
816 ccr = vlapic->apic.ccr_timer;
819 * One-shot timer has counted down to zero.
827 vlapic->apic.ccr_timer = ccr;
830 return ((ccr / decrement) + 1);
835 struct vdev_ops vlapic_dev_ops = {
837 .init = vlapic_op_init,
838 .reset = vlapic_op_reset,
839 .halt = vlapic_op_halt,
840 .memread = vlapic_op_mem_read,
841 .memwrite = vlapic_op_mem_write,
843 static struct io_region vlapic_mmio[VM_MAXCPU];
846 vlapic_init(struct vm *vm, int vcpuid)
848 struct vlapic *vlapic;
850 vlapic = malloc(sizeof(struct vlapic), M_VLAPIC, M_WAITOK | M_ZERO);
852 vlapic->vcpuid = vcpuid;
854 vlapic->msr_apicbase = DEFAULT_APIC_BASE | APICBASE_ENABLED;
857 vlapic->msr_apicbase |= APICBASE_BSP;
859 vlapic->ops = &vlapic_dev_ops;
861 vlapic->mmio = vlapic_mmio + vcpuid;
862 vlapic->mmio->base = DEFAULT_APIC_BASE;
863 vlapic->mmio->len = PAGE_SIZE;
864 vlapic->mmio->attr = MMIO_READ|MMIO_WRITE;
865 vlapic->mmio->vcpu = vcpuid;
867 vdev_register(&vlapic_dev_ops, vlapic);
869 vlapic_op_init(vlapic);
875 vlapic_cleanup(struct vlapic *vlapic)
877 vlapic_op_halt(vlapic);
878 vdev_unregister(vlapic);
879 free(vlapic, M_VLAPIC);
883 vlapic_get_apicbase(struct vlapic *vlapic)
886 return (vlapic->msr_apicbase);
890 vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val)
893 enum x2apic_state state;
895 err = vm_get_x2apic_state(vlapic->vm, vlapic->vcpuid, &state);
897 panic("vlapic_set_apicbase: err %d fetching x2apic state", err);
899 if (state == X2APIC_DISABLED)
900 val &= ~APICBASE_X2APIC;
902 vlapic->msr_apicbase = val;
906 vlapic_set_x2apic_state(struct vm *vm, int vcpuid, enum x2apic_state state)
908 struct vlapic *vlapic;
910 vlapic = vm_lapic(vm, vcpuid);
912 if (state == X2APIC_DISABLED)
913 vlapic->msr_apicbase &= ~APICBASE_X2APIC;