2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <machine/vmparam.h>
42 #include <machine/vmm.h>
44 #include <sys/types.h>
45 #include <sys/errno.h>
47 #include <machine/vmm.h>
53 CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
54 CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
57 /* struct vie_op.op_type */
66 /* struct vie_op.op_flags */
67 #define VIE_OP_F_IMM (1 << 0) /* immediate operand present */
68 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
70 static const struct vie_op one_byte_opcodes[256] = {
73 .op_type = VIE_OP_TYPE_MOV,
77 .op_type = VIE_OP_TYPE_MOV,
81 .op_type = VIE_OP_TYPE_MOV,
85 .op_type = VIE_OP_TYPE_MOV,
89 .op_type = VIE_OP_TYPE_MOV,
90 .op_flags = VIE_OP_F_IMM,
94 .op_type = VIE_OP_TYPE_AND,
97 /* XXX Group 1 extended opcode - not just AND */
99 .op_type = VIE_OP_TYPE_AND,
100 .op_flags = VIE_OP_F_IMM,
103 /* XXX Group 1 extended opcode - not just OR */
105 .op_type = VIE_OP_TYPE_OR,
106 .op_flags = VIE_OP_F_IMM8,
111 #define VIE_MOD_INDIRECT 0
112 #define VIE_MOD_INDIRECT_DISP8 1
113 #define VIE_MOD_INDIRECT_DISP32 2
114 #define VIE_MOD_DIRECT 3
118 #define VIE_RM_DISP32 5
120 #define GB (1024 * 1024 * 1024)
122 static enum vm_reg_name gpr_map[16] = {
141 static uint64_t size2mask[] = {
145 [8] = 0xffffffffffffffff,
149 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
153 error = vm_get_register(vm, vcpuid, reg, rval);
159 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
163 enum vm_reg_name reg;
166 reg = gpr_map[vie->reg];
169 * 64-bit mode imposes limitations on accessing legacy byte registers.
171 * The legacy high-byte registers cannot be addressed if the REX
172 * prefix is present. In this case the values 4, 5, 6 and 7 of the
173 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
175 * If the REX prefix is not present then the values 4, 5, 6 and 7
176 * of the 'ModRM:reg' field address the legacy high-byte registers,
177 * %ah, %ch, %dh and %bh respectively.
179 if (!vie->rex_present) {
180 if (vie->reg & 0x4) {
182 * Obtain the value of %ah by reading %rax and shifting
183 * right by 8 bits (same for %bh, %ch and %dh).
186 reg = gpr_map[vie->reg & 0x3];
190 error = vm_get_register(vm, vcpuid, reg, &val);
191 *rval = val >> rshift;
196 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
197 uint64_t val, int size)
205 error = vie_read_register(vm, vcpuid, reg, &origval);
208 val &= size2mask[size];
209 val |= origval & ~size2mask[size];
220 error = vm_set_register(vm, vcpuid, reg, val);
225 * The following simplifying assumptions are made during emulation:
227 * - guest is in 64-bit mode
228 * - default address size is 64-bits
229 * - default operand size is 32-bits
231 * - operand size override is not supported
233 * - address size override is not supported
236 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
237 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
240 enum vm_reg_name reg;
247 switch (vie->op.op_byte) {
250 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
252 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
255 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
257 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
261 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
262 * 89/r: mov r/m32, r32
263 * REX.W + 89/r mov r/m64, r64
267 reg = gpr_map[vie->reg];
268 error = vie_read_register(vm, vcpuid, reg, &val);
270 val &= size2mask[size];
271 error = memwrite(vm, vcpuid, gpa, val, size, arg);
277 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
279 * REX + 8A/r: mov r/m8, r8
280 * 8B/r: mov r32, r/m32
281 * REX.W 8B/r: mov r64, r/m64
283 if (vie->op.op_byte == 0x8A)
287 error = memread(vm, vcpuid, gpa, &val, size, arg);
289 reg = gpr_map[vie->reg];
290 error = vie_update_register(vm, vcpuid, reg, val, size);
295 * MOV from imm32 to mem (ModRM:r/m)
296 * C7/0 mov r/m32, imm32
297 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
299 val = vie->immediate; /* already sign-extended */
305 val &= size2mask[size];
307 error = memwrite(vm, vcpuid, gpa, val, size, arg);
317 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
318 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
321 enum vm_reg_name reg;
327 switch (vie->op.op_byte) {
330 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
333 * 23/r and r32, r/m32
334 * REX.W + 23/r and r64, r/m64
339 /* get the first operand */
340 reg = gpr_map[vie->reg];
341 error = vie_read_register(vm, vcpuid, reg, &val1);
345 /* get the second operand */
346 error = memread(vm, vcpuid, gpa, &val2, size, arg);
350 /* perform the operation and write the result */
352 error = vie_update_register(vm, vcpuid, reg, val1, size);
356 * AND mem (ModRM:r/m) with immediate and store the
359 * 81/ and r/m32, imm32
360 * REX.W + 81/ and r/m64, imm32 sign-extended to 64
362 * Currently, only the AND operation of the 0x81 opcode
363 * is implemented (ModRM:reg = b100).
365 if ((vie->reg & 7) != 4)
371 /* get the first operand */
372 error = memread(vm, vcpuid, gpa, &val1, size, arg);
377 * perform the operation with the pre-fetched immediate
378 * operand and write the result
380 val1 &= vie->immediate;
381 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
390 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
391 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
399 switch (vie->op.op_byte) {
402 * OR mem (ModRM:r/m) with immediate and store the
405 * 83/ OR r/m32, imm8 sign-extended to 32
406 * REX.W + 83/ OR r/m64, imm8 sign-extended to 64
408 * Currently, only the OR operation of the 0x83 opcode
409 * is implemented (ModRM:reg = b001).
411 if ((vie->reg & 7) != 1)
417 /* get the first operand */
418 error = memread(vm, vcpuid, gpa, &val1, size, arg);
423 * perform the operation with the pre-fetched immediate
424 * operand and write the result
426 val1 |= vie->immediate;
427 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
436 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
437 mem_region_read_t memread, mem_region_write_t memwrite,
445 switch (vie->op.op_type) {
446 case VIE_OP_TYPE_MOV:
447 error = emulate_mov(vm, vcpuid, gpa, vie,
448 memread, memwrite, memarg);
450 case VIE_OP_TYPE_AND:
451 error = emulate_and(vm, vcpuid, gpa, vie,
452 memread, memwrite, memarg);
455 error = emulate_or(vm, vcpuid, gpa, vie,
456 memread, memwrite, memarg);
468 vie_init(struct vie *vie)
471 bzero(vie, sizeof(struct vie));
473 vie->base_register = VM_REG_LAST;
474 vie->index_register = VM_REG_LAST;
478 gla2gpa(struct vm *vm, uint64_t gla, uint64_t ptpphys,
479 uint64_t *gpa, uint64_t *gpaend)
481 int nlevels, ptpshift, ptpindex;
482 uint64_t *ptpbase, pte, pgsize;
486 * XXX assumes 64-bit guest with 4 page walk levels
489 while (--nlevels >= 0) {
490 /* Zero out the lower 12 bits and the upper 12 bits */
491 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
493 ptpbase = vm_gpa_hold(vm, ptpphys, PAGE_SIZE, VM_PROT_READ,
498 ptpshift = PAGE_SHIFT + nlevels * 9;
499 ptpindex = (gla >> ptpshift) & 0x1FF;
500 pgsize = 1UL << ptpshift;
502 pte = ptpbase[ptpindex];
504 vm_gpa_release(cookie);
506 if ((pte & PG_V) == 0)
519 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
520 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
521 *gpa = pte | (gla & (pgsize - 1));
522 *gpaend = pte + pgsize;
530 vmm_fetch_instruction(struct vm *vm, int cpuid, uint64_t rip, int inst_length,
531 uint64_t cr3, struct vie *vie)
534 uint64_t gpa, gpaend, off;
538 * XXX cache previously fetched instructions using 'rip' as the tag
541 prot = VM_PROT_READ | VM_PROT_EXECUTE;
542 if (inst_length > VIE_INST_SIZE)
543 panic("vmm_fetch_instruction: invalid length %d", inst_length);
545 /* Copy the instruction into 'vie' */
546 while (vie->num_valid < inst_length) {
547 err = gla2gpa(vm, rip, cr3, &gpa, &gpaend);
551 off = gpa & PAGE_MASK;
552 n = min(inst_length - vie->num_valid, PAGE_SIZE - off);
554 if ((hpa = vm_gpa_hold(vm, gpa, n, prot, &cookie)) == NULL)
557 bcopy(hpa, &vie->inst[vie->num_valid], n);
559 vm_gpa_release(cookie);
565 if (vie->num_valid == inst_length)
572 vie_peek(struct vie *vie, uint8_t *x)
575 if (vie->num_processed < vie->num_valid) {
576 *x = vie->inst[vie->num_processed];
583 vie_advance(struct vie *vie)
586 vie->num_processed++;
590 decode_rex(struct vie *vie)
594 if (vie_peek(vie, &x))
597 if (x >= 0x40 && x <= 0x4F) {
598 vie->rex_present = 1;
600 vie->rex_w = x & 0x8 ? 1 : 0;
601 vie->rex_r = x & 0x4 ? 1 : 0;
602 vie->rex_x = x & 0x2 ? 1 : 0;
603 vie->rex_b = x & 0x1 ? 1 : 0;
612 decode_opcode(struct vie *vie)
616 if (vie_peek(vie, &x))
619 vie->op = one_byte_opcodes[x];
621 if (vie->op.op_type == VIE_OP_TYPE_NONE)
629 decode_modrm(struct vie *vie)
632 enum cpu_mode cpu_mode;
635 * XXX assuming that guest is in IA-32E 64-bit mode
637 cpu_mode = CPU_MODE_64BIT;
639 if (vie_peek(vie, &x))
642 vie->mod = (x >> 6) & 0x3;
643 vie->rm = (x >> 0) & 0x7;
644 vie->reg = (x >> 3) & 0x7;
647 * A direct addressing mode makes no sense in the context of an EPT
648 * fault. There has to be a memory access involved to cause the
651 if (vie->mod == VIE_MOD_DIRECT)
654 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
655 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
657 * Table 2-5: Special Cases of REX Encodings
659 * mod=0, r/m=5 is used in the compatibility mode to
660 * indicate a disp32 without a base register.
662 * mod!=3, r/m=4 is used in the compatibility mode to
663 * indicate that the SIB byte is present.
665 * The 'b' bit in the REX prefix is don't care in
669 vie->rm |= (vie->rex_b << 3);
672 vie->reg |= (vie->rex_r << 3);
675 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
678 vie->base_register = gpr_map[vie->rm];
681 case VIE_MOD_INDIRECT_DISP8:
684 case VIE_MOD_INDIRECT_DISP32:
687 case VIE_MOD_INDIRECT:
688 if (vie->rm == VIE_RM_DISP32) {
691 * Table 2-7. RIP-Relative Addressing
693 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
694 * whereas in compatibility mode it just implies disp32.
697 if (cpu_mode == CPU_MODE_64BIT)
698 vie->base_register = VM_REG_GUEST_RIP;
700 vie->base_register = VM_REG_LAST;
712 decode_sib(struct vie *vie)
716 /* Proceed only if SIB byte is present */
717 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
720 if (vie_peek(vie, &x))
723 /* De-construct the SIB byte */
724 vie->ss = (x >> 6) & 0x3;
725 vie->index = (x >> 3) & 0x7;
726 vie->base = (x >> 0) & 0x7;
728 /* Apply the REX prefix modifiers */
729 vie->index |= vie->rex_x << 3;
730 vie->base |= vie->rex_b << 3;
733 case VIE_MOD_INDIRECT_DISP8:
736 case VIE_MOD_INDIRECT_DISP32:
741 if (vie->mod == VIE_MOD_INDIRECT &&
742 (vie->base == 5 || vie->base == 13)) {
744 * Special case when base register is unused if mod = 0
745 * and base = %rbp or %r13.
748 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
749 * Table 2-5: Special Cases of REX Encodings
753 vie->base_register = gpr_map[vie->base];
757 * All encodings of 'index' are valid except for %rsp (4).
760 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
761 * Table 2-5: Special Cases of REX Encodings
764 vie->index_register = gpr_map[vie->index];
766 /* 'scale' makes sense only in the context of an index register */
767 if (vie->index_register < VM_REG_LAST)
768 vie->scale = 1 << vie->ss;
776 decode_displacement(struct vie *vie)
787 if ((n = vie->disp_bytes) == 0)
790 if (n != 1 && n != 4)
791 panic("decode_displacement: invalid disp_bytes %d", n);
793 for (i = 0; i < n; i++) {
794 if (vie_peek(vie, &x))
802 vie->displacement = u.signed8; /* sign-extended */
804 vie->displacement = u.signed32; /* sign-extended */
810 decode_immediate(struct vie *vie)
820 /* Figure out immediate operand size (if any) */
821 if (vie->op.op_flags & VIE_OP_F_IMM)
823 else if (vie->op.op_flags & VIE_OP_F_IMM8)
826 if ((n = vie->imm_bytes) == 0)
829 if (n != 1 && n != 4)
830 panic("decode_immediate: invalid imm_bytes %d", n);
832 for (i = 0; i < n; i++) {
833 if (vie_peek(vie, &x))
841 vie->immediate = u.signed8; /* sign-extended */
843 vie->immediate = u.signed32; /* sign-extended */
849 * Verify that all the bytes in the instruction buffer were consumed.
852 verify_inst_length(struct vie *vie)
855 if (vie->num_processed == vie->num_valid)
862 * Verify that the 'guest linear address' provided as collateral of the nested
863 * page table fault matches with our instruction decoding.
866 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
871 /* Skip 'gla' verification */
872 if (gla == VIE_INVALID_GLA)
876 if (vie->base_register != VM_REG_LAST) {
877 error = vm_get_register(vm, cpuid, vie->base_register, &base);
879 printf("verify_gla: error %d getting base reg %d\n",
880 error, vie->base_register);
885 * RIP-relative addressing starts from the following
888 if (vie->base_register == VM_REG_GUEST_RIP)
889 base += vie->num_valid;
893 if (vie->index_register != VM_REG_LAST) {
894 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
896 printf("verify_gla: error %d getting index reg %d\n",
897 error, vie->index_register);
902 if (base + vie->scale * idx + vie->displacement != gla) {
903 printf("verify_gla mismatch: "
904 "base(0x%0lx), scale(%d), index(0x%0lx), "
905 "disp(0x%0lx), gla(0x%0lx)\n",
906 base, vie->scale, idx, vie->displacement, gla);
914 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
920 if (decode_opcode(vie))
923 if (decode_modrm(vie))
929 if (decode_displacement(vie))
932 if (decode_immediate(vie))
935 if (verify_inst_length(vie))
938 if (verify_gla(vm, cpuid, gla, vie))
941 vie->decoded = 1; /* success */