2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
75 /* struct vie_op.op_flags */
76 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
77 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
78 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
79 #define VIE_OP_F_NO_MODRM (1 << 3)
81 static const struct vie_op two_byte_opcodes[256] = {
84 .op_type = VIE_OP_TYPE_MOVZX,
88 .op_type = VIE_OP_TYPE_MOVZX,
92 .op_type = VIE_OP_TYPE_MOVSX,
96 static const struct vie_op one_byte_opcodes[256] = {
99 .op_type = VIE_OP_TYPE_TWO_BYTE
103 .op_type = VIE_OP_TYPE_SUB,
107 .op_type = VIE_OP_TYPE_CMP,
111 .op_type = VIE_OP_TYPE_MOV,
115 .op_type = VIE_OP_TYPE_MOV,
119 .op_type = VIE_OP_TYPE_MOV,
123 .op_type = VIE_OP_TYPE_MOV,
127 .op_type = VIE_OP_TYPE_MOV,
128 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
132 .op_type = VIE_OP_TYPE_MOV,
133 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
136 /* XXX Group 11 extended opcode - not just MOV */
138 .op_type = VIE_OP_TYPE_MOV,
139 .op_flags = VIE_OP_F_IMM8,
143 .op_type = VIE_OP_TYPE_MOV,
144 .op_flags = VIE_OP_F_IMM,
148 .op_type = VIE_OP_TYPE_AND,
151 /* XXX Group 1 extended opcode - not just AND */
153 .op_type = VIE_OP_TYPE_AND,
154 .op_flags = VIE_OP_F_IMM,
157 /* XXX Group 1 extended opcode - not just OR */
159 .op_type = VIE_OP_TYPE_OR,
160 .op_flags = VIE_OP_F_IMM8,
163 /* XXX Group 5 extended opcode - not just PUSH */
165 .op_type = VIE_OP_TYPE_PUSH,
170 #define VIE_MOD_INDIRECT 0
171 #define VIE_MOD_INDIRECT_DISP8 1
172 #define VIE_MOD_INDIRECT_DISP32 2
173 #define VIE_MOD_DIRECT 3
177 #define VIE_RM_DISP32 5
179 #define GB (1024 * 1024 * 1024)
181 static enum vm_reg_name gpr_map[16] = {
200 static uint64_t size2mask[] = {
204 [8] = 0xffffffffffffffff,
208 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
212 error = vm_get_register(vm, vcpuid, reg, rval);
218 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
221 *reg = gpr_map[vie->reg];
224 * 64-bit mode imposes limitations on accessing legacy high byte
227 * The legacy high-byte registers cannot be addressed if the REX
228 * prefix is present. In this case the values 4, 5, 6 and 7 of the
229 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
231 * If the REX prefix is not present then the values 4, 5, 6 and 7
232 * of the 'ModRM:reg' field address the legacy high-byte registers,
233 * %ah, %ch, %dh and %bh respectively.
235 if (!vie->rex_present) {
236 if (vie->reg & 0x4) {
238 *reg = gpr_map[vie->reg & 0x3];
244 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
248 enum vm_reg_name reg;
250 vie_calc_bytereg(vie, ®, &lhbr);
251 error = vm_get_register(vm, vcpuid, reg, &val);
254 * To obtain the value of a legacy high byte register shift the
255 * base register right by 8 bits (%ah = %rax >> 8).
265 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
267 uint64_t origval, val, mask;
269 enum vm_reg_name reg;
271 vie_calc_bytereg(vie, ®, &lhbr);
272 error = vm_get_register(vm, vcpuid, reg, &origval);
278 * Shift left by 8 to store 'byte' in a legacy high
284 val |= origval & ~mask;
285 error = vm_set_register(vm, vcpuid, reg, val);
291 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
292 uint64_t val, int size)
300 error = vie_read_register(vm, vcpuid, reg, &origval);
303 val &= size2mask[size];
304 val |= origval & ~size2mask[size];
315 error = vm_set_register(vm, vcpuid, reg, val);
320 * Return the status flags that would result from doing (x - y).
323 getcc16(uint16_t x, uint16_t y)
327 __asm __volatile("sub %1,%2; pushfq; popq %0" :
328 "=r" (rflags) : "m" (y), "r" (x));
333 getcc32(uint32_t x, uint32_t y)
337 __asm __volatile("sub %1,%2; pushfq; popq %0" :
338 "=r" (rflags) : "m" (y), "r" (x));
343 getcc64(uint64_t x, uint64_t y)
347 __asm __volatile("sub %1,%2; pushfq; popq %0" :
348 "=r" (rflags) : "m" (y), "r" (x));
353 getcc(int opsize, uint64_t x, uint64_t y)
355 KASSERT(opsize == 2 || opsize == 4 || opsize == 8,
356 ("getcc: invalid operand size %d", opsize));
359 return (getcc16(x, y));
360 else if (opsize == 4)
361 return (getcc32(x, y));
363 return (getcc64(x, y));
367 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
368 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
371 enum vm_reg_name reg;
378 switch (vie->op.op_byte) {
381 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
383 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
385 size = 1; /* override for byte operation */
386 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
388 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
392 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
393 * 89/r: mov r/m16, r16
394 * 89/r: mov r/m32, r32
395 * REX.W + 89/r mov r/m64, r64
397 reg = gpr_map[vie->reg];
398 error = vie_read_register(vm, vcpuid, reg, &val);
400 val &= size2mask[size];
401 error = memwrite(vm, vcpuid, gpa, val, size, arg);
406 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
408 * REX + 8A/r: mov r8, r/m8
410 size = 1; /* override for byte operation */
411 error = memread(vm, vcpuid, gpa, &val, size, arg);
413 error = vie_write_bytereg(vm, vcpuid, vie, val);
417 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
418 * 8B/r: mov r16, r/m16
419 * 8B/r: mov r32, r/m32
420 * REX.W 8B/r: mov r64, r/m64
422 error = memread(vm, vcpuid, gpa, &val, size, arg);
424 reg = gpr_map[vie->reg];
425 error = vie_update_register(vm, vcpuid, reg, val, size);
430 * MOV from seg:moffset to AX/EAX/RAX
431 * A1: mov AX, moffs16
432 * A1: mov EAX, moffs32
433 * REX.W + A1: mov RAX, moffs64
435 error = memread(vm, vcpuid, gpa, &val, size, arg);
437 reg = VM_REG_GUEST_RAX;
438 error = vie_update_register(vm, vcpuid, reg, val, size);
443 * MOV from AX/EAX/RAX to seg:moffset
444 * A3: mov moffs16, AX
445 * A3: mov moffs32, EAX
446 * REX.W + A3: mov moffs64, RAX
448 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
450 val &= size2mask[size];
451 error = memwrite(vm, vcpuid, gpa, val, size, arg);
456 * MOV from imm8 to mem (ModRM:r/m)
457 * C6/0 mov r/m8, imm8
458 * REX + C6/0 mov r/m8, imm8
460 size = 1; /* override for byte operation */
461 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
465 * MOV from imm16/imm32 to mem (ModRM:r/m)
466 * C7/0 mov r/m16, imm16
467 * C7/0 mov r/m32, imm32
468 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
470 val = vie->immediate & size2mask[size];
471 error = memwrite(vm, vcpuid, gpa, val, size, arg);
481 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
482 mem_region_read_t memread, mem_region_write_t memwrite,
486 enum vm_reg_name reg;
492 switch (vie->op.op_byte) {
495 * MOV and zero extend byte from mem (ModRM:r/m) to
498 * 0F B6/r movzx r16, r/m8
499 * 0F B6/r movzx r32, r/m8
500 * REX.W + 0F B6/r movzx r64, r/m8
503 /* get the first operand */
504 error = memread(vm, vcpuid, gpa, &val, 1, arg);
508 /* get the second operand */
509 reg = gpr_map[vie->reg];
511 /* zero-extend byte */
514 /* write the result */
515 error = vie_update_register(vm, vcpuid, reg, val, size);
519 * MOV and zero extend word from mem (ModRM:r/m) to
522 * 0F B7/r movzx r32, r/m16
523 * REX.W + 0F B7/r movzx r64, r/m16
525 error = memread(vm, vcpuid, gpa, &val, 2, arg);
529 reg = gpr_map[vie->reg];
531 /* zero-extend word */
534 error = vie_update_register(vm, vcpuid, reg, val, size);
538 * MOV and sign extend byte from mem (ModRM:r/m) to
541 * 0F BE/r movsx r16, r/m8
542 * 0F BE/r movsx r32, r/m8
543 * REX.W + 0F BE/r movsx r64, r/m8
546 /* get the first operand */
547 error = memread(vm, vcpuid, gpa, &val, 1, arg);
551 /* get the second operand */
552 reg = gpr_map[vie->reg];
554 /* sign extend byte */
557 /* write the result */
558 error = vie_update_register(vm, vcpuid, reg, val, size);
567 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
568 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
571 enum vm_reg_name reg;
577 switch (vie->op.op_byte) {
580 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
583 * 23/r and r16, r/m16
584 * 23/r and r32, r/m32
585 * REX.W + 23/r and r64, r/m64
588 /* get the first operand */
589 reg = gpr_map[vie->reg];
590 error = vie_read_register(vm, vcpuid, reg, &val1);
594 /* get the second operand */
595 error = memread(vm, vcpuid, gpa, &val2, size, arg);
599 /* perform the operation and write the result */
601 error = vie_update_register(vm, vcpuid, reg, val1, size);
605 * AND/OR mem (ModRM:r/m) with immediate and store the
610 * 81 /i op r/m16, imm16
611 * 81 /i op r/m32, imm32
612 * REX.W + 81 /i op r/m64, imm32 sign-extended to 64
616 /* get the first operand */
617 error = memread(vm, vcpuid, gpa, &val1, size, arg);
622 * perform the operation with the pre-fetched immediate
623 * operand and write the result
625 switch (vie->reg & 7) {
627 /* modrm:reg == b100, AND */
628 val1 &= vie->immediate;
631 /* modrm:reg == b001, OR */
632 val1 |= vie->immediate;
641 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
650 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
651 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
659 switch (vie->op.op_byte) {
662 * OR mem (ModRM:r/m) with immediate and store the
665 * 83 /1 OR r/m16, imm8 sign-extended to 16
666 * 83 /1 OR r/m32, imm8 sign-extended to 32
667 * REX.W + 83/1 OR r/m64, imm8 sign-extended to 64
669 * Currently, only the OR operation of the 0x83 opcode
670 * is implemented (ModRM:reg = b001).
672 if ((vie->reg & 7) != 1)
675 /* get the first operand */
676 error = memread(vm, vcpuid, gpa, &val1, size, arg);
681 * perform the operation with the pre-fetched immediate
682 * operand and write the result
684 val1 |= vie->immediate;
685 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
693 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
696 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
697 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
700 uint64_t op1, op2, rflags, rflags2;
701 enum vm_reg_name reg;
704 switch (vie->op.op_byte) {
707 * 3B/r CMP r16, r/m16
708 * 3B/r CMP r32, r/m32
709 * REX.W + 3B/r CMP r64, r/m64
711 * Compare first operand (reg) with second operand (r/m) and
712 * set status flags in EFLAGS register. The comparison is
713 * performed by subtracting the second operand from the first
714 * operand and then setting the status flags.
717 /* Get the first operand */
718 reg = gpr_map[vie->reg];
719 error = vie_read_register(vm, vcpuid, reg, &op1);
723 /* Get the second operand */
724 error = memread(vm, vcpuid, gpa, &op2, size, arg);
732 rflags2 = getcc(size, op1, op2);
733 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
736 rflags &= ~RFLAGS_STATUS_BITS;
737 rflags |= rflags2 & RFLAGS_STATUS_BITS;
739 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
744 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
745 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
748 uint64_t nval, rflags, rflags2, val1, val2;
749 enum vm_reg_name reg;
754 switch (vie->op.op_byte) {
757 * SUB r/m from r and store the result in r
759 * 2B/r SUB r16, r/m16
760 * 2B/r SUB r32, r/m32
761 * REX.W + 2B/r SUB r64, r/m64
764 /* get the first operand */
765 reg = gpr_map[vie->reg];
766 error = vie_read_register(vm, vcpuid, reg, &val1);
770 /* get the second operand */
771 error = memread(vm, vcpuid, gpa, &val2, size, arg);
775 /* perform the operation and write the result */
777 error = vie_update_register(vm, vcpuid, reg, nval, size);
784 rflags2 = getcc(size, val1, val2);
785 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
790 rflags &= ~RFLAGS_STATUS_BITS;
791 rflags |= rflags2 & RFLAGS_STATUS_BITS;
792 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
800 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
801 struct vm_guest_paging *paging, mem_region_read_t memread,
802 mem_region_write_t memwrite, void *arg)
805 struct vm_copyinfo copyinfo[2];
807 struct iovec copyinfo[2];
809 struct seg_desc ss_desc;
810 uint64_t cr0, rflags, rsp, stack_gla, val;
811 int error, size, stackaddrsize;
814 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
816 * PUSH is part of the group 5 extended opcodes and is identified
817 * by ModRM:reg = b110.
819 if ((vie->reg & 7) != 6)
824 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
826 if (paging->cpu_mode == CPU_MODE_REAL) {
828 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
830 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
831 * - Stack pointer size is always 64-bits.
832 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
833 * - 16-bit PUSH/POP is supported by using the operand size
834 * override prefix (66H).
837 size = vie->opsize_override ? 2 : 8;
840 * In protected or compability mode the 'B' flag in the
841 * stack-segment descriptor determines the size of the
844 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
845 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
847 if (SEG_DESC_DEF32(ss_desc.access))
853 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
854 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
856 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
857 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
859 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
860 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
863 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
864 rsp, size, stackaddrsize, PROT_WRITE, &stack_gla)) {
865 vm_inject_ss(vm, vcpuid, 0);
869 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
870 vm_inject_ss(vm, vcpuid, 0);
874 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
875 vm_inject_ac(vm, vcpuid, 0);
879 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size, PROT_WRITE,
880 copyinfo, nitems(copyinfo));
883 * XXX cannot return a negative error value here because it
884 * ends up being the return value of the VM_RUN() ioctl and
885 * is interpreted as a pseudo-error (for e.g. ERESTART).
888 } else if (error == 1) {
889 /* Resume guest execution to handle page fault */
893 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
895 vm_copyout(vm, vcpuid, &val, copyinfo, size);
896 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
898 KASSERT(error == 0, ("error %d updating rsp", error));
901 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
907 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
908 struct vm_guest_paging *paging, mem_region_read_t memread,
909 mem_region_write_t memwrite, void *memarg)
916 switch (vie->op.op_type) {
917 case VIE_OP_TYPE_PUSH:
918 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
921 case VIE_OP_TYPE_CMP:
922 error = emulate_cmp(vm, vcpuid, gpa, vie,
923 memread, memwrite, memarg);
925 case VIE_OP_TYPE_MOV:
926 error = emulate_mov(vm, vcpuid, gpa, vie,
927 memread, memwrite, memarg);
929 case VIE_OP_TYPE_MOVSX:
930 case VIE_OP_TYPE_MOVZX:
931 error = emulate_movx(vm, vcpuid, gpa, vie,
932 memread, memwrite, memarg);
934 case VIE_OP_TYPE_AND:
935 error = emulate_and(vm, vcpuid, gpa, vie,
936 memread, memwrite, memarg);
939 error = emulate_or(vm, vcpuid, gpa, vie,
940 memread, memwrite, memarg);
942 case VIE_OP_TYPE_SUB:
943 error = emulate_sub(vm, vcpuid, gpa, vie,
944 memread, memwrite, memarg);
955 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
957 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
958 ("%s: invalid size %d", __func__, size));
959 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
961 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
964 return ((gla & (size - 1)) ? 1 : 0);
968 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
972 if (cpu_mode != CPU_MODE_64BIT)
976 * The value of the bit 47 in the 'gla' should be replicated in the
977 * most significant 16 bits.
979 mask = ~((1UL << 48) - 1);
980 if (gla & (1UL << 47))
981 return ((gla & mask) != mask);
983 return ((gla & mask) != 0);
987 vie_size2mask(int size)
989 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
990 ("vie_size2mask: invalid size %d", size));
991 return (size2mask[size]);
995 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
996 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
997 int prot, uint64_t *gla)
999 uint64_t firstoff, low_limit, high_limit, segbase;
1002 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1003 ("%s: invalid segment %d", __func__, seg));
1004 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1005 ("%s: invalid operand size %d", __func__, length));
1006 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1007 ("%s: invalid prot %#x", __func__, prot));
1010 if (cpu_mode == CPU_MODE_64BIT) {
1011 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1012 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1015 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1016 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1019 * If the segment selector is loaded with a NULL selector
1020 * then the descriptor is unusable and attempting to use
1021 * it results in a #GP(0).
1023 if (SEG_DESC_UNUSABLE(desc->access))
1027 * The processor generates a #NP exception when a segment
1028 * register is loaded with a selector that points to a
1029 * descriptor that is not present. If this was the case then
1030 * it would have been checked before the VM-exit.
1032 KASSERT(SEG_DESC_PRESENT(desc->access),
1033 ("segment %d not present: %#x", seg, desc->access));
1036 * The descriptor type must indicate a code/data segment.
1038 type = SEG_DESC_TYPE(desc->access);
1039 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1040 "descriptor type %#x", seg, type));
1042 if (prot & PROT_READ) {
1043 /* #GP on a read access to a exec-only code segment */
1044 if ((type & 0xA) == 0x8)
1048 if (prot & PROT_WRITE) {
1050 * #GP on a write access to a code segment or a
1051 * read-only data segment.
1053 if (type & 0x8) /* code segment */
1056 if ((type & 0xA) == 0) /* read-only data seg */
1061 * 'desc->limit' is fully expanded taking granularity into
1064 if ((type & 0xC) == 0x4) {
1065 /* expand-down data segment */
1066 low_limit = desc->limit + 1;
1067 high_limit = SEG_DESC_DEF32(desc->access) ?
1068 0xffffffff : 0xffff;
1070 /* code segment or expand-up data segment */
1072 high_limit = desc->limit;
1075 while (length > 0) {
1076 offset &= vie_size2mask(addrsize);
1077 if (offset < low_limit || offset > high_limit)
1085 * In 64-bit mode all segments except %fs and %gs have a segment
1086 * base address of 0.
1088 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1089 seg != VM_REG_GUEST_GS) {
1092 segbase = desc->base;
1096 * Truncate 'firstoff' to the effective address size before adding
1097 * it to the segment base.
1099 firstoff &= vie_size2mask(addrsize);
1100 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1106 vie_init(struct vie *vie)
1109 bzero(vie, sizeof(struct vie));
1111 vie->base_register = VM_REG_LAST;
1112 vie->index_register = VM_REG_LAST;
1116 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1121 error_code |= PGEX_P;
1122 if (prot & VM_PROT_WRITE)
1123 error_code |= PGEX_W;
1125 error_code |= PGEX_U;
1127 error_code |= PGEX_RSV;
1128 if (prot & VM_PROT_EXECUTE)
1129 error_code |= PGEX_I;
1131 return (error_code);
1135 ptp_release(void **cookie)
1137 if (*cookie != NULL) {
1138 vm_gpa_release(*cookie);
1144 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1148 ptp_release(cookie);
1149 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1154 vmm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1155 uint64_t gla, int prot, uint64_t *gpa)
1157 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1159 uint64_t *ptpbase, ptpphys, pte, pgsize;
1160 uint32_t *ptpbase32, pte32;
1163 usermode = (paging->cpl == 3 ? 1 : 0);
1164 writable = prot & VM_PROT_WRITE;
1169 ptpphys = paging->cr3; /* root of the page tables */
1170 ptp_release(&cookie);
1174 if (vie_canonical_check(paging->cpu_mode, gla)) {
1176 * XXX assuming a non-stack reference otherwise a stack fault
1177 * should be generated.
1179 vm_inject_gp(vm, vcpuid);
1183 if (paging->paging_mode == PAGING_MODE_FLAT) {
1188 if (paging->paging_mode == PAGING_MODE_32) {
1190 while (--nlevels >= 0) {
1191 /* Zero out the lower 12 bits. */
1194 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1196 if (ptpbase32 == NULL)
1199 ptpshift = PAGE_SHIFT + nlevels * 10;
1200 ptpindex = (gla >> ptpshift) & 0x3FF;
1201 pgsize = 1UL << ptpshift;
1203 pte32 = ptpbase32[ptpindex];
1205 if ((pte32 & PG_V) == 0 ||
1206 (usermode && (pte32 & PG_U) == 0) ||
1207 (writable && (pte32 & PG_RW) == 0)) {
1208 pfcode = pf_error_code(usermode, prot, 0,
1210 vm_inject_pf(vm, vcpuid, pfcode, gla);
1215 * Emulate the x86 MMU's management of the accessed
1216 * and dirty flags. While the accessed flag is set
1217 * at every level of the page table, the dirty flag
1218 * is only set at the last level providing the guest
1221 if ((pte32 & PG_A) == 0) {
1222 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1223 pte32, pte32 | PG_A) == 0) {
1228 /* XXX must be ignored if CR4.PSE=0 */
1229 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1235 /* Set the dirty bit in the page table entry if necessary */
1236 if (writable && (pte32 & PG_M) == 0) {
1237 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1238 pte32, pte32 | PG_M) == 0) {
1243 /* Zero out the lower 'ptpshift' bits */
1244 pte32 >>= ptpshift; pte32 <<= ptpshift;
1245 *gpa = pte32 | (gla & (pgsize - 1));
1249 if (paging->paging_mode == PAGING_MODE_PAE) {
1250 /* Zero out the lower 5 bits and the upper 32 bits */
1251 ptpphys &= 0xffffffe0UL;
1253 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1254 if (ptpbase == NULL)
1257 ptpindex = (gla >> 30) & 0x3;
1259 pte = ptpbase[ptpindex];
1261 if ((pte & PG_V) == 0) {
1262 pfcode = pf_error_code(usermode, prot, 0, pte);
1263 vm_inject_pf(vm, vcpuid, pfcode, gla);
1272 while (--nlevels >= 0) {
1273 /* Zero out the lower 12 bits and the upper 12 bits */
1274 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1276 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1277 if (ptpbase == NULL)
1280 ptpshift = PAGE_SHIFT + nlevels * 9;
1281 ptpindex = (gla >> ptpshift) & 0x1FF;
1282 pgsize = 1UL << ptpshift;
1284 pte = ptpbase[ptpindex];
1286 if ((pte & PG_V) == 0 ||
1287 (usermode && (pte & PG_U) == 0) ||
1288 (writable && (pte & PG_RW) == 0)) {
1289 pfcode = pf_error_code(usermode, prot, 0, pte);
1290 vm_inject_pf(vm, vcpuid, pfcode, gla);
1294 /* Set the accessed bit in the page table entry */
1295 if ((pte & PG_A) == 0) {
1296 if (atomic_cmpset_64(&ptpbase[ptpindex],
1297 pte, pte | PG_A) == 0) {
1302 if (nlevels > 0 && (pte & PG_PS) != 0) {
1303 if (pgsize > 1 * GB) {
1304 pfcode = pf_error_code(usermode, prot, 1, pte);
1305 vm_inject_pf(vm, vcpuid, pfcode, gla);
1314 /* Set the dirty bit in the page table entry if necessary */
1315 if (writable && (pte & PG_M) == 0) {
1316 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1320 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1321 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1322 *gpa = pte | (gla & (pgsize - 1));
1324 ptp_release(&cookie);
1335 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1336 uint64_t rip, int inst_length, struct vie *vie)
1338 struct vm_copyinfo copyinfo[2];
1341 if (inst_length > VIE_INST_SIZE)
1342 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1344 prot = PROT_READ | PROT_EXEC;
1345 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1346 copyinfo, nitems(copyinfo));
1348 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1349 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1350 vie->num_valid = inst_length;
1356 vie_peek(struct vie *vie, uint8_t *x)
1359 if (vie->num_processed < vie->num_valid) {
1360 *x = vie->inst[vie->num_processed];
1367 vie_advance(struct vie *vie)
1370 vie->num_processed++;
1374 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1379 if (vie_peek(vie, &x))
1383 vie->opsize_override = 1;
1385 vie->addrsize_override = 1;
1393 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1394 * - Only one REX prefix is allowed per instruction.
1395 * - The REX prefix must immediately precede the opcode byte or the
1396 * escape opcode byte.
1397 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1398 * the mandatory prefix must come before the REX prefix.
1400 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1401 vie->rex_present = 1;
1402 vie->rex_w = x & 0x8 ? 1 : 0;
1403 vie->rex_r = x & 0x4 ? 1 : 0;
1404 vie->rex_x = x & 0x2 ? 1 : 0;
1405 vie->rex_b = x & 0x1 ? 1 : 0;
1410 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1412 if (cpu_mode == CPU_MODE_64BIT) {
1414 * Default address size is 64-bits and default operand size
1417 vie->addrsize = vie->addrsize_override ? 4 : 8;
1420 else if (vie->opsize_override)
1425 /* Default address and operand sizes are 32-bits */
1426 vie->addrsize = vie->addrsize_override ? 2 : 4;
1427 vie->opsize = vie->opsize_override ? 2 : 4;
1429 /* Default address and operand sizes are 16-bits */
1430 vie->addrsize = vie->addrsize_override ? 4 : 2;
1431 vie->opsize = vie->opsize_override ? 4 : 2;
1437 decode_two_byte_opcode(struct vie *vie)
1441 if (vie_peek(vie, &x))
1444 vie->op = two_byte_opcodes[x];
1446 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1454 decode_opcode(struct vie *vie)
1458 if (vie_peek(vie, &x))
1461 vie->op = one_byte_opcodes[x];
1463 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1468 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
1469 return (decode_two_byte_opcode(vie));
1475 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
1479 if (cpu_mode == CPU_MODE_REAL)
1482 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
1485 if (vie_peek(vie, &x))
1488 vie->mod = (x >> 6) & 0x3;
1489 vie->rm = (x >> 0) & 0x7;
1490 vie->reg = (x >> 3) & 0x7;
1493 * A direct addressing mode makes no sense in the context of an EPT
1494 * fault. There has to be a memory access involved to cause the
1497 if (vie->mod == VIE_MOD_DIRECT)
1500 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
1501 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
1503 * Table 2-5: Special Cases of REX Encodings
1505 * mod=0, r/m=5 is used in the compatibility mode to
1506 * indicate a disp32 without a base register.
1508 * mod!=3, r/m=4 is used in the compatibility mode to
1509 * indicate that the SIB byte is present.
1511 * The 'b' bit in the REX prefix is don't care in
1515 vie->rm |= (vie->rex_b << 3);
1518 vie->reg |= (vie->rex_r << 3);
1521 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
1524 vie->base_register = gpr_map[vie->rm];
1527 case VIE_MOD_INDIRECT_DISP8:
1528 vie->disp_bytes = 1;
1530 case VIE_MOD_INDIRECT_DISP32:
1531 vie->disp_bytes = 4;
1533 case VIE_MOD_INDIRECT:
1534 if (vie->rm == VIE_RM_DISP32) {
1535 vie->disp_bytes = 4;
1537 * Table 2-7. RIP-Relative Addressing
1539 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
1540 * whereas in compatibility mode it just implies disp32.
1543 if (cpu_mode == CPU_MODE_64BIT)
1544 vie->base_register = VM_REG_GUEST_RIP;
1546 vie->base_register = VM_REG_LAST;
1558 decode_sib(struct vie *vie)
1562 /* Proceed only if SIB byte is present */
1563 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
1566 if (vie_peek(vie, &x))
1569 /* De-construct the SIB byte */
1570 vie->ss = (x >> 6) & 0x3;
1571 vie->index = (x >> 3) & 0x7;
1572 vie->base = (x >> 0) & 0x7;
1574 /* Apply the REX prefix modifiers */
1575 vie->index |= vie->rex_x << 3;
1576 vie->base |= vie->rex_b << 3;
1579 case VIE_MOD_INDIRECT_DISP8:
1580 vie->disp_bytes = 1;
1582 case VIE_MOD_INDIRECT_DISP32:
1583 vie->disp_bytes = 4;
1587 if (vie->mod == VIE_MOD_INDIRECT &&
1588 (vie->base == 5 || vie->base == 13)) {
1590 * Special case when base register is unused if mod = 0
1591 * and base = %rbp or %r13.
1594 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1595 * Table 2-5: Special Cases of REX Encodings
1597 vie->disp_bytes = 4;
1599 vie->base_register = gpr_map[vie->base];
1603 * All encodings of 'index' are valid except for %rsp (4).
1606 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1607 * Table 2-5: Special Cases of REX Encodings
1609 if (vie->index != 4)
1610 vie->index_register = gpr_map[vie->index];
1612 /* 'scale' makes sense only in the context of an index register */
1613 if (vie->index_register < VM_REG_LAST)
1614 vie->scale = 1 << vie->ss;
1622 decode_displacement(struct vie *vie)
1633 if ((n = vie->disp_bytes) == 0)
1636 if (n != 1 && n != 4)
1637 panic("decode_displacement: invalid disp_bytes %d", n);
1639 for (i = 0; i < n; i++) {
1640 if (vie_peek(vie, &x))
1648 vie->displacement = u.signed8; /* sign-extended */
1650 vie->displacement = u.signed32; /* sign-extended */
1656 decode_immediate(struct vie *vie)
1667 /* Figure out immediate operand size (if any) */
1668 if (vie->op.op_flags & VIE_OP_F_IMM) {
1670 * Section 2.2.1.5 "Immediates", Intel SDM:
1671 * In 64-bit mode the typical size of immediate operands
1672 * remains 32-bits. When the operand size if 64-bits, the
1673 * processor sign-extends all immediates to 64-bits prior
1676 if (vie->opsize == 4 || vie->opsize == 8)
1680 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
1684 if ((n = vie->imm_bytes) == 0)
1687 KASSERT(n == 1 || n == 2 || n == 4,
1688 ("%s: invalid number of immediate bytes: %d", __func__, n));
1690 for (i = 0; i < n; i++) {
1691 if (vie_peek(vie, &x))
1698 /* sign-extend the immediate value before use */
1700 vie->immediate = u.signed8;
1702 vie->immediate = u.signed16;
1704 vie->immediate = u.signed32;
1710 decode_moffset(struct vie *vie)
1719 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
1723 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
1724 * The memory offset size follows the address-size of the instruction.
1727 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
1730 for (i = 0; i < n; i++) {
1731 if (vie_peek(vie, &x))
1737 vie->displacement = u.u64;
1742 * Verify that all the bytes in the instruction buffer were consumed.
1745 verify_inst_length(struct vie *vie)
1748 if (vie->num_processed == vie->num_valid)
1755 * Verify that the 'guest linear address' provided as collateral of the nested
1756 * page table fault matches with our instruction decoding.
1759 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
1762 uint64_t base, idx, gla2;
1764 /* Skip 'gla' verification */
1765 if (gla == VIE_INVALID_GLA)
1769 if (vie->base_register != VM_REG_LAST) {
1770 error = vm_get_register(vm, cpuid, vie->base_register, &base);
1772 printf("verify_gla: error %d getting base reg %d\n",
1773 error, vie->base_register);
1778 * RIP-relative addressing starts from the following
1781 if (vie->base_register == VM_REG_GUEST_RIP)
1782 base += vie->num_valid;
1786 if (vie->index_register != VM_REG_LAST) {
1787 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
1789 printf("verify_gla: error %d getting index reg %d\n",
1790 error, vie->index_register);
1795 /* XXX assuming that the base address of the segment is 0 */
1796 gla2 = base + vie->scale * idx + vie->displacement;
1797 gla2 &= size2mask[vie->addrsize];
1799 printf("verify_gla mismatch: "
1800 "base(0x%0lx), scale(%d), index(0x%0lx), "
1801 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
1802 base, vie->scale, idx, vie->displacement, gla, gla2);
1810 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
1811 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
1814 if (decode_prefixes(vie, cpu_mode, cs_d))
1817 if (decode_opcode(vie))
1820 if (decode_modrm(vie, cpu_mode))
1823 if (decode_sib(vie))
1826 if (decode_displacement(vie))
1829 if (decode_immediate(vie))
1832 if (decode_moffset(vie))
1835 if (verify_inst_length(vie))
1838 if (verify_gla(vm, cpuid, gla, vie))
1841 vie->decoded = 1; /* success */
1845 #endif /* _KERNEL */