2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
42 #include <machine/vmparam.h>
43 #include <machine/vmm.h>
45 #include <sys/types.h>
46 #include <sys/errno.h>
47 #include <sys/_iovec.h>
49 #include <machine/vmm.h>
53 #define KASSERT(exp,msg) assert((exp))
56 #include <machine/vmm_instruction_emul.h>
58 #include <x86/specialreg.h>
60 /* struct vie_op.op_type */
77 /* struct vie_op.op_flags */
78 #define VIE_OP_F_IMM (1 << 0) /* 16/32-bit immediate operand */
79 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
80 #define VIE_OP_F_MOFFSET (1 << 2) /* 16/32/64-bit immediate moffset */
81 #define VIE_OP_F_NO_MODRM (1 << 3)
82 #define VIE_OP_F_NO_GLA_VERIFICATION (1 << 4)
84 static const struct vie_op two_byte_opcodes[256] = {
87 .op_type = VIE_OP_TYPE_MOVZX,
91 .op_type = VIE_OP_TYPE_MOVZX,
95 .op_type = VIE_OP_TYPE_MOVSX,
99 static const struct vie_op one_byte_opcodes[256] = {
102 .op_type = VIE_OP_TYPE_TWO_BYTE
106 .op_type = VIE_OP_TYPE_SUB,
110 .op_type = VIE_OP_TYPE_CMP,
114 .op_type = VIE_OP_TYPE_MOV,
118 .op_type = VIE_OP_TYPE_MOV,
122 .op_type = VIE_OP_TYPE_MOV,
126 .op_type = VIE_OP_TYPE_MOV,
130 .op_type = VIE_OP_TYPE_MOV,
131 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
135 .op_type = VIE_OP_TYPE_MOV,
136 .op_flags = VIE_OP_F_MOFFSET | VIE_OP_F_NO_MODRM,
140 .op_type = VIE_OP_TYPE_MOVS,
141 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
145 .op_type = VIE_OP_TYPE_MOVS,
146 .op_flags = VIE_OP_F_NO_MODRM | VIE_OP_F_NO_GLA_VERIFICATION
149 /* XXX Group 11 extended opcode - not just MOV */
151 .op_type = VIE_OP_TYPE_MOV,
152 .op_flags = VIE_OP_F_IMM8,
156 .op_type = VIE_OP_TYPE_MOV,
157 .op_flags = VIE_OP_F_IMM,
161 .op_type = VIE_OP_TYPE_AND,
164 /* XXX Group 1 extended opcode - not just AND */
166 .op_type = VIE_OP_TYPE_AND,
167 .op_flags = VIE_OP_F_IMM,
170 /* XXX Group 1 extended opcode - not just OR */
172 .op_type = VIE_OP_TYPE_OR,
173 .op_flags = VIE_OP_F_IMM8,
176 /* XXX Group 1A extended opcode - not just POP */
178 .op_type = VIE_OP_TYPE_POP,
181 /* XXX Group 5 extended opcode - not just PUSH */
183 .op_type = VIE_OP_TYPE_PUSH,
188 #define VIE_MOD_INDIRECT 0
189 #define VIE_MOD_INDIRECT_DISP8 1
190 #define VIE_MOD_INDIRECT_DISP32 2
191 #define VIE_MOD_DIRECT 3
195 #define VIE_RM_DISP32 5
197 #define GB (1024 * 1024 * 1024)
199 static enum vm_reg_name gpr_map[16] = {
218 static uint64_t size2mask[] = {
222 [8] = 0xffffffffffffffff,
226 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
230 error = vm_get_register(vm, vcpuid, reg, rval);
236 vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
239 *reg = gpr_map[vie->reg];
242 * 64-bit mode imposes limitations on accessing legacy high byte
245 * The legacy high-byte registers cannot be addressed if the REX
246 * prefix is present. In this case the values 4, 5, 6 and 7 of the
247 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
249 * If the REX prefix is not present then the values 4, 5, 6 and 7
250 * of the 'ModRM:reg' field address the legacy high-byte registers,
251 * %ah, %ch, %dh and %bh respectively.
253 if (!vie->rex_present) {
254 if (vie->reg & 0x4) {
256 *reg = gpr_map[vie->reg & 0x3];
262 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
266 enum vm_reg_name reg;
268 vie_calc_bytereg(vie, ®, &lhbr);
269 error = vm_get_register(vm, vcpuid, reg, &val);
272 * To obtain the value of a legacy high byte register shift the
273 * base register right by 8 bits (%ah = %rax >> 8).
283 vie_write_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t byte)
285 uint64_t origval, val, mask;
287 enum vm_reg_name reg;
289 vie_calc_bytereg(vie, ®, &lhbr);
290 error = vm_get_register(vm, vcpuid, reg, &origval);
296 * Shift left by 8 to store 'byte' in a legacy high
302 val |= origval & ~mask;
303 error = vm_set_register(vm, vcpuid, reg, val);
309 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
310 uint64_t val, int size)
318 error = vie_read_register(vm, vcpuid, reg, &origval);
321 val &= size2mask[size];
322 val |= origval & ~size2mask[size];
333 error = vm_set_register(vm, vcpuid, reg, val);
337 #define RFLAGS_STATUS_BITS (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_V)
340 * Return the status flags that would result from doing (x - y).
344 getcc##sz(uint##sz##_t x, uint##sz##_t y) \
348 __asm __volatile("sub %2,%1; pushfq; popq %0" : \
349 "=r" (rflags), "+r" (x) : "m" (y)); \
359 getcc(int opsize, uint64_t x, uint64_t y)
361 KASSERT(opsize == 1 || opsize == 2 || opsize == 4 || opsize == 8,
362 ("getcc: invalid operand size %d", opsize));
365 return (getcc8(x, y));
366 else if (opsize == 2)
367 return (getcc16(x, y));
368 else if (opsize == 4)
369 return (getcc32(x, y));
371 return (getcc64(x, y));
375 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
376 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
379 enum vm_reg_name reg;
386 switch (vie->op.op_byte) {
389 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
391 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
393 size = 1; /* override for byte operation */
394 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
396 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
400 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
401 * 89/r: mov r/m16, r16
402 * 89/r: mov r/m32, r32
403 * REX.W + 89/r mov r/m64, r64
405 reg = gpr_map[vie->reg];
406 error = vie_read_register(vm, vcpuid, reg, &val);
408 val &= size2mask[size];
409 error = memwrite(vm, vcpuid, gpa, val, size, arg);
414 * MOV byte from mem (ModRM:r/m) to reg (ModRM:reg)
416 * REX + 8A/r: mov r8, r/m8
418 size = 1; /* override for byte operation */
419 error = memread(vm, vcpuid, gpa, &val, size, arg);
421 error = vie_write_bytereg(vm, vcpuid, vie, val);
425 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
426 * 8B/r: mov r16, r/m16
427 * 8B/r: mov r32, r/m32
428 * REX.W 8B/r: mov r64, r/m64
430 error = memread(vm, vcpuid, gpa, &val, size, arg);
432 reg = gpr_map[vie->reg];
433 error = vie_update_register(vm, vcpuid, reg, val, size);
438 * MOV from seg:moffset to AX/EAX/RAX
439 * A1: mov AX, moffs16
440 * A1: mov EAX, moffs32
441 * REX.W + A1: mov RAX, moffs64
443 error = memread(vm, vcpuid, gpa, &val, size, arg);
445 reg = VM_REG_GUEST_RAX;
446 error = vie_update_register(vm, vcpuid, reg, val, size);
451 * MOV from AX/EAX/RAX to seg:moffset
452 * A3: mov moffs16, AX
453 * A3: mov moffs32, EAX
454 * REX.W + A3: mov moffs64, RAX
456 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RAX, &val);
458 val &= size2mask[size];
459 error = memwrite(vm, vcpuid, gpa, val, size, arg);
464 * MOV from imm8 to mem (ModRM:r/m)
465 * C6/0 mov r/m8, imm8
466 * REX + C6/0 mov r/m8, imm8
468 size = 1; /* override for byte operation */
469 error = memwrite(vm, vcpuid, gpa, vie->immediate, size, arg);
473 * MOV from imm16/imm32 to mem (ModRM:r/m)
474 * C7/0 mov r/m16, imm16
475 * C7/0 mov r/m32, imm32
476 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
478 val = vie->immediate & size2mask[size];
479 error = memwrite(vm, vcpuid, gpa, val, size, arg);
489 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
490 mem_region_read_t memread, mem_region_write_t memwrite,
494 enum vm_reg_name reg;
500 switch (vie->op.op_byte) {
503 * MOV and zero extend byte from mem (ModRM:r/m) to
506 * 0F B6/r movzx r16, r/m8
507 * 0F B6/r movzx r32, r/m8
508 * REX.W + 0F B6/r movzx r64, r/m8
511 /* get the first operand */
512 error = memread(vm, vcpuid, gpa, &val, 1, arg);
516 /* get the second operand */
517 reg = gpr_map[vie->reg];
519 /* zero-extend byte */
522 /* write the result */
523 error = vie_update_register(vm, vcpuid, reg, val, size);
527 * MOV and zero extend word from mem (ModRM:r/m) to
530 * 0F B7/r movzx r32, r/m16
531 * REX.W + 0F B7/r movzx r64, r/m16
533 error = memread(vm, vcpuid, gpa, &val, 2, arg);
537 reg = gpr_map[vie->reg];
539 /* zero-extend word */
542 error = vie_update_register(vm, vcpuid, reg, val, size);
546 * MOV and sign extend byte from mem (ModRM:r/m) to
549 * 0F BE/r movsx r16, r/m8
550 * 0F BE/r movsx r32, r/m8
551 * REX.W + 0F BE/r movsx r64, r/m8
554 /* get the first operand */
555 error = memread(vm, vcpuid, gpa, &val, 1, arg);
559 /* get the second operand */
560 reg = gpr_map[vie->reg];
562 /* sign extend byte */
565 /* write the result */
566 error = vie_update_register(vm, vcpuid, reg, val, size);
575 * Helper function to calculate and validate a linear address.
577 * Returns 0 on success and 1 if an exception was injected into the guest.
580 get_gla(void *vm, int vcpuid, struct vie *vie, struct vm_guest_paging *paging,
581 int opsize, int addrsize, int prot, enum vm_reg_name seg,
582 enum vm_reg_name gpr, uint64_t *gla)
584 struct seg_desc desc;
585 uint64_t cr0, val, rflags;
588 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
589 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
591 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
592 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
594 error = vm_get_seg_desc(vm, vcpuid, seg, &desc);
595 KASSERT(error == 0, ("%s: error %d getting segment descriptor %d",
596 __func__, error, seg));
598 error = vie_read_register(vm, vcpuid, gpr, &val);
599 KASSERT(error == 0, ("%s: error %d getting register %d", __func__,
602 if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
603 addrsize, prot, gla)) {
604 if (seg == VM_REG_GUEST_SS)
605 vm_inject_ss(vm, vcpuid, 0);
607 vm_inject_gp(vm, vcpuid);
611 if (vie_canonical_check(paging->cpu_mode, *gla)) {
612 if (seg == VM_REG_GUEST_SS)
613 vm_inject_ss(vm, vcpuid, 0);
615 vm_inject_gp(vm, vcpuid);
619 if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
620 vm_inject_ac(vm, vcpuid, 0);
628 emulate_movs(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
629 struct vm_guest_paging *paging, mem_region_read_t memread,
630 mem_region_write_t memwrite, void *arg)
633 struct vm_copyinfo copyinfo[2];
635 struct iovec copyinfo[2];
637 uint64_t dstaddr, srcaddr, val;
638 uint64_t rcx, rdi, rsi, rflags;
639 int error, opsize, seg, repeat;
641 opsize = (vie->op.op_byte == 0xA4) ? 1 : vie->opsize;
646 * XXX although the MOVS instruction is only supposed to be used with
647 * the "rep" prefix some guests like FreeBSD will use "repnz" instead.
649 * Empirically the "repnz" prefix has identical behavior to "rep"
650 * and the zero flag does not make a difference.
652 repeat = vie->repz_present | vie->repnz_present;
655 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RCX, &rcx);
656 KASSERT(!error, ("%s: error %d getting rcx", __func__, error));
659 * The count register is %rcx, %ecx or %cx depending on the
660 * address size of the instruction.
662 if ((rcx & vie_size2mask(vie->addrsize)) == 0)
667 * Source Destination Comments
668 * --------------------------------------------
669 * (1) memory memory n/a
670 * (2) memory mmio emulated
671 * (3) mmio memory emulated
672 * (4) mmio mmio not emulated
674 * At this point we don't have sufficient information to distinguish
675 * between (2), (3) and (4). We use 'vm_copy_setup()' to tease this
676 * out because it will succeed only when operating on regular memory.
678 * XXX the emulation doesn't properly handle the case where 'gpa'
679 * is straddling the boundary between the normal memory and MMIO.
682 seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
683 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
684 PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr);
688 error = vm_copy_setup(vm, vcpuid, paging, srcaddr, opsize, PROT_READ,
689 copyinfo, nitems(copyinfo));
692 * case (2): read from system memory and write to mmio.
694 vm_copyin(vm, vcpuid, copyinfo, &val, opsize);
695 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
696 error = memwrite(vm, vcpuid, gpa, val, opsize, arg);
698 } else if (error > 0) {
700 * Resume guest execution to handle fault.
705 * 'vm_copy_setup()' is expected to fail for cases (3) and (4)
706 * if 'srcaddr' is in the mmio space.
710 error = get_gla(vm, vcpuid, vie, paging, opsize, vie->addrsize,
711 PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr);
715 error = vm_copy_setup(vm, vcpuid, paging, dstaddr, opsize,
716 PROT_WRITE, copyinfo, nitems(copyinfo));
719 * case (3): read from MMIO and write to system memory.
721 * A MMIO read can have side-effects so we commit to it
722 * only after vm_copy_setup() is successful. If a page-fault
723 * needs to be injected into the guest then it will happen
724 * before the MMIO read is attempted.
726 error = memread(vm, vcpuid, gpa, &val, opsize, arg);
730 vm_copyout(vm, vcpuid, &val, copyinfo, opsize);
731 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
732 } else if (error > 0) {
734 * Resume guest execution to handle fault.
741 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSI, &rsi);
742 KASSERT(error == 0, ("%s: error %d getting rsi", __func__, error));
744 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RDI, &rdi);
745 KASSERT(error == 0, ("%s: error %d getting rdi", __func__, error));
747 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
748 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
750 if (rflags & PSL_D) {
758 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSI, rsi,
760 KASSERT(error == 0, ("%s: error %d updating rsi", __func__, error));
762 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RDI, rdi,
764 KASSERT(error == 0, ("%s: error %d updating rdi", __func__, error));
768 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RCX,
770 KASSERT(!error, ("%s: error %d updating rcx", __func__, error));
773 * Repeat the instruction if the count register is not zero.
775 if ((rcx & vie_size2mask(vie->addrsize)) != 0)
776 vm_restart_instruction(vm, vcpuid);
786 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
787 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
790 enum vm_reg_name reg;
791 uint64_t result, rflags, rflags2, val1, val2;
796 switch (vie->op.op_byte) {
799 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
802 * 23/r and r16, r/m16
803 * 23/r and r32, r/m32
804 * REX.W + 23/r and r64, r/m64
807 /* get the first operand */
808 reg = gpr_map[vie->reg];
809 error = vie_read_register(vm, vcpuid, reg, &val1);
813 /* get the second operand */
814 error = memread(vm, vcpuid, gpa, &val2, size, arg);
818 /* perform the operation and write the result */
819 result = val1 & val2;
820 error = vie_update_register(vm, vcpuid, reg, result, size);
824 * AND/OR mem (ModRM:r/m) with immediate and store the
829 * 81 /i op r/m16, imm16
830 * 81 /i op r/m32, imm32
831 * REX.W + 81 /i op r/m64, imm32 sign-extended to 64
835 /* get the first operand */
836 error = memread(vm, vcpuid, gpa, &val1, size, arg);
841 * perform the operation with the pre-fetched immediate
842 * operand and write the result
844 switch (vie->reg & 7) {
846 /* modrm:reg == b100, AND */
847 result = val1 & vie->immediate;
850 /* modrm:reg == b001, OR */
851 result = val1 | vie->immediate;
860 error = memwrite(vm, vcpuid, gpa, result, size, arg);
868 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
873 * OF and CF are cleared; the SF, ZF and PF flags are set according
874 * to the result; AF is undefined.
876 * The updated status flags are obtained by subtracting 0 from 'result'.
878 rflags2 = getcc(size, result, 0);
879 rflags &= ~RFLAGS_STATUS_BITS;
880 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
882 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
887 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
888 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
891 uint64_t val1, result, rflags, rflags2;
896 switch (vie->op.op_byte) {
899 * OR mem (ModRM:r/m) with immediate and store the
902 * 83 /1 OR r/m16, imm8 sign-extended to 16
903 * 83 /1 OR r/m32, imm8 sign-extended to 32
904 * REX.W + 83/1 OR r/m64, imm8 sign-extended to 64
906 * Currently, only the OR operation of the 0x83 opcode
907 * is implemented (ModRM:reg = b001).
909 if ((vie->reg & 7) != 1)
912 /* get the first operand */
913 error = memread(vm, vcpuid, gpa, &val1, size, arg);
918 * perform the operation with the pre-fetched immediate
919 * operand and write the result
921 result = val1 | vie->immediate;
922 error = memwrite(vm, vcpuid, gpa, result, size, arg);
930 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
935 * OF and CF are cleared; the SF, ZF and PF flags are set according
936 * to the result; AF is undefined.
938 * The updated status flags are obtained by subtracting 0 from 'result'.
940 rflags2 = getcc(size, result, 0);
941 rflags &= ~RFLAGS_STATUS_BITS;
942 rflags |= rflags2 & (PSL_PF | PSL_Z | PSL_N);
944 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
949 emulate_cmp(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
950 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
953 uint64_t op1, op2, rflags, rflags2;
954 enum vm_reg_name reg;
957 switch (vie->op.op_byte) {
960 * 3B/r CMP r16, r/m16
961 * 3B/r CMP r32, r/m32
962 * REX.W + 3B/r CMP r64, r/m64
964 * Compare first operand (reg) with second operand (r/m) and
965 * set status flags in EFLAGS register. The comparison is
966 * performed by subtracting the second operand from the first
967 * operand and then setting the status flags.
970 /* Get the first operand */
971 reg = gpr_map[vie->reg];
972 error = vie_read_register(vm, vcpuid, reg, &op1);
976 /* Get the second operand */
977 error = memread(vm, vcpuid, gpa, &op2, size, arg);
985 rflags2 = getcc(size, op1, op2);
986 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
989 rflags &= ~RFLAGS_STATUS_BITS;
990 rflags |= rflags2 & RFLAGS_STATUS_BITS;
992 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, rflags, 8);
997 emulate_sub(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
998 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
1001 uint64_t nval, rflags, rflags2, val1, val2;
1002 enum vm_reg_name reg;
1007 switch (vie->op.op_byte) {
1010 * SUB r/m from r and store the result in r
1012 * 2B/r SUB r16, r/m16
1013 * 2B/r SUB r32, r/m32
1014 * REX.W + 2B/r SUB r64, r/m64
1017 /* get the first operand */
1018 reg = gpr_map[vie->reg];
1019 error = vie_read_register(vm, vcpuid, reg, &val1);
1023 /* get the second operand */
1024 error = memread(vm, vcpuid, gpa, &val2, size, arg);
1028 /* perform the operation and write the result */
1030 error = vie_update_register(vm, vcpuid, reg, nval, size);
1037 rflags2 = getcc(size, val1, val2);
1038 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1043 rflags &= ~RFLAGS_STATUS_BITS;
1044 rflags |= rflags2 & RFLAGS_STATUS_BITS;
1045 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RFLAGS,
1053 emulate_stack_op(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1054 struct vm_guest_paging *paging, mem_region_read_t memread,
1055 mem_region_write_t memwrite, void *arg)
1058 struct vm_copyinfo copyinfo[2];
1060 struct iovec copyinfo[2];
1062 struct seg_desc ss_desc;
1063 uint64_t cr0, rflags, rsp, stack_gla, val;
1064 int error, size, stackaddrsize, pushop;
1068 pushop = (vie->op.op_type == VIE_OP_TYPE_PUSH) ? 1 : 0;
1071 * From "Address-Size Attributes for Stack Accesses", Intel SDL, Vol 1
1073 if (paging->cpu_mode == CPU_MODE_REAL) {
1075 } else if (paging->cpu_mode == CPU_MODE_64BIT) {
1077 * "Stack Manipulation Instructions in 64-bit Mode", SDM, Vol 3
1078 * - Stack pointer size is always 64-bits.
1079 * - PUSH/POP of 32-bit values is not possible in 64-bit mode.
1080 * - 16-bit PUSH/POP is supported by using the operand size
1081 * override prefix (66H).
1084 size = vie->opsize_override ? 2 : 8;
1087 * In protected or compability mode the 'B' flag in the
1088 * stack-segment descriptor determines the size of the
1091 error = vm_get_seg_desc(vm, vcpuid, VM_REG_GUEST_SS, &ss_desc);
1092 KASSERT(error == 0, ("%s: error %d getting SS descriptor",
1094 if (SEG_DESC_DEF32(ss_desc.access))
1100 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_CR0, &cr0);
1101 KASSERT(error == 0, ("%s: error %d getting cr0", __func__, error));
1103 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RFLAGS, &rflags);
1104 KASSERT(error == 0, ("%s: error %d getting rflags", __func__, error));
1106 error = vie_read_register(vm, vcpuid, VM_REG_GUEST_RSP, &rsp);
1107 KASSERT(error == 0, ("%s: error %d getting rsp", __func__, error));
1112 if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
1113 rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
1115 vm_inject_ss(vm, vcpuid, 0);
1119 if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
1120 vm_inject_ss(vm, vcpuid, 0);
1124 if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
1125 vm_inject_ac(vm, vcpuid, 0);
1129 error = vm_copy_setup(vm, vcpuid, paging, stack_gla, size,
1130 pushop ? PROT_WRITE : PROT_READ, copyinfo, nitems(copyinfo));
1133 * XXX cannot return a negative error value here because it
1134 * ends up being the return value of the VM_RUN() ioctl and
1135 * is interpreted as a pseudo-error (for e.g. ERESTART).
1138 } else if (error == 1) {
1139 /* Resume guest execution to handle page fault */
1144 error = memread(vm, vcpuid, mmio_gpa, &val, size, arg);
1146 vm_copyout(vm, vcpuid, &val, copyinfo, size);
1148 vm_copyin(vm, vcpuid, copyinfo, &val, size);
1149 error = memwrite(vm, vcpuid, mmio_gpa, val, size, arg);
1152 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1155 error = vie_update_register(vm, vcpuid, VM_REG_GUEST_RSP, rsp,
1157 KASSERT(error == 0, ("error %d updating rsp", error));
1163 emulate_push(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1164 struct vm_guest_paging *paging, mem_region_read_t memread,
1165 mem_region_write_t memwrite, void *arg)
1170 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1172 * PUSH is part of the group 5 extended opcodes and is identified
1173 * by ModRM:reg = b110.
1175 if ((vie->reg & 7) != 6)
1178 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1184 emulate_pop(void *vm, int vcpuid, uint64_t mmio_gpa, struct vie *vie,
1185 struct vm_guest_paging *paging, mem_region_read_t memread,
1186 mem_region_write_t memwrite, void *arg)
1191 * Table A-6, "Opcode Extensions", Intel SDM, Vol 2.
1193 * POP is part of the group 1A extended opcodes and is identified
1194 * by ModRM:reg = b000.
1196 if ((vie->reg & 7) != 0)
1199 error = emulate_stack_op(vm, vcpuid, mmio_gpa, vie, paging, memread,
1205 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
1206 struct vm_guest_paging *paging, mem_region_read_t memread,
1207 mem_region_write_t memwrite, void *memarg)
1214 switch (vie->op.op_type) {
1215 case VIE_OP_TYPE_POP:
1216 error = emulate_pop(vm, vcpuid, gpa, vie, paging, memread,
1219 case VIE_OP_TYPE_PUSH:
1220 error = emulate_push(vm, vcpuid, gpa, vie, paging, memread,
1223 case VIE_OP_TYPE_CMP:
1224 error = emulate_cmp(vm, vcpuid, gpa, vie,
1225 memread, memwrite, memarg);
1227 case VIE_OP_TYPE_MOV:
1228 error = emulate_mov(vm, vcpuid, gpa, vie,
1229 memread, memwrite, memarg);
1231 case VIE_OP_TYPE_MOVSX:
1232 case VIE_OP_TYPE_MOVZX:
1233 error = emulate_movx(vm, vcpuid, gpa, vie,
1234 memread, memwrite, memarg);
1236 case VIE_OP_TYPE_MOVS:
1237 error = emulate_movs(vm, vcpuid, gpa, vie, paging, memread,
1240 case VIE_OP_TYPE_AND:
1241 error = emulate_and(vm, vcpuid, gpa, vie,
1242 memread, memwrite, memarg);
1244 case VIE_OP_TYPE_OR:
1245 error = emulate_or(vm, vcpuid, gpa, vie,
1246 memread, memwrite, memarg);
1248 case VIE_OP_TYPE_SUB:
1249 error = emulate_sub(vm, vcpuid, gpa, vie,
1250 memread, memwrite, memarg);
1261 vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
1263 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1264 ("%s: invalid size %d", __func__, size));
1265 KASSERT(cpl >= 0 && cpl <= 3, ("%s: invalid cpl %d", __func__, cpl));
1267 if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
1270 return ((gla & (size - 1)) ? 1 : 0);
1274 vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
1278 if (cpu_mode != CPU_MODE_64BIT)
1282 * The value of the bit 47 in the 'gla' should be replicated in the
1283 * most significant 16 bits.
1285 mask = ~((1UL << 48) - 1);
1286 if (gla & (1UL << 47))
1287 return ((gla & mask) != mask);
1289 return ((gla & mask) != 0);
1293 vie_size2mask(int size)
1295 KASSERT(size == 1 || size == 2 || size == 4 || size == 8,
1296 ("vie_size2mask: invalid size %d", size));
1297 return (size2mask[size]);
1301 vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
1302 struct seg_desc *desc, uint64_t offset, int length, int addrsize,
1303 int prot, uint64_t *gla)
1305 uint64_t firstoff, low_limit, high_limit, segbase;
1308 KASSERT(seg >= VM_REG_GUEST_ES && seg <= VM_REG_GUEST_GS,
1309 ("%s: invalid segment %d", __func__, seg));
1310 KASSERT(length == 1 || length == 2 || length == 4 || length == 8,
1311 ("%s: invalid operand size %d", __func__, length));
1312 KASSERT((prot & ~(PROT_READ | PROT_WRITE)) == 0,
1313 ("%s: invalid prot %#x", __func__, prot));
1316 if (cpu_mode == CPU_MODE_64BIT) {
1317 KASSERT(addrsize == 4 || addrsize == 8, ("%s: invalid address "
1318 "size %d for cpu_mode %d", __func__, addrsize, cpu_mode));
1321 KASSERT(addrsize == 2 || addrsize == 4, ("%s: invalid address "
1322 "size %d for cpu mode %d", __func__, addrsize, cpu_mode));
1325 * If the segment selector is loaded with a NULL selector
1326 * then the descriptor is unusable and attempting to use
1327 * it results in a #GP(0).
1329 if (SEG_DESC_UNUSABLE(desc->access))
1333 * The processor generates a #NP exception when a segment
1334 * register is loaded with a selector that points to a
1335 * descriptor that is not present. If this was the case then
1336 * it would have been checked before the VM-exit.
1338 KASSERT(SEG_DESC_PRESENT(desc->access),
1339 ("segment %d not present: %#x", seg, desc->access));
1342 * The descriptor type must indicate a code/data segment.
1344 type = SEG_DESC_TYPE(desc->access);
1345 KASSERT(type >= 16 && type <= 31, ("segment %d has invalid "
1346 "descriptor type %#x", seg, type));
1348 if (prot & PROT_READ) {
1349 /* #GP on a read access to a exec-only code segment */
1350 if ((type & 0xA) == 0x8)
1354 if (prot & PROT_WRITE) {
1356 * #GP on a write access to a code segment or a
1357 * read-only data segment.
1359 if (type & 0x8) /* code segment */
1362 if ((type & 0xA) == 0) /* read-only data seg */
1367 * 'desc->limit' is fully expanded taking granularity into
1370 if ((type & 0xC) == 0x4) {
1371 /* expand-down data segment */
1372 low_limit = desc->limit + 1;
1373 high_limit = SEG_DESC_DEF32(desc->access) ?
1374 0xffffffff : 0xffff;
1376 /* code segment or expand-up data segment */
1378 high_limit = desc->limit;
1381 while (length > 0) {
1382 offset &= vie_size2mask(addrsize);
1383 if (offset < low_limit || offset > high_limit)
1391 * In 64-bit mode all segments except %fs and %gs have a segment
1392 * base address of 0.
1394 if (cpu_mode == CPU_MODE_64BIT && seg != VM_REG_GUEST_FS &&
1395 seg != VM_REG_GUEST_GS) {
1398 segbase = desc->base;
1402 * Truncate 'firstoff' to the effective address size before adding
1403 * it to the segment base.
1405 firstoff &= vie_size2mask(addrsize);
1406 *gla = (segbase + firstoff) & vie_size2mask(glasize);
1412 vie_init(struct vie *vie, const char *inst_bytes, int inst_length)
1414 KASSERT(inst_length >= 0 && inst_length <= VIE_INST_SIZE,
1415 ("%s: invalid instruction length (%d)", __func__, inst_length));
1417 bzero(vie, sizeof(struct vie));
1419 vie->base_register = VM_REG_LAST;
1420 vie->index_register = VM_REG_LAST;
1421 vie->segment_register = VM_REG_LAST;
1424 bcopy(inst_bytes, vie->inst, inst_length);
1425 vie->num_valid = inst_length;
1430 pf_error_code(int usermode, int prot, int rsvd, uint64_t pte)
1435 error_code |= PGEX_P;
1436 if (prot & VM_PROT_WRITE)
1437 error_code |= PGEX_W;
1439 error_code |= PGEX_U;
1441 error_code |= PGEX_RSV;
1442 if (prot & VM_PROT_EXECUTE)
1443 error_code |= PGEX_I;
1445 return (error_code);
1449 ptp_release(void **cookie)
1451 if (*cookie != NULL) {
1452 vm_gpa_release(*cookie);
1458 ptp_hold(struct vm *vm, vm_paddr_t ptpphys, size_t len, void **cookie)
1462 ptp_release(cookie);
1463 ptr = vm_gpa_hold(vm, ptpphys, len, VM_PROT_RW, cookie);
1468 vmm_gla2gpa(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1469 uint64_t gla, int prot, uint64_t *gpa)
1471 int nlevels, pfcode, ptpshift, ptpindex, retval, usermode, writable;
1473 uint64_t *ptpbase, ptpphys, pte, pgsize;
1474 uint32_t *ptpbase32, pte32;
1477 usermode = (paging->cpl == 3 ? 1 : 0);
1478 writable = prot & VM_PROT_WRITE;
1483 ptpphys = paging->cr3; /* root of the page tables */
1484 ptp_release(&cookie);
1488 if (vie_canonical_check(paging->cpu_mode, gla)) {
1490 * XXX assuming a non-stack reference otherwise a stack fault
1491 * should be generated.
1493 vm_inject_gp(vm, vcpuid);
1497 if (paging->paging_mode == PAGING_MODE_FLAT) {
1502 if (paging->paging_mode == PAGING_MODE_32) {
1504 while (--nlevels >= 0) {
1505 /* Zero out the lower 12 bits. */
1508 ptpbase32 = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1510 if (ptpbase32 == NULL)
1513 ptpshift = PAGE_SHIFT + nlevels * 10;
1514 ptpindex = (gla >> ptpshift) & 0x3FF;
1515 pgsize = 1UL << ptpshift;
1517 pte32 = ptpbase32[ptpindex];
1519 if ((pte32 & PG_V) == 0 ||
1520 (usermode && (pte32 & PG_U) == 0) ||
1521 (writable && (pte32 & PG_RW) == 0)) {
1522 pfcode = pf_error_code(usermode, prot, 0,
1524 vm_inject_pf(vm, vcpuid, pfcode, gla);
1529 * Emulate the x86 MMU's management of the accessed
1530 * and dirty flags. While the accessed flag is set
1531 * at every level of the page table, the dirty flag
1532 * is only set at the last level providing the guest
1535 if ((pte32 & PG_A) == 0) {
1536 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1537 pte32, pte32 | PG_A) == 0) {
1542 /* XXX must be ignored if CR4.PSE=0 */
1543 if (nlevels > 0 && (pte32 & PG_PS) != 0)
1549 /* Set the dirty bit in the page table entry if necessary */
1550 if (writable && (pte32 & PG_M) == 0) {
1551 if (atomic_cmpset_32(&ptpbase32[ptpindex],
1552 pte32, pte32 | PG_M) == 0) {
1557 /* Zero out the lower 'ptpshift' bits */
1558 pte32 >>= ptpshift; pte32 <<= ptpshift;
1559 *gpa = pte32 | (gla & (pgsize - 1));
1563 if (paging->paging_mode == PAGING_MODE_PAE) {
1564 /* Zero out the lower 5 bits and the upper 32 bits */
1565 ptpphys &= 0xffffffe0UL;
1567 ptpbase = ptp_hold(vm, ptpphys, sizeof(*ptpbase) * 4, &cookie);
1568 if (ptpbase == NULL)
1571 ptpindex = (gla >> 30) & 0x3;
1573 pte = ptpbase[ptpindex];
1575 if ((pte & PG_V) == 0) {
1576 pfcode = pf_error_code(usermode, prot, 0, pte);
1577 vm_inject_pf(vm, vcpuid, pfcode, gla);
1586 while (--nlevels >= 0) {
1587 /* Zero out the lower 12 bits and the upper 12 bits */
1588 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
1590 ptpbase = ptp_hold(vm, ptpphys, PAGE_SIZE, &cookie);
1591 if (ptpbase == NULL)
1594 ptpshift = PAGE_SHIFT + nlevels * 9;
1595 ptpindex = (gla >> ptpshift) & 0x1FF;
1596 pgsize = 1UL << ptpshift;
1598 pte = ptpbase[ptpindex];
1600 if ((pte & PG_V) == 0 ||
1601 (usermode && (pte & PG_U) == 0) ||
1602 (writable && (pte & PG_RW) == 0)) {
1603 pfcode = pf_error_code(usermode, prot, 0, pte);
1604 vm_inject_pf(vm, vcpuid, pfcode, gla);
1608 /* Set the accessed bit in the page table entry */
1609 if ((pte & PG_A) == 0) {
1610 if (atomic_cmpset_64(&ptpbase[ptpindex],
1611 pte, pte | PG_A) == 0) {
1616 if (nlevels > 0 && (pte & PG_PS) != 0) {
1617 if (pgsize > 1 * GB) {
1618 pfcode = pf_error_code(usermode, prot, 1, pte);
1619 vm_inject_pf(vm, vcpuid, pfcode, gla);
1628 /* Set the dirty bit in the page table entry if necessary */
1629 if (writable && (pte & PG_M) == 0) {
1630 if (atomic_cmpset_64(&ptpbase[ptpindex], pte, pte | PG_M) == 0)
1634 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
1635 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
1636 *gpa = pte | (gla & (pgsize - 1));
1638 ptp_release(&cookie);
1649 vmm_fetch_instruction(struct vm *vm, int vcpuid, struct vm_guest_paging *paging,
1650 uint64_t rip, int inst_length, struct vie *vie)
1652 struct vm_copyinfo copyinfo[2];
1655 if (inst_length > VIE_INST_SIZE)
1656 panic("vmm_fetch_instruction: invalid length %d", inst_length);
1658 prot = PROT_READ | PROT_EXEC;
1659 error = vm_copy_setup(vm, vcpuid, paging, rip, inst_length, prot,
1660 copyinfo, nitems(copyinfo));
1662 vm_copyin(vm, vcpuid, copyinfo, vie->inst, inst_length);
1663 vm_copy_teardown(vm, vcpuid, copyinfo, nitems(copyinfo));
1664 vie->num_valid = inst_length;
1670 vie_peek(struct vie *vie, uint8_t *x)
1673 if (vie->num_processed < vie->num_valid) {
1674 *x = vie->inst[vie->num_processed];
1681 vie_advance(struct vie *vie)
1684 vie->num_processed++;
1688 segment_override(uint8_t x, int *seg)
1693 *seg = VM_REG_GUEST_CS;
1696 *seg = VM_REG_GUEST_SS;
1699 *seg = VM_REG_GUEST_DS;
1702 *seg = VM_REG_GUEST_ES;
1705 *seg = VM_REG_GUEST_FS;
1708 *seg = VM_REG_GUEST_GS;
1717 decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
1722 if (vie_peek(vie, &x))
1726 vie->opsize_override = 1;
1728 vie->addrsize_override = 1;
1730 vie->repz_present = 1;
1732 vie->repnz_present = 1;
1733 else if (segment_override(x, &vie->segment_register))
1734 vie->segment_override = 1;
1742 * From section 2.2.1, "REX Prefixes", Intel SDM Vol 2:
1743 * - Only one REX prefix is allowed per instruction.
1744 * - The REX prefix must immediately precede the opcode byte or the
1745 * escape opcode byte.
1746 * - If an instruction has a mandatory prefix (0x66, 0xF2 or 0xF3)
1747 * the mandatory prefix must come before the REX prefix.
1749 if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
1750 vie->rex_present = 1;
1751 vie->rex_w = x & 0x8 ? 1 : 0;
1752 vie->rex_r = x & 0x4 ? 1 : 0;
1753 vie->rex_x = x & 0x2 ? 1 : 0;
1754 vie->rex_b = x & 0x1 ? 1 : 0;
1759 * Section "Operand-Size And Address-Size Attributes", Intel SDM, Vol 1
1761 if (cpu_mode == CPU_MODE_64BIT) {
1763 * Default address size is 64-bits and default operand size
1766 vie->addrsize = vie->addrsize_override ? 4 : 8;
1769 else if (vie->opsize_override)
1774 /* Default address and operand sizes are 32-bits */
1775 vie->addrsize = vie->addrsize_override ? 2 : 4;
1776 vie->opsize = vie->opsize_override ? 2 : 4;
1778 /* Default address and operand sizes are 16-bits */
1779 vie->addrsize = vie->addrsize_override ? 4 : 2;
1780 vie->opsize = vie->opsize_override ? 4 : 2;
1786 decode_two_byte_opcode(struct vie *vie)
1790 if (vie_peek(vie, &x))
1793 vie->op = two_byte_opcodes[x];
1795 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1803 decode_opcode(struct vie *vie)
1807 if (vie_peek(vie, &x))
1810 vie->op = one_byte_opcodes[x];
1812 if (vie->op.op_type == VIE_OP_TYPE_NONE)
1817 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
1818 return (decode_two_byte_opcode(vie));
1824 decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
1828 if (cpu_mode == CPU_MODE_REAL)
1831 if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
1834 if (vie_peek(vie, &x))
1837 vie->mod = (x >> 6) & 0x3;
1838 vie->rm = (x >> 0) & 0x7;
1839 vie->reg = (x >> 3) & 0x7;
1842 * A direct addressing mode makes no sense in the context of an EPT
1843 * fault. There has to be a memory access involved to cause the
1846 if (vie->mod == VIE_MOD_DIRECT)
1849 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
1850 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
1852 * Table 2-5: Special Cases of REX Encodings
1854 * mod=0, r/m=5 is used in the compatibility mode to
1855 * indicate a disp32 without a base register.
1857 * mod!=3, r/m=4 is used in the compatibility mode to
1858 * indicate that the SIB byte is present.
1860 * The 'b' bit in the REX prefix is don't care in
1864 vie->rm |= (vie->rex_b << 3);
1867 vie->reg |= (vie->rex_r << 3);
1870 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
1873 vie->base_register = gpr_map[vie->rm];
1876 case VIE_MOD_INDIRECT_DISP8:
1877 vie->disp_bytes = 1;
1879 case VIE_MOD_INDIRECT_DISP32:
1880 vie->disp_bytes = 4;
1882 case VIE_MOD_INDIRECT:
1883 if (vie->rm == VIE_RM_DISP32) {
1884 vie->disp_bytes = 4;
1886 * Table 2-7. RIP-Relative Addressing
1888 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
1889 * whereas in compatibility mode it just implies disp32.
1892 if (cpu_mode == CPU_MODE_64BIT)
1893 vie->base_register = VM_REG_GUEST_RIP;
1895 vie->base_register = VM_REG_LAST;
1907 decode_sib(struct vie *vie)
1911 /* Proceed only if SIB byte is present */
1912 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
1915 if (vie_peek(vie, &x))
1918 /* De-construct the SIB byte */
1919 vie->ss = (x >> 6) & 0x3;
1920 vie->index = (x >> 3) & 0x7;
1921 vie->base = (x >> 0) & 0x7;
1923 /* Apply the REX prefix modifiers */
1924 vie->index |= vie->rex_x << 3;
1925 vie->base |= vie->rex_b << 3;
1928 case VIE_MOD_INDIRECT_DISP8:
1929 vie->disp_bytes = 1;
1931 case VIE_MOD_INDIRECT_DISP32:
1932 vie->disp_bytes = 4;
1936 if (vie->mod == VIE_MOD_INDIRECT &&
1937 (vie->base == 5 || vie->base == 13)) {
1939 * Special case when base register is unused if mod = 0
1940 * and base = %rbp or %r13.
1943 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1944 * Table 2-5: Special Cases of REX Encodings
1946 vie->disp_bytes = 4;
1948 vie->base_register = gpr_map[vie->base];
1952 * All encodings of 'index' are valid except for %rsp (4).
1955 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
1956 * Table 2-5: Special Cases of REX Encodings
1958 if (vie->index != 4)
1959 vie->index_register = gpr_map[vie->index];
1961 /* 'scale' makes sense only in the context of an index register */
1962 if (vie->index_register < VM_REG_LAST)
1963 vie->scale = 1 << vie->ss;
1971 decode_displacement(struct vie *vie)
1982 if ((n = vie->disp_bytes) == 0)
1985 if (n != 1 && n != 4)
1986 panic("decode_displacement: invalid disp_bytes %d", n);
1988 for (i = 0; i < n; i++) {
1989 if (vie_peek(vie, &x))
1997 vie->displacement = u.signed8; /* sign-extended */
1999 vie->displacement = u.signed32; /* sign-extended */
2005 decode_immediate(struct vie *vie)
2016 /* Figure out immediate operand size (if any) */
2017 if (vie->op.op_flags & VIE_OP_F_IMM) {
2019 * Section 2.2.1.5 "Immediates", Intel SDM:
2020 * In 64-bit mode the typical size of immediate operands
2021 * remains 32-bits. When the operand size if 64-bits, the
2022 * processor sign-extends all immediates to 64-bits prior
2025 if (vie->opsize == 4 || vie->opsize == 8)
2029 } else if (vie->op.op_flags & VIE_OP_F_IMM8) {
2033 if ((n = vie->imm_bytes) == 0)
2036 KASSERT(n == 1 || n == 2 || n == 4,
2037 ("%s: invalid number of immediate bytes: %d", __func__, n));
2039 for (i = 0; i < n; i++) {
2040 if (vie_peek(vie, &x))
2047 /* sign-extend the immediate value before use */
2049 vie->immediate = u.signed8;
2051 vie->immediate = u.signed16;
2053 vie->immediate = u.signed32;
2059 decode_moffset(struct vie *vie)
2068 if ((vie->op.op_flags & VIE_OP_F_MOFFSET) == 0)
2072 * Section 2.2.1.4, "Direct Memory-Offset MOVs", Intel SDM:
2073 * The memory offset size follows the address-size of the instruction.
2076 KASSERT(n == 2 || n == 4 || n == 8, ("invalid moffset bytes: %d", n));
2079 for (i = 0; i < n; i++) {
2080 if (vie_peek(vie, &x))
2086 vie->displacement = u.u64;
2091 * Verify that all the bytes in the instruction buffer were consumed.
2094 verify_inst_length(struct vie *vie)
2097 if (vie->num_processed)
2104 * Verify that the 'guest linear address' provided as collateral of the nested
2105 * page table fault matches with our instruction decoding.
2108 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
2111 uint64_t base, idx, gla2;
2113 /* Skip 'gla' verification */
2114 if (gla == VIE_INVALID_GLA)
2118 if (vie->base_register != VM_REG_LAST) {
2119 error = vm_get_register(vm, cpuid, vie->base_register, &base);
2121 printf("verify_gla: error %d getting base reg %d\n",
2122 error, vie->base_register);
2127 * RIP-relative addressing starts from the following
2130 if (vie->base_register == VM_REG_GUEST_RIP)
2131 base += vie->num_valid;
2135 if (vie->index_register != VM_REG_LAST) {
2136 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
2138 printf("verify_gla: error %d getting index reg %d\n",
2139 error, vie->index_register);
2144 /* XXX assuming that the base address of the segment is 0 */
2145 gla2 = base + vie->scale * idx + vie->displacement;
2146 gla2 &= size2mask[vie->addrsize];
2148 printf("verify_gla mismatch: "
2149 "base(0x%0lx), scale(%d), index(0x%0lx), "
2150 "disp(0x%0lx), gla(0x%0lx), gla2(0x%0lx)\n",
2151 base, vie->scale, idx, vie->displacement, gla, gla2);
2159 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla,
2160 enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
2163 if (decode_prefixes(vie, cpu_mode, cs_d))
2166 if (decode_opcode(vie))
2169 if (decode_modrm(vie, cpu_mode))
2172 if (decode_sib(vie))
2175 if (decode_displacement(vie))
2178 if (decode_immediate(vie))
2181 if (decode_moffset(vie))
2184 if (verify_inst_length(vie))
2187 if ((vie->op.op_flags & VIE_OP_F_NO_GLA_VERIFICATION) == 0) {
2188 if (verify_gla(vm, cpuid, gla, vie))
2192 vie->decoded = 1; /* success */
2196 #endif /* _KERNEL */