2 * Copyright (c) 2012 Sandvine, Inc.
3 * Copyright (c) 2012 NetApp, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/systm.h>
41 #include <machine/vmparam.h>
42 #include <machine/vmm.h>
44 #include <sys/types.h>
45 #include <sys/errno.h>
47 #include <machine/vmm.h>
53 CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
54 CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
57 /* struct vie_op.op_type */
69 /* struct vie_op.op_flags */
70 #define VIE_OP_F_IMM (1 << 0) /* immediate operand present */
71 #define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
73 static const struct vie_op two_byte_opcodes[256] = {
76 .op_type = VIE_OP_TYPE_MOVZX,
80 .op_type = VIE_OP_TYPE_MOVSX,
84 static const struct vie_op one_byte_opcodes[256] = {
87 .op_type = VIE_OP_TYPE_TWO_BYTE
91 .op_type = VIE_OP_TYPE_MOV,
95 .op_type = VIE_OP_TYPE_MOV,
99 .op_type = VIE_OP_TYPE_MOV,
103 .op_type = VIE_OP_TYPE_MOV,
107 .op_type = VIE_OP_TYPE_MOV,
108 .op_flags = VIE_OP_F_IMM,
112 .op_type = VIE_OP_TYPE_AND,
115 /* XXX Group 1 extended opcode - not just AND */
117 .op_type = VIE_OP_TYPE_AND,
118 .op_flags = VIE_OP_F_IMM,
121 /* XXX Group 1 extended opcode - not just OR */
123 .op_type = VIE_OP_TYPE_OR,
124 .op_flags = VIE_OP_F_IMM8,
129 #define VIE_MOD_INDIRECT 0
130 #define VIE_MOD_INDIRECT_DISP8 1
131 #define VIE_MOD_INDIRECT_DISP32 2
132 #define VIE_MOD_DIRECT 3
136 #define VIE_RM_DISP32 5
138 #define GB (1024 * 1024 * 1024)
140 static enum vm_reg_name gpr_map[16] = {
159 static uint64_t size2mask[] = {
163 [8] = 0xffffffffffffffff,
167 vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
171 error = vm_get_register(vm, vcpuid, reg, rval);
177 vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
181 enum vm_reg_name reg;
184 reg = gpr_map[vie->reg];
187 * 64-bit mode imposes limitations on accessing legacy byte registers.
189 * The legacy high-byte registers cannot be addressed if the REX
190 * prefix is present. In this case the values 4, 5, 6 and 7 of the
191 * 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
193 * If the REX prefix is not present then the values 4, 5, 6 and 7
194 * of the 'ModRM:reg' field address the legacy high-byte registers,
195 * %ah, %ch, %dh and %bh respectively.
197 if (!vie->rex_present) {
198 if (vie->reg & 0x4) {
200 * Obtain the value of %ah by reading %rax and shifting
201 * right by 8 bits (same for %bh, %ch and %dh).
204 reg = gpr_map[vie->reg & 0x3];
208 error = vm_get_register(vm, vcpuid, reg, &val);
209 *rval = val >> rshift;
214 vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
215 uint64_t val, int size)
223 error = vie_read_register(vm, vcpuid, reg, &origval);
226 val &= size2mask[size];
227 val |= origval & ~size2mask[size];
238 error = vm_set_register(vm, vcpuid, reg, val);
243 * The following simplifying assumptions are made during emulation:
245 * - guest is in 64-bit mode
246 * - default address size is 64-bits
247 * - default operand size is 32-bits
249 * - operand size override is not supported
251 * - address size override is not supported
254 emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
255 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
258 enum vm_reg_name reg;
265 switch (vie->op.op_byte) {
268 * MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
270 * REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
273 error = vie_read_bytereg(vm, vcpuid, vie, &byte);
275 error = memwrite(vm, vcpuid, gpa, byte, size, arg);
279 * MOV from reg (ModRM:reg) to mem (ModRM:r/m)
280 * 89/r: mov r/m32, r32
281 * REX.W + 89/r mov r/m64, r64
285 reg = gpr_map[vie->reg];
286 error = vie_read_register(vm, vcpuid, reg, &val);
288 val &= size2mask[size];
289 error = memwrite(vm, vcpuid, gpa, val, size, arg);
295 * MOV from mem (ModRM:r/m) to reg (ModRM:reg)
297 * REX + 8A/r: mov r/m8, r8
298 * 8B/r: mov r32, r/m32
299 * REX.W 8B/r: mov r64, r/m64
301 if (vie->op.op_byte == 0x8A)
305 error = memread(vm, vcpuid, gpa, &val, size, arg);
307 reg = gpr_map[vie->reg];
308 error = vie_update_register(vm, vcpuid, reg, val, size);
313 * MOV from imm32 to mem (ModRM:r/m)
314 * C7/0 mov r/m32, imm32
315 * REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
317 val = vie->immediate; /* already sign-extended */
323 val &= size2mask[size];
325 error = memwrite(vm, vcpuid, gpa, val, size, arg);
335 * The following simplifying assumptions are made during emulation:
337 * - guest is in 64-bit mode
338 * - default address size is 64-bits
339 * - default operand size is 32-bits
341 * - operand size override is not supported
343 * - address size override is not supported
346 emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
347 mem_region_read_t memread, mem_region_write_t memwrite,
351 enum vm_reg_name reg;
357 switch (vie->op.op_byte) {
360 * MOV and zero extend byte from mem (ModRM:r/m) to
363 * 0F B6/r movzx r/m8, r32
364 * REX.W + 0F B6/r movzx r/m8, r64
367 /* get the first operand */
368 error = memread(vm, vcpuid, gpa, &val, 1, arg);
372 /* get the second operand */
373 reg = gpr_map[vie->reg];
378 /* write the result */
379 error = vie_update_register(vm, vcpuid, reg, val, size);
383 * MOV and sign extend byte from mem (ModRM:r/m) to
386 * 0F BE/r movsx r/m8, r32
387 * REX.W + 0F BE/r movsx r/m8, r64
390 /* get the first operand */
391 error = memread(vm, vcpuid, gpa, &val, 1, arg);
395 /* get the second operand */
396 reg = gpr_map[vie->reg];
401 /* sign extend byte */
404 /* write the result */
405 error = vie_update_register(vm, vcpuid, reg, val, size);
414 emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
415 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
418 enum vm_reg_name reg;
424 switch (vie->op.op_byte) {
427 * AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
430 * 23/r and r32, r/m32
431 * REX.W + 23/r and r64, r/m64
436 /* get the first operand */
437 reg = gpr_map[vie->reg];
438 error = vie_read_register(vm, vcpuid, reg, &val1);
442 /* get the second operand */
443 error = memread(vm, vcpuid, gpa, &val2, size, arg);
447 /* perform the operation and write the result */
449 error = vie_update_register(vm, vcpuid, reg, val1, size);
453 * AND mem (ModRM:r/m) with immediate and store the
456 * 81/ and r/m32, imm32
457 * REX.W + 81/ and r/m64, imm32 sign-extended to 64
459 * Currently, only the AND operation of the 0x81 opcode
460 * is implemented (ModRM:reg = b100).
462 if ((vie->reg & 7) != 4)
468 /* get the first operand */
469 error = memread(vm, vcpuid, gpa, &val1, size, arg);
474 * perform the operation with the pre-fetched immediate
475 * operand and write the result
477 val1 &= vie->immediate;
478 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
487 emulate_or(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
488 mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
496 switch (vie->op.op_byte) {
499 * OR mem (ModRM:r/m) with immediate and store the
502 * 83/ OR r/m32, imm8 sign-extended to 32
503 * REX.W + 83/ OR r/m64, imm8 sign-extended to 64
505 * Currently, only the OR operation of the 0x83 opcode
506 * is implemented (ModRM:reg = b001).
508 if ((vie->reg & 7) != 1)
514 /* get the first operand */
515 error = memread(vm, vcpuid, gpa, &val1, size, arg);
520 * perform the operation with the pre-fetched immediate
521 * operand and write the result
523 val1 |= vie->immediate;
524 error = memwrite(vm, vcpuid, gpa, val1, size, arg);
533 vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
534 mem_region_read_t memread, mem_region_write_t memwrite,
542 switch (vie->op.op_type) {
543 case VIE_OP_TYPE_MOV:
544 error = emulate_mov(vm, vcpuid, gpa, vie,
545 memread, memwrite, memarg);
547 case VIE_OP_TYPE_MOVSX:
548 case VIE_OP_TYPE_MOVZX:
549 error = emulate_movx(vm, vcpuid, gpa, vie,
550 memread, memwrite, memarg);
552 case VIE_OP_TYPE_AND:
553 error = emulate_and(vm, vcpuid, gpa, vie,
554 memread, memwrite, memarg);
557 error = emulate_or(vm, vcpuid, gpa, vie,
558 memread, memwrite, memarg);
570 vie_init(struct vie *vie)
573 bzero(vie, sizeof(struct vie));
575 vie->base_register = VM_REG_LAST;
576 vie->index_register = VM_REG_LAST;
580 gla2gpa(struct vm *vm, uint64_t gla, uint64_t ptpphys,
581 uint64_t *gpa, uint64_t *gpaend)
583 int nlevels, ptpshift, ptpindex;
584 uint64_t *ptpbase, pte, pgsize;
588 * XXX assumes 64-bit guest with 4 page walk levels
591 while (--nlevels >= 0) {
592 /* Zero out the lower 12 bits and the upper 12 bits */
593 ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
595 ptpbase = vm_gpa_hold(vm, ptpphys, PAGE_SIZE, VM_PROT_READ,
600 ptpshift = PAGE_SHIFT + nlevels * 9;
601 ptpindex = (gla >> ptpshift) & 0x1FF;
602 pgsize = 1UL << ptpshift;
604 pte = ptpbase[ptpindex];
606 vm_gpa_release(cookie);
608 if ((pte & PG_V) == 0)
621 /* Zero out the lower 'ptpshift' bits and the upper 12 bits */
622 pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
623 *gpa = pte | (gla & (pgsize - 1));
624 *gpaend = pte + pgsize;
632 vmm_fetch_instruction(struct vm *vm, int cpuid, uint64_t rip, int inst_length,
633 uint64_t cr3, struct vie *vie)
636 uint64_t gpa, gpaend, off;
640 * XXX cache previously fetched instructions using 'rip' as the tag
643 prot = VM_PROT_READ | VM_PROT_EXECUTE;
644 if (inst_length > VIE_INST_SIZE)
645 panic("vmm_fetch_instruction: invalid length %d", inst_length);
647 /* Copy the instruction into 'vie' */
648 while (vie->num_valid < inst_length) {
649 err = gla2gpa(vm, rip, cr3, &gpa, &gpaend);
653 off = gpa & PAGE_MASK;
654 n = min(inst_length - vie->num_valid, PAGE_SIZE - off);
656 if ((hpa = vm_gpa_hold(vm, gpa, n, prot, &cookie)) == NULL)
659 bcopy(hpa, &vie->inst[vie->num_valid], n);
661 vm_gpa_release(cookie);
667 if (vie->num_valid == inst_length)
674 vie_peek(struct vie *vie, uint8_t *x)
677 if (vie->num_processed < vie->num_valid) {
678 *x = vie->inst[vie->num_processed];
685 vie_advance(struct vie *vie)
688 vie->num_processed++;
692 decode_rex(struct vie *vie)
696 if (vie_peek(vie, &x))
699 if (x >= 0x40 && x <= 0x4F) {
700 vie->rex_present = 1;
702 vie->rex_w = x & 0x8 ? 1 : 0;
703 vie->rex_r = x & 0x4 ? 1 : 0;
704 vie->rex_x = x & 0x2 ? 1 : 0;
705 vie->rex_b = x & 0x1 ? 1 : 0;
714 decode_two_byte_opcode(struct vie *vie)
718 if (vie_peek(vie, &x))
721 vie->op = two_byte_opcodes[x];
723 if (vie->op.op_type == VIE_OP_TYPE_NONE)
731 decode_opcode(struct vie *vie)
735 if (vie_peek(vie, &x))
738 vie->op = one_byte_opcodes[x];
740 if (vie->op.op_type == VIE_OP_TYPE_NONE)
745 if (vie->op.op_type == VIE_OP_TYPE_TWO_BYTE)
746 return (decode_two_byte_opcode(vie));
752 decode_modrm(struct vie *vie)
755 enum cpu_mode cpu_mode;
758 * XXX assuming that guest is in IA-32E 64-bit mode
760 cpu_mode = CPU_MODE_64BIT;
762 if (vie_peek(vie, &x))
765 vie->mod = (x >> 6) & 0x3;
766 vie->rm = (x >> 0) & 0x7;
767 vie->reg = (x >> 3) & 0x7;
770 * A direct addressing mode makes no sense in the context of an EPT
771 * fault. There has to be a memory access involved to cause the
774 if (vie->mod == VIE_MOD_DIRECT)
777 if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
778 (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
780 * Table 2-5: Special Cases of REX Encodings
782 * mod=0, r/m=5 is used in the compatibility mode to
783 * indicate a disp32 without a base register.
785 * mod!=3, r/m=4 is used in the compatibility mode to
786 * indicate that the SIB byte is present.
788 * The 'b' bit in the REX prefix is don't care in
792 vie->rm |= (vie->rex_b << 3);
795 vie->reg |= (vie->rex_r << 3);
798 if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
801 vie->base_register = gpr_map[vie->rm];
804 case VIE_MOD_INDIRECT_DISP8:
807 case VIE_MOD_INDIRECT_DISP32:
810 case VIE_MOD_INDIRECT:
811 if (vie->rm == VIE_RM_DISP32) {
814 * Table 2-7. RIP-Relative Addressing
816 * In 64-bit mode mod=00 r/m=101 implies [rip] + disp32
817 * whereas in compatibility mode it just implies disp32.
820 if (cpu_mode == CPU_MODE_64BIT)
821 vie->base_register = VM_REG_GUEST_RIP;
823 vie->base_register = VM_REG_LAST;
835 decode_sib(struct vie *vie)
839 /* Proceed only if SIB byte is present */
840 if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
843 if (vie_peek(vie, &x))
846 /* De-construct the SIB byte */
847 vie->ss = (x >> 6) & 0x3;
848 vie->index = (x >> 3) & 0x7;
849 vie->base = (x >> 0) & 0x7;
851 /* Apply the REX prefix modifiers */
852 vie->index |= vie->rex_x << 3;
853 vie->base |= vie->rex_b << 3;
856 case VIE_MOD_INDIRECT_DISP8:
859 case VIE_MOD_INDIRECT_DISP32:
864 if (vie->mod == VIE_MOD_INDIRECT &&
865 (vie->base == 5 || vie->base == 13)) {
867 * Special case when base register is unused if mod = 0
868 * and base = %rbp or %r13.
871 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
872 * Table 2-5: Special Cases of REX Encodings
876 vie->base_register = gpr_map[vie->base];
880 * All encodings of 'index' are valid except for %rsp (4).
883 * Table 2-3: 32-bit Addressing Forms with the SIB Byte
884 * Table 2-5: Special Cases of REX Encodings
887 vie->index_register = gpr_map[vie->index];
889 /* 'scale' makes sense only in the context of an index register */
890 if (vie->index_register < VM_REG_LAST)
891 vie->scale = 1 << vie->ss;
899 decode_displacement(struct vie *vie)
910 if ((n = vie->disp_bytes) == 0)
913 if (n != 1 && n != 4)
914 panic("decode_displacement: invalid disp_bytes %d", n);
916 for (i = 0; i < n; i++) {
917 if (vie_peek(vie, &x))
925 vie->displacement = u.signed8; /* sign-extended */
927 vie->displacement = u.signed32; /* sign-extended */
933 decode_immediate(struct vie *vie)
943 /* Figure out immediate operand size (if any) */
944 if (vie->op.op_flags & VIE_OP_F_IMM)
946 else if (vie->op.op_flags & VIE_OP_F_IMM8)
949 if ((n = vie->imm_bytes) == 0)
952 if (n != 1 && n != 4)
953 panic("decode_immediate: invalid imm_bytes %d", n);
955 for (i = 0; i < n; i++) {
956 if (vie_peek(vie, &x))
964 vie->immediate = u.signed8; /* sign-extended */
966 vie->immediate = u.signed32; /* sign-extended */
972 * Verify that all the bytes in the instruction buffer were consumed.
975 verify_inst_length(struct vie *vie)
978 if (vie->num_processed == vie->num_valid)
985 * Verify that the 'guest linear address' provided as collateral of the nested
986 * page table fault matches with our instruction decoding.
989 verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
994 /* Skip 'gla' verification */
995 if (gla == VIE_INVALID_GLA)
999 if (vie->base_register != VM_REG_LAST) {
1000 error = vm_get_register(vm, cpuid, vie->base_register, &base);
1002 printf("verify_gla: error %d getting base reg %d\n",
1003 error, vie->base_register);
1008 * RIP-relative addressing starts from the following
1011 if (vie->base_register == VM_REG_GUEST_RIP)
1012 base += vie->num_valid;
1016 if (vie->index_register != VM_REG_LAST) {
1017 error = vm_get_register(vm, cpuid, vie->index_register, &idx);
1019 printf("verify_gla: error %d getting index reg %d\n",
1020 error, vie->index_register);
1025 if (base + vie->scale * idx + vie->displacement != gla) {
1026 printf("verify_gla mismatch: "
1027 "base(0x%0lx), scale(%d), index(0x%0lx), "
1028 "disp(0x%0lx), gla(0x%0lx)\n",
1029 base, vie->scale, idx, vie->displacement, gla);
1037 vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
1040 if (decode_rex(vie))
1043 if (decode_opcode(vie))
1046 if (decode_modrm(vie))
1049 if (decode_sib(vie))
1052 if (decode_displacement(vie))
1055 if (decode_immediate(vie))
1058 if (verify_inst_length(vie))
1061 if (verify_gla(vm, cpuid, gla, vie))
1064 vie->decoded = 1; /* success */
1068 #endif /* _KERNEL */