2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <x86/specialreg.h>
37 #include <x86/apicreg.h>
39 #include <machine/vmm.h>
42 #include "vmm_lapic.h"
46 * Some MSI message definitions
48 #define MSI_X86_ADDR_MASK 0xfff00000
49 #define MSI_X86_ADDR_BASE 0xfee00000
50 #define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */
51 #define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */
54 lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
56 struct vlapic *vlapic;
58 if (cpu < 0 || cpu >= VM_MAXCPU)
62 * According to section "Maskable Hardware Interrupts" in Intel SDM
63 * vectors 16 through 255 can be delivered through the local APIC.
65 if (vector < 16 || vector > 255)
68 vlapic = vm_lapic(vm, cpu);
69 if (vlapic_set_intr_ready(vlapic, vector, level))
70 vcpu_notify_event(vm, cpu, true);
75 lapic_set_local_intr(struct vm *vm, int cpu, int vector)
77 struct vlapic *vlapic;
81 if (cpu < -1 || cpu >= VM_MAXCPU)
85 dmask = vm_active_cpus(vm);
87 CPU_SETOF(cpu, &dmask);
89 while ((cpu = CPU_FFS(&dmask)) != 0) {
92 vlapic = vm_lapic(vm, cpu);
93 error = vlapic_trigger_lvt(vlapic, vector);
102 lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
108 VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
110 if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) {
111 VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr);
116 * Extract the x86-specific fields from the MSI addr/msg
117 * params according to the Intel Arch spec, Vol3 Ch 10.
119 * The PCI specification does not support level triggered
120 * MSI/MSI-X so ignore trigger level in 'msg'.
122 * The 'dest' is interpreted as a logical APIC ID if both
123 * the Redirection Hint and Destination Mode are '1' and
124 * physical otherwise.
126 dest = (addr >> 12) & 0xff;
127 phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
128 (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
129 delmode = msg & APIC_DELMODE_MASK;
132 VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d",
133 phys ? "physical" : "logical", dest, vec);
135 vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec);
140 x2apic_msr(u_int msr)
142 if (msr >= 0x800 && msr <= 0xBFF)
149 x2apic_msr_to_regoff(u_int msr)
152 return ((msr - 0x800) << 4);
159 if (x2apic_msr(msr) || (msr == MSR_APICBASE))
166 lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu)
170 struct vlapic *vlapic;
172 vlapic = vm_lapic(vm, cpu);
174 if (msr == MSR_APICBASE) {
175 *rval = vlapic_get_apicbase(vlapic);
178 offset = x2apic_msr_to_regoff(msr);
179 error = vlapic_read(vlapic, 0, offset, rval, retu);
186 lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu)
190 struct vlapic *vlapic;
192 vlapic = vm_lapic(vm, cpu);
194 if (msr == MSR_APICBASE) {
195 error = vlapic_set_apicbase(vlapic, val);
197 offset = x2apic_msr_to_regoff(msr);
198 error = vlapic_write(vlapic, 0, offset, val, retu);
205 lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
210 struct vlapic *vlapic;
212 off = gpa - DEFAULT_APIC_BASE;
215 * Memory mapped local apic accesses must be 4 bytes wide and
216 * aligned on a 16-byte boundary.
218 if (size != 4 || off & 0xf)
221 vlapic = vm_lapic(vm, cpu);
222 error = vlapic_write(vlapic, 1, off, wval, arg);
227 lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
232 struct vlapic *vlapic;
234 off = gpa - DEFAULT_APIC_BASE;
237 * Memory mapped local apic accesses should be aligned on a
238 * 16-byte boundary. They are also suggested to be 4 bytes
239 * wide, alas not all OSes follow suggestions.
245 vlapic = vm_lapic(vm, cpu);
246 error = vlapic_read(vlapic, 1, off, rval, arg);