2 * Copyright (c) 2012 Ian Lepore
3 * Copyright (c) 2010 Mark Tinguely
4 * Copyright (c) 2004 Olivier Houchard
5 * Copyright (c) 2002 Peter Grehan
6 * Copyright (c) 1997, 1998 Justin T. Gibbs.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #define _ARM32_BUS_DMA_PRIVATE
37 #include <sys/param.h>
40 #include <ddb/db_output.h>
41 #include <sys/systm.h>
42 #include <sys/malloc.h>
44 #include <sys/busdma_bufalloc.h>
45 #include <sys/interrupt.h>
46 #include <sys/kernel.h>
49 #include <sys/memdesc.h>
51 #include <sys/mutex.h>
52 #include <sys/sysctl.h>
56 #include <vm/vm_page.h>
57 #include <vm/vm_map.h>
58 #include <vm/vm_extern.h>
59 #include <vm/vm_kern.h>
61 #include <machine/atomic.h>
62 #include <machine/bus.h>
63 #include <machine/cpufunc.h>
64 #include <machine/md_var.h>
67 #define MAX_DMA_SEGMENTS 4096
68 #define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2
69 #define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3
70 #define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE)
71 #define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4
81 bus_dma_filter_t *filter;
89 bus_dma_lock_t *lockfunc;
91 struct bounce_zone *bounce_zone;
93 * DMA range for this tag. If the page doesn't fall within
94 * one of these ranges, an error is returned. The caller
95 * may then decide what to do with the transfer. If the
96 * range pointer is NULL, it is ignored.
98 struct arm32_dma_range *ranges;
103 vm_offset_t vaddr; /* kva of bounce buffer */
104 bus_addr_t busaddr; /* Physical address */
105 vm_offset_t datavaddr; /* kva of client data */
106 bus_addr_t dataaddr; /* client physical address */
107 bus_size_t datacount; /* client data count */
108 STAILQ_ENTRY(bounce_page) links;
112 vm_offset_t vaddr; /* kva of bounce buffer */
113 bus_addr_t busaddr; /* Physical address */
114 bus_size_t datacount; /* client data count */
117 int busdma_swi_pending;
120 STAILQ_ENTRY(bounce_zone) links;
121 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list;
129 bus_size_t alignment;
133 struct sysctl_ctx_list sysctl_tree;
134 struct sysctl_oid *sysctl_tree_top;
137 static struct mtx bounce_lock;
138 static int total_bpages;
139 static int busdma_zonecount;
140 static uint32_t tags_total;
141 static uint32_t maps_total;
142 static uint32_t maps_dmamem;
143 static uint32_t maps_coherent;
144 static uint64_t maploads_total;
145 static uint64_t maploads_bounced;
146 static uint64_t maploads_coherent;
147 static uint64_t maploads_dmamem;
148 static uint64_t maploads_mbuf;
149 static uint64_t maploads_physmem;
151 static STAILQ_HEAD(, bounce_zone) bounce_zone_list;
153 SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters");
154 SYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0,
155 "Number of active tags");
156 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0,
157 "Number of active maps");
158 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0,
159 "Number of active maps for bus_dmamem_alloc buffers");
160 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0,
161 "Number of active maps with BUS_DMA_COHERENT flag set");
162 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, &maploads_total, 0,
163 "Number of load operations performed");
164 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, &maploads_bounced, 0,
165 "Number of load operations that used bounce buffers");
166 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, &maploads_dmamem, 0,
167 "Number of load operations on BUS_DMA_COHERENT memory");
168 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, &maploads_dmamem, 0,
169 "Number of load operations on bus_dmamem_alloc buffers");
170 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, &maploads_mbuf, 0,
171 "Number of load operations for mbufs");
172 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, &maploads_physmem, 0,
173 "Number of load operations on physical buffers");
174 SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
175 "Total bounce pages");
178 struct bp_list bpages;
184 bus_dmamap_callback_t *callback;
187 #define DMAMAP_COHERENT (1 << 0)
188 #define DMAMAP_DMAMEM_ALLOC (1 << 1)
189 #define DMAMAP_MBUF (1 << 2)
190 STAILQ_ENTRY(bus_dmamap) links;
191 bus_dma_segment_t *segments;
193 struct sync_list slist[];
196 static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist;
197 static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist;
199 static void init_bounce_pages(void *dummy);
200 static int alloc_bounce_zone(bus_dma_tag_t dmat);
201 static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages);
202 static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
204 static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map,
205 vm_offset_t vaddr, bus_addr_t addr,
207 static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage);
208 static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
209 void *buf, bus_size_t buflen, int flags);
210 static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map,
211 vm_paddr_t buf, bus_size_t buflen, int flags);
212 static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
215 static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */
216 static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */
218 busdma_init(void *dummy)
224 /* Create a cache of buffers in standard (cacheable) memory. */
225 standard_allocator = busdma_bufalloc_create("buffer",
226 arm_dcache_align, /* minimum_alignment */
227 NULL, /* uma_alloc func */
228 NULL, /* uma_free func */
229 uma_flags); /* uma_zcreate_flags */
233 * Force UMA zone to allocate service structures like
234 * slabs using own allocator. uma_debug code performs
235 * atomic ops on uma_slab_t fields and safety of this
236 * operation is not guaranteed for write-back caches
238 uma_flags = UMA_ZONE_OFFPAGE;
241 * Create a cache of buffers in uncacheable memory, to implement the
242 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag.
244 coherent_allocator = busdma_bufalloc_create("coherent",
245 arm_dcache_align, /* minimum_alignment */
246 busdma_bufalloc_alloc_uncacheable,
247 busdma_bufalloc_free_uncacheable,
248 uma_flags); /* uma_zcreate_flags */
252 * This init historically used SI_SUB_VM, but now the init code requires
253 * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by
254 * SI_SUB_KMEM and SI_ORDER_SECOND, so we'll go right after that by using
255 * SI_SUB_KMEM and SI_ORDER_THIRD.
257 SYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_THIRD, busdma_init, NULL);
260 exclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr)
263 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) {
264 if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) ||
265 (lowaddr < phys_avail[i] && highaddr >= phys_avail[i]))
272 * Return true if the tag has an exclusion zone that could lead to bouncing.
275 exclusion_bounce(bus_dma_tag_t dmat)
278 return (dmat->flags & BUS_DMA_EXCL_BOUNCE);
282 * Return true if the given address does not fall on the alignment boundary.
285 alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr)
288 return (addr & (dmat->alignment - 1));
292 * Return true if the DMA should bounce because the start or end does not fall
293 * on a cacheline boundary (which would require a partial cacheline flush).
294 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by
295 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a
296 * strict rule that such memory cannot be accessed by the CPU while DMA is in
297 * progress (or by multiple DMA engines at once), so that it's always safe to do
298 * full cacheline flushes even if that affects memory outside the range of a
299 * given DMA operation that doesn't involve the full allocated buffer. If we're
300 * mapping an mbuf, that follows the same rules as a buffer we allocated.
303 cacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size)
306 if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF))
308 return ((addr | size) & arm_dcache_align_mask);
312 * Return true if we might need to bounce the DMA described by addr and size.
314 * This is used to quick-check whether we need to do the more expensive work of
315 * checking the DMA page-by-page looking for alignment and exclusion bounces.
317 * Note that the addr argument might be either virtual or physical. It doesn't
318 * matter because we only look at the low-order bits, which are the same in both
322 might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr,
325 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) ||
326 alignment_bounce(dmat, addr) ||
327 cacheline_bounce(map, addr, size));
331 * Return true if we must bounce the DMA described by paddr and size.
333 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline
334 * boundaries, or doesn't begin on an alignment boundary, or falls within the
335 * exclusion zone of any tag in the ancestry chain.
337 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone
338 * within each tag. If the tag has a filter function, use it to decide whether
339 * the DMA needs to bounce, otherwise any DMA within the zone bounces.
342 must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
346 if (cacheline_bounce(map, paddr, size))
350 * The tag already contains ancestors' alignment restrictions so this
351 * check doesn't need to be inside the loop.
353 if (alignment_bounce(dmat, paddr))
357 * Even though each tag has an exclusion zone that is a superset of its
358 * own and all its ancestors' exclusions, the exclusion zone of each tag
359 * up the chain must be checked within the loop, because the busdma
360 * rules say the filter function is called only when the address lies
361 * within the low-highaddr range of the tag that filterfunc belongs to.
363 while (dmat != NULL && exclusion_bounce(dmat)) {
364 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) &&
365 (dmat->filter == NULL ||
366 dmat->filter(dmat->filterarg, paddr) != 0))
374 static __inline struct arm32_dma_range *
375 _bus_dma_inrange(struct arm32_dma_range *ranges, int nranges,
378 struct arm32_dma_range *dr;
381 for (i = 0, dr = ranges; i < nranges; i++, dr++) {
382 if (curaddr >= dr->dr_sysbase &&
383 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len))
391 * Convenience function for manipulating driver locks from busdma (during
392 * busdma_swi, for example). Drivers that don't provide their own locks
393 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own
394 * non-mutex locking scheme don't have to use this at all.
397 busdma_lock_mutex(void *arg, bus_dma_lock_op_t op)
401 dmtx = (struct mtx *)arg;
410 panic("Unknown operation 0x%x for busdma_lock_mutex!", op);
415 * dflt_lock should never get called. It gets put into the dma tag when
416 * lockfunc == NULL, which is only valid if the maps that are associated
417 * with the tag are meant to never be defered.
418 * XXX Should have a way to identify which driver is responsible here.
421 dflt_lock(void *arg, bus_dma_lock_op_t op)
423 panic("driver error: busdma dflt_lock called");
427 * Allocate a device specific dma_tag.
430 bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
431 bus_size_t boundary, bus_addr_t lowaddr,
432 bus_addr_t highaddr, bus_dma_filter_t *filter,
433 void *filterarg, bus_size_t maxsize, int nsegments,
434 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
435 void *lockfuncarg, bus_dma_tag_t *dmat)
437 bus_dma_tag_t newtag;
442 parent = arm_root_dma_tag;
445 /* Basic sanity checking */
446 if (boundary != 0 && boundary < maxsegsz)
449 /* Return a NULL tag on failure */
456 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF,
458 if (newtag == NULL) {
459 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
460 __func__, newtag, 0, error);
464 newtag->parent = parent;
465 newtag->alignment = alignment;
466 newtag->boundary = boundary;
467 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1);
468 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) +
470 newtag->filter = filter;
471 newtag->filterarg = filterarg;
472 newtag->maxsize = maxsize;
473 newtag->nsegments = nsegments;
474 newtag->maxsegsz = maxsegsz;
475 newtag->flags = flags;
476 newtag->ref_count = 1; /* Count ourself */
477 newtag->map_count = 0;
478 newtag->ranges = bus_dma_get_range();
479 newtag->_nranges = bus_dma_get_range_nb();
480 if (lockfunc != NULL) {
481 newtag->lockfunc = lockfunc;
482 newtag->lockfuncarg = lockfuncarg;
484 newtag->lockfunc = dflt_lock;
485 newtag->lockfuncarg = NULL;
488 /* Take into account any restrictions imposed by our parent tag */
489 if (parent != NULL) {
490 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr);
491 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr);
492 newtag->alignment = MAX(parent->alignment, newtag->alignment);
493 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE;
494 if (newtag->boundary == 0)
495 newtag->boundary = parent->boundary;
496 else if (parent->boundary != 0)
497 newtag->boundary = MIN(parent->boundary,
499 if (newtag->filter == NULL) {
501 * Short circuit to looking at our parent directly
502 * since we have encapsulated all of its information
504 newtag->filter = parent->filter;
505 newtag->filterarg = parent->filterarg;
506 newtag->parent = parent->parent;
508 if (newtag->parent != NULL)
509 atomic_add_int(&parent->ref_count, 1);
512 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr))
513 newtag->flags |= BUS_DMA_EXCL_BOUNCE;
514 if (alignment_bounce(newtag, 1))
515 newtag->flags |= BUS_DMA_ALIGN_BOUNCE;
518 * Any request can auto-bounce due to cacheline alignment, in addition
519 * to any alignment or boundary specifications in the tag, so if the
520 * ALLOCNOW flag is set, there's always work to do.
522 if ((flags & BUS_DMA_ALLOCNOW) != 0) {
523 struct bounce_zone *bz;
525 * Round size up to a full page, and add one more page because
526 * there can always be one more boundary crossing than the
527 * number of pages in a transfer.
529 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE;
531 if ((error = alloc_bounce_zone(newtag)) != 0) {
532 free(newtag, M_DEVBUF);
535 bz = newtag->bounce_zone;
537 if (ptoa(bz->total_bpages) < maxsize) {
540 pages = atop(maxsize) - bz->total_bpages;
542 /* Add pages to our bounce pool */
543 if (alloc_bounce_pages(newtag, pages) < pages)
546 /* Performed initial allocation */
547 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP;
549 newtag->bounce_zone = NULL;
552 free(newtag, M_DEVBUF);
554 atomic_add_32(&tags_total, 1);
557 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
558 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error);
563 bus_dma_tag_destroy(bus_dma_tag_t dmat)
565 bus_dma_tag_t dmat_copy;
573 if (dmat->map_count != 0) {
578 while (dmat != NULL) {
579 bus_dma_tag_t parent;
581 parent = dmat->parent;
582 atomic_subtract_int(&dmat->ref_count, 1);
583 if (dmat->ref_count == 0) {
584 atomic_subtract_32(&tags_total, 1);
585 free(dmat, M_DEVBUF);
587 * Last reference count, so
588 * release our reference
589 * count on our parent.
597 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error);
601 static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp)
603 struct bounce_zone *bz;
607 if (dmat->bounce_zone == NULL)
608 if ((error = alloc_bounce_zone(dmat)) != 0)
610 bz = dmat->bounce_zone;
611 /* Initialize the new map */
612 STAILQ_INIT(&(mapp->bpages));
615 * Attempt to add pages to our pool on a per-instance basis up to a sane
616 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to
617 * alignment and boundary constraints, it could still auto-bounce due to
618 * cacheline alignment, which requires at most two bounce pages.
620 if (dmat->flags & BUS_DMA_COULD_BOUNCE)
621 maxpages = MAX_BPAGES;
623 maxpages = 2 * bz->map_count;
624 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 ||
625 (bz->map_count > 0 && bz->total_bpages < maxpages)) {
628 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1;
629 pages = MIN(maxpages - bz->total_bpages, pages);
630 pages = MAX(pages, 2);
631 if (alloc_bounce_pages(dmat, pages) < pages)
634 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0)
635 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
642 allocate_map(bus_dma_tag_t dmat, int mflags)
644 int mapsize, segsize;
648 * Allocate the map. The map structure ends with an embedded
649 * variable-sized array of sync_list structures. Following that
650 * we allocate enough extra space to hold the array of bus_dma_segments.
652 KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS,
653 ("cannot allocate %u dma segments (max is %u)",
654 dmat->nsegments, MAX_DMA_SEGMENTS));
655 segsize = sizeof(struct bus_dma_segment) * dmat->nsegments;
656 mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments;
657 map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO);
659 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM);
662 map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize);
667 * Allocate a handle for mapping from kva/uva/physical
668 * address space into bus device space.
671 bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
676 *mapp = map = allocate_map(dmat, M_NOWAIT);
678 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM);
683 * Bouncing might be required if the driver asks for an exclusion
684 * region, a data alignment that is stricter than 1, or DMA that begins
685 * or ends with a partial cacheline. Whether bouncing will actually
686 * happen can't be known until mapping time, but we need to pre-allocate
687 * resources now because we might not be allowed to at mapping time.
689 error = allocate_bz_and_pages(dmat, map);
695 if (map->flags & DMAMAP_COHERENT)
696 atomic_add_32(&maps_coherent, 1);
697 atomic_add_32(&maps_total, 1);
702 * Destroy a handle for mapping from kva/uva/physical
703 * address space into bus device space.
706 bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
708 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) {
709 CTR3(KTR_BUSDMA, "%s: tag %p error %d",
710 __func__, dmat, EBUSY);
713 if (dmat->bounce_zone)
714 dmat->bounce_zone->map_count--;
715 if (map->flags & DMAMAP_COHERENT)
716 atomic_subtract_32(&maps_coherent, 1);
717 atomic_subtract_32(&maps_total, 1);
720 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat);
726 * Allocate a piece of memory that can be efficiently mapped into
727 * bus device space based on the constraints lited in the dma tag.
728 * A dmamap to for use with dmamap_load is also allocated.
731 bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
734 busdma_bufalloc_t ba;
735 struct busdma_bufzone *bufzone;
737 vm_memattr_t memattr;
740 if (flags & BUS_DMA_NOWAIT)
744 if (flags & BUS_DMA_ZERO)
747 *mapp = map = allocate_map(dmat, mflags);
749 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
750 __func__, dmat, dmat->flags, ENOMEM);
753 map->flags = DMAMAP_DMAMEM_ALLOC;
755 /* Choose a busdma buffer allocator based on memory type flags. */
756 if (flags & BUS_DMA_COHERENT) {
757 memattr = VM_MEMATTR_UNCACHEABLE;
758 ba = coherent_allocator;
759 map->flags |= DMAMAP_COHERENT;
761 memattr = VM_MEMATTR_DEFAULT;
762 ba = standard_allocator;
766 * Try to find a bufzone in the allocator that holds a cache of buffers
767 * of the right size for this request. If the buffer is too big to be
768 * held in the allocator cache, this returns NULL.
770 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize);
773 * Allocate the buffer from the uma(9) allocator if...
774 * - It's small enough to be in the allocator (bufzone not NULL).
775 * - The alignment constraint isn't larger than the allocation size
776 * (the allocator aligns buffers to their size boundaries).
777 * - There's no need to handle lowaddr/highaddr exclusion zones.
778 * else allocate non-contiguous pages if...
779 * - The page count that could get allocated doesn't exceed nsegments.
780 * - The alignment constraint isn't larger than a page boundary.
781 * - There are no boundary-crossing constraints.
782 * else allocate a block of contiguous pages because one or more of the
783 * constraints is something that only the contig allocator can fulfill.
785 if (bufzone != NULL && dmat->alignment <= bufzone->size &&
786 !exclusion_bounce(dmat)) {
787 *vaddr = uma_zalloc(bufzone->umazone, mflags);
788 } else if (dmat->nsegments >= btoc(dmat->maxsize) &&
789 dmat->alignment <= PAGE_SIZE && dmat->boundary == 0) {
790 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize,
791 mflags, 0, dmat->lowaddr, memattr);
793 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize,
794 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary,
799 if (*vaddr == NULL) {
800 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
801 __func__, dmat, dmat->flags, ENOMEM);
805 } else if ((uintptr_t)*vaddr & (dmat->alignment - 1)) {
806 printf("bus_dmamem_alloc failed to align memory properly.\n");
808 if (map->flags & DMAMAP_COHERENT)
809 atomic_add_32(&maps_coherent, 1);
810 atomic_add_32(&maps_dmamem, 1);
811 atomic_add_32(&maps_total, 1);
814 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
815 __func__, dmat, dmat->flags, 0);
820 * Free a piece of memory and it's allociated dmamap, that was allocated
821 * via bus_dmamem_alloc. Make the same choice for free/contigfree.
824 bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map)
826 struct busdma_bufzone *bufzone;
827 busdma_bufalloc_t ba;
829 if (map->flags & DMAMAP_COHERENT)
830 ba = coherent_allocator;
832 ba = standard_allocator;
834 /* Be careful not to access map from here on. */
836 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize);
838 if (bufzone != NULL && dmat->alignment <= bufzone->size &&
839 !exclusion_bounce(dmat))
840 uma_zfree(bufzone->umazone, vaddr);
842 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize);
845 if (map->flags & DMAMAP_COHERENT)
846 atomic_subtract_32(&maps_coherent, 1);
847 atomic_subtract_32(&maps_total, 1);
848 atomic_subtract_32(&maps_dmamem, 1);
850 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags);
854 _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
855 bus_size_t buflen, int flags)
860 if (map->pagesneeded == 0) {
861 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d"
862 " map= %p, pagesneeded= %d",
863 dmat->lowaddr, dmat->boundary, dmat->alignment,
864 map, map->pagesneeded);
866 * Count the number of bounce pages
867 * needed in order to complete this transfer
870 while (buflen != 0) {
871 sgsize = MIN(buflen, dmat->maxsegsz);
872 if (must_bounce(dmat, map, curaddr, sgsize) != 0) {
873 sgsize = MIN(sgsize, PAGE_SIZE);
879 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded);
884 _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
885 void *buf, bus_size_t buflen, int flags)
888 vm_offset_t vendaddr;
891 if (map->pagesneeded == 0) {
892 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d"
893 " map= %p, pagesneeded= %d",
894 dmat->lowaddr, dmat->boundary, dmat->alignment,
895 map, map->pagesneeded);
897 * Count the number of bounce pages
898 * needed in order to complete this transfer
900 vaddr = (vm_offset_t)buf;
901 vendaddr = (vm_offset_t)buf + buflen;
903 while (vaddr < vendaddr) {
904 if (__predict_true(map->pmap == kernel_pmap))
905 paddr = pmap_kextract(vaddr);
907 paddr = pmap_extract(map->pmap, vaddr);
908 if (must_bounce(dmat, map, paddr,
909 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr &
910 PAGE_MASK)))) != 0) {
913 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK));
916 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded);
921 _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags)
924 /* Reserve Necessary Bounce Pages */
925 mtx_lock(&bounce_lock);
926 if (flags & BUS_DMA_NOWAIT) {
927 if (reserve_bounce_pages(dmat, map, 0) != 0) {
928 map->pagesneeded = 0;
929 mtx_unlock(&bounce_lock);
933 if (reserve_bounce_pages(dmat, map, 1) != 0) {
934 /* Queue us for resources */
935 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links);
936 mtx_unlock(&bounce_lock);
937 return (EINPROGRESS);
940 mtx_unlock(&bounce_lock);
946 * Add a single contiguous physical range to the segment list.
949 _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr,
950 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp)
952 bus_addr_t baddr, bmask;
956 * Make sure we don't cross any boundaries.
958 bmask = ~(dmat->boundary - 1);
959 if (dmat->boundary > 0) {
960 baddr = (curaddr + dmat->boundary) & bmask;
961 if (sgsize > (baddr - curaddr))
962 sgsize = (baddr - curaddr);
966 struct arm32_dma_range *dr;
968 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges,
971 _bus_dmamap_unload(dmat, map);
975 * In a valid DMA range. Translate the physical
976 * memory address to an address in the DMA window.
978 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase;
982 * Insert chunk into a segment, coalescing with
983 * previous segment if possible.
988 segs[seg].ds_addr = curaddr;
989 segs[seg].ds_len = sgsize;
991 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len &&
992 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz &&
993 (dmat->boundary == 0 ||
994 (segs[seg].ds_addr & bmask) == (curaddr & bmask)))
995 segs[seg].ds_len += sgsize;
997 if (++seg >= dmat->nsegments)
999 segs[seg].ds_addr = curaddr;
1000 segs[seg].ds_len = sgsize;
1008 * Utility function to load a physical buffer. segp contains
1009 * the starting segment on entrace, and the ending segment on exit.
1012 _bus_dmamap_load_phys(bus_dma_tag_t dmat,
1014 vm_paddr_t buf, bus_size_t buflen,
1016 bus_dma_segment_t *segs,
1024 segs = map->segments;
1029 if (might_bounce(dmat, map, buflen, buflen)) {
1030 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags);
1031 if (map->pagesneeded != 0) {
1033 error = _bus_dmamap_reserve_pages(dmat, map, flags);
1039 while (buflen > 0) {
1041 sgsize = MIN(buflen, dmat->maxsegsz);
1042 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr,
1044 sgsize = MIN(sgsize, PAGE_SIZE);
1045 curaddr = add_bounce_page(dmat, map, 0, curaddr,
1048 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
1060 _bus_dmamap_unload(dmat, map);
1061 return (EFBIG); /* XXX better return value here? */
1067 _bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map,
1068 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
1069 bus_dma_segment_t *segs, int *segp)
1072 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags,
1077 * Utility function to load a linear buffer. segp contains
1078 * the starting segment on entrace, and the ending segment on exit.
1081 _bus_dmamap_load_buffer(bus_dma_tag_t dmat,
1083 void *buf, bus_size_t buflen,
1086 bus_dma_segment_t *segs,
1092 struct sync_list *sl;
1096 if (map->flags & DMAMAP_COHERENT)
1097 maploads_coherent++;
1098 if (map->flags & DMAMAP_DMAMEM_ALLOC)
1102 segs = map->segments;
1104 if (flags & BUS_DMA_LOAD_MBUF) {
1106 map->flags |= DMAMAP_MBUF;
1111 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) {
1112 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags);
1113 if (map->pagesneeded != 0) {
1115 error = _bus_dmamap_reserve_pages(dmat, map, flags);
1122 vaddr = (vm_offset_t)buf;
1124 while (buflen > 0) {
1126 * Get the physical address for this segment.
1128 if (__predict_true(map->pmap == kernel_pmap))
1129 curaddr = pmap_kextract(vaddr);
1131 curaddr = pmap_extract(map->pmap, vaddr);
1134 * Compute the segment size, and adjust counts.
1136 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK);
1137 if (sgsize > dmat->maxsegsz)
1138 sgsize = dmat->maxsegsz;
1139 if (buflen < sgsize)
1142 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr,
1144 curaddr = add_bounce_page(dmat, map, vaddr, curaddr,
1147 sl = &map->slist[map->sync_count - 1];
1148 if (map->sync_count == 0 ||
1150 curaddr != sl->busaddr + sl->datacount ||
1152 vaddr != sl->vaddr + sl->datacount) {
1153 if (++map->sync_count > dmat->nsegments)
1157 sl->datacount = sgsize;
1158 sl->busaddr = curaddr;
1160 sl->datacount += sgsize;
1162 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
1175 _bus_dmamap_unload(dmat, map);
1176 return (EFBIG); /* XXX better return value here? */
1183 __bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map,
1184 struct memdesc *mem, bus_dmamap_callback_t *callback,
1190 map->callback = callback;
1191 map->callback_arg = callback_arg;
1195 _bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
1196 bus_dma_segment_t *segs, int nsegs, int error)
1200 segs = map->segments;
1205 * Release the mapping held by map.
1208 _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
1210 struct bounce_page *bpage;
1211 struct bounce_zone *bz;
1213 if ((bz = dmat->bounce_zone) != NULL) {
1214 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1215 STAILQ_REMOVE_HEAD(&map->bpages, links);
1216 free_bounce_page(dmat, bpage);
1219 bz = dmat->bounce_zone;
1220 bz->free_bpages += map->pagesreserved;
1221 bz->reserved_bpages -= map->pagesreserved;
1222 map->pagesreserved = 0;
1223 map->pagesneeded = 0;
1225 map->sync_count = 0;
1226 map->flags &= ~DMAMAP_MBUF;
1229 #ifdef notyetbounceuser
1230 /* If busdma uses user pages, then the interrupt handler could
1231 * be use the kernel vm mapping. Both bounce pages and sync list
1232 * do not cross page boundaries.
1233 * Below is a rough sequence that a person would do to fix the
1234 * user page reference in the kernel vmspace. This would be
1235 * done in the dma post routine.
1238 _bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len,
1239 pmap_t pmap, int op)
1245 /* each synclist entry is contained within a single page.
1247 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented
1249 curaddr = pmap_extract(pmap, buf);
1250 va = pmap_dma_map(curaddr);
1253 cpu_dcache_wb_range(va, sgsize);
1256 case SYNC_USER_COPYTO:
1257 bcopy((void *)va, (void *)bounce, sgsize);
1260 case SYNC_USER_COPYFROM:
1261 bcopy((void *) bounce, (void *)va, sgsize);
1273 #define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size)
1274 #define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size)
1275 #define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size)
1277 #define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size)
1278 #define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size)
1279 #define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size)
1283 _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
1285 struct bounce_page *bpage;
1286 struct sync_list *sl, *end;
1288 * If the buffer was from user space, it is possible that this is not
1289 * the same vm map, especially on a POST operation. It's not clear that
1290 * dma on userland buffers can work at all right now, certainly not if a
1291 * partial cacheline flush has to be handled. To be safe, until we're
1292 * able to test direct userland dma, panic on a map mismatch.
1294 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1295 if (!pmap_dmap_iscurrent(map->pmap))
1296 panic("_bus_dmamap_sync: wrong user map for bounce sync.");
1297 /* Handle data bouncing. */
1298 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
1299 "performing bounce", __func__, dmat, dmat->flags, op);
1301 if (op & BUS_DMASYNC_PREWRITE) {
1302 while (bpage != NULL) {
1303 if (bpage->datavaddr != 0)
1304 bcopy((void *)bpage->datavaddr,
1305 (void *)bpage->vaddr,
1308 physcopyout(bpage->dataaddr,
1309 (void *)bpage->vaddr,
1311 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr,
1313 l2cache_wb_range((vm_offset_t)bpage->vaddr,
1314 (vm_offset_t)bpage->busaddr,
1316 bpage = STAILQ_NEXT(bpage, links);
1318 dmat->bounce_zone->total_bounced++;
1321 if (op & BUS_DMASYNC_PREREAD) {
1322 bpage = STAILQ_FIRST(&map->bpages);
1323 while (bpage != NULL) {
1324 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr,
1326 l2cache_inv_range((vm_offset_t)bpage->vaddr,
1327 (vm_offset_t)bpage->busaddr,
1329 bpage = STAILQ_NEXT(bpage, links);
1332 if (op & BUS_DMASYNC_POSTREAD) {
1333 while (bpage != NULL) {
1338 startv = bpage->vaddr &~ arm_dcache_align_mask;
1339 startp = bpage->busaddr &~ arm_dcache_align_mask;
1340 len = bpage->datacount;
1342 if (startv != bpage->vaddr)
1343 len += bpage->vaddr & arm_dcache_align_mask;
1344 if (len & arm_dcache_align_mask)
1346 (len & arm_dcache_align_mask)) +
1348 cpu_dcache_inv_range(startv, len);
1349 l2cache_inv_range(startv, startp, len);
1350 if (bpage->datavaddr != 0)
1351 bcopy((void *)bpage->vaddr,
1352 (void *)bpage->datavaddr,
1355 physcopyin((void *)bpage->vaddr,
1358 bpage = STAILQ_NEXT(bpage, links);
1360 dmat->bounce_zone->total_bounced++;
1363 if (map->flags & DMAMAP_COHERENT)
1366 if (map->sync_count != 0) {
1367 if (!pmap_dmap_iscurrent(map->pmap))
1368 panic("_bus_dmamap_sync: wrong user map for sync.");
1369 /* ARM caches are not self-snooping for dma */
1371 sl = &map->slist[0];
1372 end = &map->slist[map->sync_count];
1373 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
1374 "performing sync", __func__, dmat, dmat->flags, op);
1377 case BUS_DMASYNC_PREWRITE:
1379 cpu_dcache_wb_range(sl->vaddr, sl->datacount);
1380 l2cache_wb_range(sl->vaddr, sl->busaddr,
1386 case BUS_DMASYNC_PREREAD:
1388 cpu_dcache_inv_range(sl->vaddr, sl->datacount);
1389 l2cache_inv_range(sl->vaddr, sl->busaddr,
1395 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD:
1397 cpu_dcache_wbinv_range(sl->vaddr, sl->datacount);
1398 l2cache_wbinv_range(sl->vaddr,
1399 sl->busaddr, sl->datacount);
1404 case BUS_DMASYNC_POSTREAD:
1405 case BUS_DMASYNC_POSTWRITE:
1406 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
1409 panic("unsupported combination of sync operations: 0x%08x\n", op);
1416 init_bounce_pages(void *dummy __unused)
1420 STAILQ_INIT(&bounce_zone_list);
1421 STAILQ_INIT(&bounce_map_waitinglist);
1422 STAILQ_INIT(&bounce_map_callbacklist);
1423 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF);
1425 SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL);
1427 static struct sysctl_ctx_list *
1428 busdma_sysctl_tree(struct bounce_zone *bz)
1430 return (&bz->sysctl_tree);
1433 static struct sysctl_oid *
1434 busdma_sysctl_tree_top(struct bounce_zone *bz)
1436 return (bz->sysctl_tree_top);
1440 alloc_bounce_zone(bus_dma_tag_t dmat)
1442 struct bounce_zone *bz;
1444 /* Check to see if we already have a suitable zone */
1445 STAILQ_FOREACH(bz, &bounce_zone_list, links) {
1446 if ((dmat->alignment <= bz->alignment) &&
1447 (dmat->lowaddr >= bz->lowaddr)) {
1448 dmat->bounce_zone = bz;
1453 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF,
1454 M_NOWAIT | M_ZERO)) == NULL)
1457 STAILQ_INIT(&bz->bounce_page_list);
1458 bz->free_bpages = 0;
1459 bz->reserved_bpages = 0;
1460 bz->active_bpages = 0;
1461 bz->lowaddr = dmat->lowaddr;
1462 bz->alignment = MAX(dmat->alignment, PAGE_SIZE);
1464 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount);
1466 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr);
1467 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links);
1468 dmat->bounce_zone = bz;
1470 sysctl_ctx_init(&bz->sysctl_tree);
1471 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree,
1472 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid,
1474 if (bz->sysctl_tree_top == NULL) {
1475 sysctl_ctx_free(&bz->sysctl_tree);
1476 return (0); /* XXX error code? */
1479 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1480 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1481 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0,
1482 "Total bounce pages");
1483 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1484 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1485 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0,
1486 "Free bounce pages");
1487 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1488 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1489 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0,
1490 "Reserved bounce pages");
1491 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1492 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1493 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0,
1494 "Active bounce pages");
1495 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1496 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1497 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0,
1498 "Total bounce requests (pages bounced)");
1499 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1500 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1501 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0,
1502 "Total bounce requests that were deferred");
1503 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz),
1504 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1505 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, "");
1506 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1507 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1508 "alignment", CTLFLAG_RD, &bz->alignment, 0, "");
1514 alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages)
1516 struct bounce_zone *bz;
1519 bz = dmat->bounce_zone;
1521 while (numpages > 0) {
1522 struct bounce_page *bpage;
1524 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF,
1529 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF,
1530 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0);
1531 if (bpage->vaddr == 0) {
1532 free(bpage, M_DEVBUF);
1535 bpage->busaddr = pmap_kextract(bpage->vaddr);
1536 mtx_lock(&bounce_lock);
1537 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links);
1541 mtx_unlock(&bounce_lock);
1549 reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit)
1551 struct bounce_zone *bz;
1554 mtx_assert(&bounce_lock, MA_OWNED);
1555 bz = dmat->bounce_zone;
1556 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved);
1557 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages))
1558 return (map->pagesneeded - (map->pagesreserved + pages));
1559 bz->free_bpages -= pages;
1560 bz->reserved_bpages += pages;
1561 map->pagesreserved += pages;
1562 pages = map->pagesneeded - map->pagesreserved;
1568 add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr,
1569 bus_addr_t addr, bus_size_t size)
1571 struct bounce_zone *bz;
1572 struct bounce_page *bpage;
1574 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag"));
1575 KASSERT(map != NULL,
1576 ("add_bounce_page: bad map %p", map));
1578 bz = dmat->bounce_zone;
1579 if (map->pagesneeded == 0)
1580 panic("add_bounce_page: map doesn't need any pages");
1583 if (map->pagesreserved == 0)
1584 panic("add_bounce_page: map doesn't need any pages");
1585 map->pagesreserved--;
1587 mtx_lock(&bounce_lock);
1588 bpage = STAILQ_FIRST(&bz->bounce_page_list);
1590 panic("add_bounce_page: free page list is empty");
1592 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links);
1593 bz->reserved_bpages--;
1594 bz->active_bpages++;
1595 mtx_unlock(&bounce_lock);
1597 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
1598 /* Page offset needs to be preserved. */
1599 bpage->vaddr |= vaddr & PAGE_MASK;
1600 bpage->busaddr |= vaddr & PAGE_MASK;
1602 bpage->datavaddr = vaddr;
1603 bpage->dataaddr = addr;
1604 bpage->datacount = size;
1605 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links);
1606 return (bpage->busaddr);
1610 free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage)
1612 struct bus_dmamap *map;
1613 struct bounce_zone *bz;
1615 bz = dmat->bounce_zone;
1616 bpage->datavaddr = 0;
1617 bpage->datacount = 0;
1618 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
1620 * Reset the bounce page to start at offset 0. Other uses
1621 * of this bounce page may need to store a full page of
1622 * data and/or assume it starts on a page boundary.
1624 bpage->vaddr &= ~PAGE_MASK;
1625 bpage->busaddr &= ~PAGE_MASK;
1628 mtx_lock(&bounce_lock);
1629 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links);
1631 bz->active_bpages--;
1632 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) {
1633 if (reserve_bounce_pages(map->dmat, map, 1) == 0) {
1634 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links);
1635 STAILQ_INSERT_TAIL(&bounce_map_callbacklist,
1637 busdma_swi_pending = 1;
1638 bz->total_deferred++;
1639 swi_sched(vm_ih, 0);
1642 mtx_unlock(&bounce_lock);
1649 struct bus_dmamap *map;
1651 mtx_lock(&bounce_lock);
1652 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) {
1653 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links);
1654 mtx_unlock(&bounce_lock);
1656 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK);
1657 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback,
1658 map->callback_arg, BUS_DMA_WAITOK);
1659 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK);
1660 mtx_lock(&bounce_lock);
1662 mtx_unlock(&bounce_lock);