2 * Copyright (c) 2012-2014 Ian Lepore
3 * Copyright (c) 2010 Mark Tinguely
4 * Copyright (c) 2004 Olivier Houchard
5 * Copyright (c) 2002 Peter Grehan
6 * Copyright (c) 1997, 1998 Justin T. Gibbs.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #define _ARM32_BUS_DMA_PRIVATE
37 #include <sys/param.h>
40 #include <ddb/db_output.h>
41 #include <sys/systm.h>
42 #include <sys/malloc.h>
44 #include <sys/busdma_bufalloc.h>
45 #include <sys/interrupt.h>
46 #include <sys/kernel.h>
49 #include <sys/memdesc.h>
51 #include <sys/mutex.h>
52 #include <sys/sysctl.h>
56 #include <vm/vm_page.h>
57 #include <vm/vm_map.h>
58 #include <vm/vm_extern.h>
59 #include <vm/vm_kern.h>
61 #include <machine/atomic.h>
62 #include <machine/bus.h>
63 #include <machine/cpufunc.h>
64 #include <machine/md_var.h>
67 #define MAX_DMA_SEGMENTS 4096
68 #define BUS_DMA_EXCL_BOUNCE BUS_DMA_BUS2
69 #define BUS_DMA_ALIGN_BOUNCE BUS_DMA_BUS3
70 #define BUS_DMA_COULD_BOUNCE (BUS_DMA_EXCL_BOUNCE | BUS_DMA_ALIGN_BOUNCE)
71 #define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4
81 bus_dma_filter_t *filter;
89 bus_dma_lock_t *lockfunc;
91 struct bounce_zone *bounce_zone;
93 * DMA range for this tag. If the page doesn't fall within
94 * one of these ranges, an error is returned. The caller
95 * may then decide what to do with the transfer. If the
96 * range pointer is NULL, it is ignored.
98 struct arm32_dma_range *ranges;
103 vm_offset_t vaddr; /* kva of bounce buffer */
104 bus_addr_t busaddr; /* Physical address */
105 vm_offset_t datavaddr; /* kva of client data */
106 bus_addr_t dataaddr; /* client physical address */
107 bus_size_t datacount; /* client data count */
108 STAILQ_ENTRY(bounce_page) links;
112 vm_offset_t vaddr; /* kva of bounce buffer */
113 bus_addr_t busaddr; /* Physical address */
114 bus_size_t datacount; /* client data count */
117 int busdma_swi_pending;
120 STAILQ_ENTRY(bounce_zone) links;
121 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list;
129 bus_size_t alignment;
133 struct sysctl_ctx_list sysctl_tree;
134 struct sysctl_oid *sysctl_tree_top;
137 static struct mtx bounce_lock;
138 static int total_bpages;
139 static int busdma_zonecount;
140 static uint32_t tags_total;
141 static uint32_t maps_total;
142 static uint32_t maps_dmamem;
143 static uint32_t maps_coherent;
144 static uint64_t maploads_total;
145 static uint64_t maploads_bounced;
146 static uint64_t maploads_coherent;
147 static uint64_t maploads_dmamem;
148 static uint64_t maploads_mbuf;
149 static uint64_t maploads_physmem;
151 static STAILQ_HEAD(, bounce_zone) bounce_zone_list;
153 SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters");
154 SYSCTL_UINT(_hw_busdma, OID_AUTO, tags_total, CTLFLAG_RD, &tags_total, 0,
155 "Number of active tags");
156 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_total, CTLFLAG_RD, &maps_total, 0,
157 "Number of active maps");
158 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_dmamem, CTLFLAG_RD, &maps_dmamem, 0,
159 "Number of active maps for bus_dmamem_alloc buffers");
160 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0,
161 "Number of active maps with BUS_DMA_COHERENT flag set");
162 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, &maploads_total, 0,
163 "Number of load operations performed");
164 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD, &maploads_bounced, 0,
165 "Number of load operations that used bounce buffers");
166 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_coherent, CTLFLAG_RD, &maploads_dmamem, 0,
167 "Number of load operations on BUS_DMA_COHERENT memory");
168 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_dmamem, CTLFLAG_RD, &maploads_dmamem, 0,
169 "Number of load operations on bus_dmamem_alloc buffers");
170 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_mbuf, CTLFLAG_RD, &maploads_mbuf, 0,
171 "Number of load operations for mbufs");
172 SYSCTL_UQUAD(_hw_busdma, OID_AUTO, maploads_physmem, CTLFLAG_RD, &maploads_physmem, 0,
173 "Number of load operations on physical buffers");
174 SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0,
175 "Total bounce pages");
178 struct bp_list bpages;
184 bus_dmamap_callback_t *callback;
187 #define DMAMAP_COHERENT (1 << 0)
188 #define DMAMAP_DMAMEM_ALLOC (1 << 1)
189 #define DMAMAP_MBUF (1 << 2)
190 STAILQ_ENTRY(bus_dmamap) links;
191 bus_dma_segment_t *segments;
193 struct sync_list slist[];
196 static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist;
197 static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist;
199 static void init_bounce_pages(void *dummy);
200 static int alloc_bounce_zone(bus_dma_tag_t dmat);
201 static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages);
202 static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
204 static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map,
205 vm_offset_t vaddr, bus_addr_t addr,
207 static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage);
208 static void _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
209 void *buf, bus_size_t buflen, int flags);
210 static void _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map,
211 vm_paddr_t buf, bus_size_t buflen, int flags);
212 static int _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
215 static busdma_bufalloc_t coherent_allocator; /* Cache of coherent buffers */
216 static busdma_bufalloc_t standard_allocator; /* Cache of standard buffers */
218 busdma_init(void *dummy)
224 /* Create a cache of buffers in standard (cacheable) memory. */
225 standard_allocator = busdma_bufalloc_create("buffer",
226 arm_dcache_align, /* minimum_alignment */
227 NULL, /* uma_alloc func */
228 NULL, /* uma_free func */
229 uma_flags); /* uma_zcreate_flags */
233 * Force UMA zone to allocate service structures like
234 * slabs using own allocator. uma_debug code performs
235 * atomic ops on uma_slab_t fields and safety of this
236 * operation is not guaranteed for write-back caches
238 uma_flags = UMA_ZONE_OFFPAGE;
241 * Create a cache of buffers in uncacheable memory, to implement the
242 * BUS_DMA_COHERENT (and potentially BUS_DMA_NOCACHE) flag.
244 coherent_allocator = busdma_bufalloc_create("coherent",
245 arm_dcache_align, /* minimum_alignment */
246 busdma_bufalloc_alloc_uncacheable,
247 busdma_bufalloc_free_uncacheable,
248 uma_flags); /* uma_zcreate_flags */
252 * This init historically used SI_SUB_VM, but now the init code requires
253 * malloc(9) using M_DEVBUF memory, which is set up later than SI_SUB_VM, by
254 * SI_SUB_KMEM and SI_ORDER_SECOND, so we'll go right after that by using
255 * SI_SUB_KMEM and SI_ORDER_THIRD.
257 SYSINIT(busdma, SI_SUB_KMEM, SI_ORDER_THIRD, busdma_init, NULL);
260 exclusion_bounce_check(vm_offset_t lowaddr, vm_offset_t highaddr)
263 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) {
264 if ((lowaddr >= phys_avail[i] && lowaddr < phys_avail[i + 1]) ||
265 (lowaddr < phys_avail[i] && highaddr >= phys_avail[i]))
272 * Return true if the tag has an exclusion zone that could lead to bouncing.
275 exclusion_bounce(bus_dma_tag_t dmat)
278 return (dmat->flags & BUS_DMA_EXCL_BOUNCE);
282 * Return true if the given address does not fall on the alignment boundary.
285 alignment_bounce(bus_dma_tag_t dmat, bus_addr_t addr)
288 return (addr & (dmat->alignment - 1));
292 * Return true if the DMA should bounce because the start or end does not fall
293 * on a cacheline boundary (which would require a partial cacheline flush).
294 * COHERENT memory doesn't trigger cacheline flushes. Memory allocated by
295 * bus_dmamem_alloc() is always aligned to cacheline boundaries, and there's a
296 * strict rule that such memory cannot be accessed by the CPU while DMA is in
297 * progress (or by multiple DMA engines at once), so that it's always safe to do
298 * full cacheline flushes even if that affects memory outside the range of a
299 * given DMA operation that doesn't involve the full allocated buffer. If we're
300 * mapping an mbuf, that follows the same rules as a buffer we allocated.
303 cacheline_bounce(bus_dmamap_t map, bus_addr_t addr, bus_size_t size)
306 if (map->flags & (DMAMAP_DMAMEM_ALLOC | DMAMAP_COHERENT | DMAMAP_MBUF))
308 return ((addr | size) & arm_dcache_align_mask);
312 * Return true if we might need to bounce the DMA described by addr and size.
314 * This is used to quick-check whether we need to do the more expensive work of
315 * checking the DMA page-by-page looking for alignment and exclusion bounces.
317 * Note that the addr argument might be either virtual or physical. It doesn't
318 * matter because we only look at the low-order bits, which are the same in both
322 might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr,
326 return ((dmat->flags & BUS_DMA_EXCL_BOUNCE) ||
327 alignment_bounce(dmat, addr) ||
328 cacheline_bounce(map, addr, size));
332 * Return true if we must bounce the DMA described by paddr and size.
334 * Bouncing can be triggered by DMA that doesn't begin and end on cacheline
335 * boundaries, or doesn't begin on an alignment boundary, or falls within the
336 * exclusion zone of any tag in the ancestry chain.
338 * For exclusions, walk the chain of tags comparing paddr to the exclusion zone
339 * within each tag. If the tag has a filter function, use it to decide whether
340 * the DMA needs to bounce, otherwise any DMA within the zone bounces.
343 must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
347 if (cacheline_bounce(map, paddr, size))
351 * The tag already contains ancestors' alignment restrictions so this
352 * check doesn't need to be inside the loop.
354 if (alignment_bounce(dmat, paddr))
358 * Even though each tag has an exclusion zone that is a superset of its
359 * own and all its ancestors' exclusions, the exclusion zone of each tag
360 * up the chain must be checked within the loop, because the busdma
361 * rules say the filter function is called only when the address lies
362 * within the low-highaddr range of the tag that filterfunc belongs to.
364 while (dmat != NULL && exclusion_bounce(dmat)) {
365 if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) &&
366 (dmat->filter == NULL ||
367 dmat->filter(dmat->filterarg, paddr) != 0))
375 static __inline struct arm32_dma_range *
376 _bus_dma_inrange(struct arm32_dma_range *ranges, int nranges,
379 struct arm32_dma_range *dr;
382 for (i = 0, dr = ranges; i < nranges; i++, dr++) {
383 if (curaddr >= dr->dr_sysbase &&
384 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len))
392 * Convenience function for manipulating driver locks from busdma (during
393 * busdma_swi, for example). Drivers that don't provide their own locks
394 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own
395 * non-mutex locking scheme don't have to use this at all.
398 busdma_lock_mutex(void *arg, bus_dma_lock_op_t op)
402 dmtx = (struct mtx *)arg;
411 panic("Unknown operation 0x%x for busdma_lock_mutex!", op);
416 * dflt_lock should never get called. It gets put into the dma tag when
417 * lockfunc == NULL, which is only valid if the maps that are associated
418 * with the tag are meant to never be defered.
419 * XXX Should have a way to identify which driver is responsible here.
422 dflt_lock(void *arg, bus_dma_lock_op_t op)
425 panic("driver error: busdma dflt_lock called");
429 * Allocate a device specific dma_tag.
432 bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment,
433 bus_size_t boundary, bus_addr_t lowaddr,
434 bus_addr_t highaddr, bus_dma_filter_t *filter,
435 void *filterarg, bus_size_t maxsize, int nsegments,
436 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
437 void *lockfuncarg, bus_dma_tag_t *dmat)
439 bus_dma_tag_t newtag;
444 parent = arm_root_dma_tag;
447 /* Basic sanity checking */
448 if (boundary != 0 && boundary < maxsegsz)
451 /* Return a NULL tag on failure */
458 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF,
460 if (newtag == NULL) {
461 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
462 __func__, newtag, 0, error);
466 newtag->parent = parent;
467 newtag->alignment = alignment;
468 newtag->boundary = boundary;
469 newtag->lowaddr = trunc_page((vm_paddr_t)lowaddr) + (PAGE_SIZE - 1);
470 newtag->highaddr = trunc_page((vm_paddr_t)highaddr) +
472 newtag->filter = filter;
473 newtag->filterarg = filterarg;
474 newtag->maxsize = maxsize;
475 newtag->nsegments = nsegments;
476 newtag->maxsegsz = maxsegsz;
477 newtag->flags = flags;
478 newtag->ref_count = 1; /* Count ourself */
479 newtag->map_count = 0;
480 newtag->ranges = bus_dma_get_range();
481 newtag->_nranges = bus_dma_get_range_nb();
482 if (lockfunc != NULL) {
483 newtag->lockfunc = lockfunc;
484 newtag->lockfuncarg = lockfuncarg;
486 newtag->lockfunc = dflt_lock;
487 newtag->lockfuncarg = NULL;
490 /* Take into account any restrictions imposed by our parent tag */
491 if (parent != NULL) {
492 newtag->lowaddr = MIN(parent->lowaddr, newtag->lowaddr);
493 newtag->highaddr = MAX(parent->highaddr, newtag->highaddr);
494 newtag->alignment = MAX(parent->alignment, newtag->alignment);
495 newtag->flags |= parent->flags & BUS_DMA_COULD_BOUNCE;
496 if (newtag->boundary == 0)
497 newtag->boundary = parent->boundary;
498 else if (parent->boundary != 0)
499 newtag->boundary = MIN(parent->boundary,
501 if (newtag->filter == NULL) {
503 * Short circuit to looking at our parent directly
504 * since we have encapsulated all of its information
506 newtag->filter = parent->filter;
507 newtag->filterarg = parent->filterarg;
508 newtag->parent = parent->parent;
510 if (newtag->parent != NULL)
511 atomic_add_int(&parent->ref_count, 1);
514 if (exclusion_bounce_check(newtag->lowaddr, newtag->highaddr))
515 newtag->flags |= BUS_DMA_EXCL_BOUNCE;
516 if (alignment_bounce(newtag, 1))
517 newtag->flags |= BUS_DMA_ALIGN_BOUNCE;
520 * Any request can auto-bounce due to cacheline alignment, in addition
521 * to any alignment or boundary specifications in the tag, so if the
522 * ALLOCNOW flag is set, there's always work to do.
524 if ((flags & BUS_DMA_ALLOCNOW) != 0) {
525 struct bounce_zone *bz;
527 * Round size up to a full page, and add one more page because
528 * there can always be one more boundary crossing than the
529 * number of pages in a transfer.
531 maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE;
533 if ((error = alloc_bounce_zone(newtag)) != 0) {
534 free(newtag, M_DEVBUF);
537 bz = newtag->bounce_zone;
539 if (ptoa(bz->total_bpages) < maxsize) {
542 pages = atop(maxsize) - bz->total_bpages;
544 /* Add pages to our bounce pool */
545 if (alloc_bounce_pages(newtag, pages) < pages)
548 /* Performed initial allocation */
549 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP;
551 newtag->bounce_zone = NULL;
554 free(newtag, M_DEVBUF);
556 atomic_add_32(&tags_total, 1);
559 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d",
560 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error);
565 bus_dma_tag_destroy(bus_dma_tag_t dmat)
567 bus_dma_tag_t dmat_copy;
575 if (dmat->map_count != 0) {
580 while (dmat != NULL) {
581 bus_dma_tag_t parent;
583 parent = dmat->parent;
584 atomic_subtract_int(&dmat->ref_count, 1);
585 if (dmat->ref_count == 0) {
586 atomic_subtract_32(&tags_total, 1);
587 free(dmat, M_DEVBUF);
589 * Last reference count, so
590 * release our reference
591 * count on our parent.
599 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error);
603 static int allocate_bz_and_pages(bus_dma_tag_t dmat, bus_dmamap_t mapp)
605 struct bounce_zone *bz;
609 if (dmat->bounce_zone == NULL)
610 if ((error = alloc_bounce_zone(dmat)) != 0)
612 bz = dmat->bounce_zone;
613 /* Initialize the new map */
614 STAILQ_INIT(&(mapp->bpages));
617 * Attempt to add pages to our pool on a per-instance basis up to a sane
618 * limit. Even if the tag isn't flagged as COULD_BOUNCE due to
619 * alignment and boundary constraints, it could still auto-bounce due to
620 * cacheline alignment, which requires at most two bounce pages.
622 if (dmat->flags & BUS_DMA_COULD_BOUNCE)
623 maxpages = MAX_BPAGES;
625 maxpages = 2 * bz->map_count;
626 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 ||
627 (bz->map_count > 0 && bz->total_bpages < maxpages)) {
630 pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1;
631 pages = MIN(maxpages - bz->total_bpages, pages);
632 pages = MAX(pages, 2);
633 if (alloc_bounce_pages(dmat, pages) < pages)
636 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0)
637 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
644 allocate_map(bus_dma_tag_t dmat, int mflags)
646 int mapsize, segsize;
650 * Allocate the map. The map structure ends with an embedded
651 * variable-sized array of sync_list structures. Following that
652 * we allocate enough extra space to hold the array of bus_dma_segments.
654 KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS,
655 ("cannot allocate %u dma segments (max is %u)",
656 dmat->nsegments, MAX_DMA_SEGMENTS));
657 segsize = sizeof(struct bus_dma_segment) * dmat->nsegments;
658 mapsize = sizeof(*map) + sizeof(struct sync_list) * dmat->nsegments;
659 map = malloc(mapsize + segsize, M_DEVBUF, mflags | M_ZERO);
661 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM);
664 map->segments = (bus_dma_segment_t *)((uintptr_t)map + mapsize);
669 * Allocate a handle for mapping from kva/uva/physical
670 * address space into bus device space.
673 bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
678 *mapp = map = allocate_map(dmat, M_NOWAIT);
680 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM);
685 * Bouncing might be required if the driver asks for an exclusion
686 * region, a data alignment that is stricter than 1, or DMA that begins
687 * or ends with a partial cacheline. Whether bouncing will actually
688 * happen can't be known until mapping time, but we need to pre-allocate
689 * resources now because we might not be allowed to at mapping time.
691 error = allocate_bz_and_pages(dmat, map);
697 if (map->flags & DMAMAP_COHERENT)
698 atomic_add_32(&maps_coherent, 1);
699 atomic_add_32(&maps_total, 1);
706 * Destroy a handle for mapping from kva/uva/physical
707 * address space into bus device space.
710 bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
712 if (STAILQ_FIRST(&map->bpages) != NULL || map->sync_count != 0) {
713 CTR3(KTR_BUSDMA, "%s: tag %p error %d",
714 __func__, dmat, EBUSY);
717 if (dmat->bounce_zone)
718 dmat->bounce_zone->map_count--;
719 if (map->flags & DMAMAP_COHERENT)
720 atomic_subtract_32(&maps_coherent, 1);
721 atomic_subtract_32(&maps_total, 1);
724 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat);
730 * Allocate a piece of memory that can be efficiently mapped into
731 * bus device space based on the constraints lited in the dma tag.
732 * A dmamap to for use with dmamap_load is also allocated.
735 bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
738 busdma_bufalloc_t ba;
739 struct busdma_bufzone *bufzone;
741 vm_memattr_t memattr;
744 if (flags & BUS_DMA_NOWAIT)
748 if (flags & BUS_DMA_ZERO)
751 *mapp = map = allocate_map(dmat, mflags);
753 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
754 __func__, dmat, dmat->flags, ENOMEM);
757 map->flags = DMAMAP_DMAMEM_ALLOC;
759 /* Choose a busdma buffer allocator based on memory type flags. */
760 if (flags & BUS_DMA_COHERENT) {
761 memattr = VM_MEMATTR_UNCACHEABLE;
762 ba = coherent_allocator;
763 map->flags |= DMAMAP_COHERENT;
765 memattr = VM_MEMATTR_DEFAULT;
766 ba = standard_allocator;
770 * Try to find a bufzone in the allocator that holds a cache of buffers
771 * of the right size for this request. If the buffer is too big to be
772 * held in the allocator cache, this returns NULL.
774 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize);
777 * Allocate the buffer from the uma(9) allocator if...
778 * - It's small enough to be in the allocator (bufzone not NULL).
779 * - The alignment constraint isn't larger than the allocation size
780 * (the allocator aligns buffers to their size boundaries).
781 * - There's no need to handle lowaddr/highaddr exclusion zones.
782 * else allocate non-contiguous pages if...
783 * - The page count that could get allocated doesn't exceed
784 * nsegments also when the maximum segment size is less
786 * - The alignment constraint isn't larger than a page boundary.
787 * - There are no boundary-crossing constraints.
788 * else allocate a block of contiguous pages because one or more of the
789 * constraints is something that only the contig allocator can fulfill.
791 if (bufzone != NULL && dmat->alignment <= bufzone->size &&
792 !exclusion_bounce(dmat)) {
793 *vaddr = uma_zalloc(bufzone->umazone, mflags);
794 } else if (dmat->nsegments >=
795 howmany(dmat->maxsize, MIN(dmat->maxsegsz, PAGE_SIZE)) &&
796 dmat->alignment <= PAGE_SIZE &&
797 (dmat->boundary % PAGE_SIZE) == 0) {
798 *vaddr = (void *)kmem_alloc_attr(kernel_arena, dmat->maxsize,
799 mflags, 0, dmat->lowaddr, memattr);
801 *vaddr = (void *)kmem_alloc_contig(kernel_arena, dmat->maxsize,
802 mflags, 0, dmat->lowaddr, dmat->alignment, dmat->boundary,
807 if (*vaddr == NULL) {
808 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
809 __func__, dmat, dmat->flags, ENOMEM);
813 } else if ((uintptr_t)*vaddr & (dmat->alignment - 1)) {
814 printf("bus_dmamem_alloc failed to align memory properly.\n");
816 if (map->flags & DMAMAP_COHERENT)
817 atomic_add_32(&maps_coherent, 1);
818 atomic_add_32(&maps_dmamem, 1);
819 atomic_add_32(&maps_total, 1);
822 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
823 __func__, dmat, dmat->flags, 0);
828 * Free a piece of memory and it's allociated dmamap, that was allocated
829 * via bus_dmamem_alloc. Make the same choice for free/contigfree.
832 bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map)
834 struct busdma_bufzone *bufzone;
835 busdma_bufalloc_t ba;
837 if (map->flags & DMAMAP_COHERENT)
838 ba = coherent_allocator;
840 ba = standard_allocator;
842 bufzone = busdma_bufalloc_findzone(ba, dmat->maxsize);
844 if (bufzone != NULL && dmat->alignment <= bufzone->size &&
845 !exclusion_bounce(dmat))
846 uma_zfree(bufzone->umazone, vaddr);
848 kmem_free(kernel_arena, (vm_offset_t)vaddr, dmat->maxsize);
851 if (map->flags & DMAMAP_COHERENT)
852 atomic_subtract_32(&maps_coherent, 1);
853 atomic_subtract_32(&maps_total, 1);
854 atomic_subtract_32(&maps_dmamem, 1);
856 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags);
860 _bus_dmamap_count_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
861 bus_size_t buflen, int flags)
866 if (map->pagesneeded == 0) {
867 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d"
868 " map= %p, pagesneeded= %d",
869 dmat->lowaddr, dmat->boundary, dmat->alignment,
870 map, map->pagesneeded);
872 * Count the number of bounce pages
873 * needed in order to complete this transfer
876 while (buflen != 0) {
877 sgsize = MIN(buflen, dmat->maxsegsz);
878 if (must_bounce(dmat, map, curaddr, sgsize) != 0) {
879 sgsize = MIN(sgsize, PAGE_SIZE);
885 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded);
890 _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map,
891 void *buf, bus_size_t buflen, int flags)
894 vm_offset_t vendaddr;
897 if (map->pagesneeded == 0) {
898 CTR5(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d"
899 " map= %p, pagesneeded= %d",
900 dmat->lowaddr, dmat->boundary, dmat->alignment,
901 map, map->pagesneeded);
903 * Count the number of bounce pages
904 * needed in order to complete this transfer
906 vaddr = (vm_offset_t)buf;
907 vendaddr = (vm_offset_t)buf + buflen;
909 while (vaddr < vendaddr) {
910 if (__predict_true(map->pmap == kernel_pmap))
911 paddr = pmap_kextract(vaddr);
913 paddr = pmap_extract(map->pmap, vaddr);
914 if (must_bounce(dmat, map, paddr,
915 min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr &
916 PAGE_MASK)))) != 0) {
919 vaddr += (PAGE_SIZE - ((vm_offset_t)vaddr & PAGE_MASK));
922 CTR1(KTR_BUSDMA, "pagesneeded= %d", map->pagesneeded);
927 _bus_dmamap_reserve_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int flags)
930 /* Reserve Necessary Bounce Pages */
931 mtx_lock(&bounce_lock);
932 if (flags & BUS_DMA_NOWAIT) {
933 if (reserve_bounce_pages(dmat, map, 0) != 0) {
934 map->pagesneeded = 0;
935 mtx_unlock(&bounce_lock);
939 if (reserve_bounce_pages(dmat, map, 1) != 0) {
940 /* Queue us for resources */
941 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, map, links);
942 mtx_unlock(&bounce_lock);
943 return (EINPROGRESS);
946 mtx_unlock(&bounce_lock);
952 * Add a single contiguous physical range to the segment list.
955 _bus_dmamap_addseg(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t curaddr,
956 bus_size_t sgsize, bus_dma_segment_t *segs, int *segp)
958 bus_addr_t baddr, bmask;
962 * Make sure we don't cross any boundaries.
964 bmask = ~(dmat->boundary - 1);
965 if (dmat->boundary > 0) {
966 baddr = (curaddr + dmat->boundary) & bmask;
967 if (sgsize > (baddr - curaddr))
968 sgsize = (baddr - curaddr);
972 struct arm32_dma_range *dr;
974 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges,
977 _bus_dmamap_unload(dmat, map);
981 * In a valid DMA range. Translate the physical
982 * memory address to an address in the DMA window.
984 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase;
988 * Insert chunk into a segment, coalescing with
989 * previous segment if possible.
994 segs[seg].ds_addr = curaddr;
995 segs[seg].ds_len = sgsize;
997 if (curaddr == segs[seg].ds_addr + segs[seg].ds_len &&
998 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz &&
999 (dmat->boundary == 0 ||
1000 (segs[seg].ds_addr & bmask) == (curaddr & bmask)))
1001 segs[seg].ds_len += sgsize;
1003 if (++seg >= dmat->nsegments)
1005 segs[seg].ds_addr = curaddr;
1006 segs[seg].ds_len = sgsize;
1014 * Utility function to load a physical buffer. segp contains
1015 * the starting segment on entrace, and the ending segment on exit.
1018 _bus_dmamap_load_phys(bus_dma_tag_t dmat,
1020 vm_paddr_t buf, bus_size_t buflen,
1022 bus_dma_segment_t *segs,
1030 segs = map->segments;
1035 if (might_bounce(dmat, map, buflen, buflen)) {
1036 _bus_dmamap_count_phys(dmat, map, buf, buflen, flags);
1037 if (map->pagesneeded != 0) {
1039 error = _bus_dmamap_reserve_pages(dmat, map, flags);
1045 while (buflen > 0) {
1047 sgsize = MIN(buflen, dmat->maxsegsz);
1048 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr,
1050 sgsize = MIN(sgsize, PAGE_SIZE);
1051 curaddr = add_bounce_page(dmat, map, 0, curaddr,
1054 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
1066 _bus_dmamap_unload(dmat, map);
1067 return (EFBIG); /* XXX better return value here? */
1073 _bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map,
1074 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
1075 bus_dma_segment_t *segs, int *segp)
1078 return (bus_dmamap_load_ma_triv(dmat, map, ma, tlen, ma_offs, flags,
1083 * Utility function to load a linear buffer. segp contains
1084 * the starting segment on entrace, and the ending segment on exit.
1087 _bus_dmamap_load_buffer(bus_dma_tag_t dmat,
1089 void *buf, bus_size_t buflen,
1092 bus_dma_segment_t *segs,
1098 struct sync_list *sl;
1102 if (map->flags & DMAMAP_COHERENT)
1103 maploads_coherent++;
1104 if (map->flags & DMAMAP_DMAMEM_ALLOC)
1108 segs = map->segments;
1110 if (flags & BUS_DMA_LOAD_MBUF) {
1112 map->flags |= DMAMAP_MBUF;
1117 if (might_bounce(dmat, map, (bus_addr_t)buf, buflen)) {
1118 _bus_dmamap_count_pages(dmat, map, buf, buflen, flags);
1119 if (map->pagesneeded != 0) {
1121 error = _bus_dmamap_reserve_pages(dmat, map, flags);
1128 vaddr = (vm_offset_t)buf;
1130 while (buflen > 0) {
1132 * Get the physical address for this segment.
1134 if (__predict_true(map->pmap == kernel_pmap))
1135 curaddr = pmap_kextract(vaddr);
1137 curaddr = pmap_extract(map->pmap, vaddr);
1140 * Compute the segment size, and adjust counts.
1142 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK);
1143 if (sgsize > dmat->maxsegsz)
1144 sgsize = dmat->maxsegsz;
1145 if (buflen < sgsize)
1148 if (map->pagesneeded != 0 && must_bounce(dmat, map, curaddr,
1150 curaddr = add_bounce_page(dmat, map, vaddr, curaddr,
1153 sl = &map->slist[map->sync_count - 1];
1154 if (map->sync_count == 0 ||
1156 curaddr != sl->busaddr + sl->datacount ||
1158 vaddr != sl->vaddr + sl->datacount) {
1159 if (++map->sync_count > dmat->nsegments)
1163 sl->datacount = sgsize;
1164 sl->busaddr = curaddr;
1166 sl->datacount += sgsize;
1168 sgsize = _bus_dmamap_addseg(dmat, map, curaddr, sgsize, segs,
1181 _bus_dmamap_unload(dmat, map);
1182 return (EFBIG); /* XXX better return value here? */
1189 __bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map,
1190 struct memdesc *mem, bus_dmamap_callback_t *callback,
1196 map->callback = callback;
1197 map->callback_arg = callback_arg;
1201 _bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
1202 bus_dma_segment_t *segs, int nsegs, int error)
1206 segs = map->segments;
1211 * Release the mapping held by map.
1214 _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
1216 struct bounce_page *bpage;
1217 struct bounce_zone *bz;
1219 if ((bz = dmat->bounce_zone) != NULL) {
1220 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1221 STAILQ_REMOVE_HEAD(&map->bpages, links);
1222 free_bounce_page(dmat, bpage);
1225 bz = dmat->bounce_zone;
1226 bz->free_bpages += map->pagesreserved;
1227 bz->reserved_bpages -= map->pagesreserved;
1228 map->pagesreserved = 0;
1229 map->pagesneeded = 0;
1231 map->sync_count = 0;
1232 map->flags &= ~DMAMAP_MBUF;
1235 #ifdef notyetbounceuser
1236 /* If busdma uses user pages, then the interrupt handler could
1237 * be use the kernel vm mapping. Both bounce pages and sync list
1238 * do not cross page boundaries.
1239 * Below is a rough sequence that a person would do to fix the
1240 * user page reference in the kernel vmspace. This would be
1241 * done in the dma post routine.
1244 _bus_dmamap_fix_user(vm_offset_t buf, bus_size_t len,
1245 pmap_t pmap, int op)
1252 * each synclist entry is contained within a single page.
1253 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented
1255 curaddr = pmap_extract(pmap, buf);
1256 va = pmap_dma_map(curaddr);
1259 cpu_dcache_wb_range(va, sgsize);
1262 case SYNC_USER_COPYTO:
1263 bcopy((void *)va, (void *)bounce, sgsize);
1266 case SYNC_USER_COPYFROM:
1267 bcopy((void *) bounce, (void *)va, sgsize);
1279 #define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(pa, size)
1280 #define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(pa, size)
1281 #define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(pa, size)
1283 #define l2cache_wb_range(va, pa, size) cpu_l2cache_wb_range(va, size)
1284 #define l2cache_wbinv_range(va, pa, size) cpu_l2cache_wbinv_range(va, size)
1285 #define l2cache_inv_range(va, pa, size) cpu_l2cache_inv_range(va, size)
1289 _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
1291 struct bounce_page *bpage;
1292 struct sync_list *sl, *end;
1294 * If the buffer was from user space, it is possible that this is not
1295 * the same vm map, especially on a POST operation. It's not clear that
1296 * dma on userland buffers can work at all right now. To be safe, until
1297 * we're able to test direct userland dma, panic on a map mismatch.
1299 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) {
1300 if (!pmap_dmap_iscurrent(map->pmap))
1301 panic("_bus_dmamap_sync: wrong user map for bounce sync.");
1303 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
1304 "performing bounce", __func__, dmat, dmat->flags, op);
1307 * For PREWRITE do a writeback. Clean the caches from the
1308 * innermost to the outermost levels.
1310 if (op & BUS_DMASYNC_PREWRITE) {
1311 while (bpage != NULL) {
1312 if (bpage->datavaddr != 0)
1313 bcopy((void *)bpage->datavaddr,
1314 (void *)bpage->vaddr,
1317 physcopyout(bpage->dataaddr,
1318 (void *)bpage->vaddr,
1320 cpu_dcache_wb_range((vm_offset_t)bpage->vaddr,
1322 l2cache_wb_range((vm_offset_t)bpage->vaddr,
1323 (vm_offset_t)bpage->busaddr,
1325 bpage = STAILQ_NEXT(bpage, links);
1327 dmat->bounce_zone->total_bounced++;
1331 * Do an invalidate for PREREAD unless a writeback was already
1332 * done above due to PREWRITE also being set. The reason for a
1333 * PREREAD invalidate is to prevent dirty lines currently in the
1334 * cache from being evicted during the DMA. If a writeback was
1335 * done due to PREWRITE also being set there will be no dirty
1336 * lines and the POSTREAD invalidate handles the rest. The
1337 * invalidate is done from the innermost to outermost level. If
1338 * L2 were done first, a dirty cacheline could be automatically
1339 * evicted from L1 before we invalidated it, re-dirtying the L2.
1341 if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) {
1342 bpage = STAILQ_FIRST(&map->bpages);
1343 while (bpage != NULL) {
1344 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr,
1346 l2cache_inv_range((vm_offset_t)bpage->vaddr,
1347 (vm_offset_t)bpage->busaddr,
1349 bpage = STAILQ_NEXT(bpage, links);
1354 * Re-invalidate the caches on a POSTREAD, even though they were
1355 * already invalidated at PREREAD time. Aggressive prefetching
1356 * due to accesses to other data near the dma buffer could have
1357 * brought buffer data into the caches which is now stale. The
1358 * caches are invalidated from the outermost to innermost; the
1359 * prefetches could be happening right now, and if L1 were
1360 * invalidated first, stale L2 data could be prefetched into L1.
1362 if (op & BUS_DMASYNC_POSTREAD) {
1363 while (bpage != NULL) {
1368 startv = bpage->vaddr &~ arm_dcache_align_mask;
1369 startp = bpage->busaddr &~ arm_dcache_align_mask;
1370 len = bpage->datacount;
1372 if (startv != bpage->vaddr)
1373 len += bpage->vaddr & arm_dcache_align_mask;
1374 if (len & arm_dcache_align_mask)
1376 (len & arm_dcache_align_mask)) +
1378 l2cache_inv_range(startv, startp, len);
1379 cpu_dcache_inv_range(startv, len);
1380 if (bpage->datavaddr != 0)
1381 bcopy((void *)bpage->vaddr,
1382 (void *)bpage->datavaddr,
1385 physcopyin((void *)bpage->vaddr,
1388 bpage = STAILQ_NEXT(bpage, links);
1390 dmat->bounce_zone->total_bounced++;
1395 * For COHERENT memory no cache maintenance is necessary, but ensure all
1396 * writes have reached memory for the PREWRITE case. No action is
1397 * needed for a PREREAD without PREWRITE also set, because that would
1398 * imply that the cpu had written to the COHERENT buffer and expected
1399 * the dma device to see that change, and by definition a PREWRITE sync
1400 * is required to make that happen.
1402 if (map->flags & DMAMAP_COHERENT) {
1403 if (op & BUS_DMASYNC_PREWRITE) {
1405 cpu_l2cache_drain_writebuf();
1411 * Cache maintenance for normal (non-COHERENT non-bounce) buffers. All
1412 * the comments about the sequences for flushing cache levels in the
1413 * bounce buffer code above apply here as well. In particular, the fact
1414 * that the sequence is inner-to-outer for PREREAD invalidation and
1415 * outer-to-inner for POSTREAD invalidation is not a mistake.
1417 if (map->sync_count != 0) {
1418 if (!pmap_dmap_iscurrent(map->pmap))
1419 panic("_bus_dmamap_sync: wrong user map for sync.");
1421 sl = &map->slist[0];
1422 end = &map->slist[map->sync_count];
1423 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x "
1424 "performing sync", __func__, dmat, dmat->flags, op);
1427 case BUS_DMASYNC_PREWRITE:
1428 case BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD:
1430 cpu_dcache_wb_range(sl->vaddr, sl->datacount);
1431 l2cache_wb_range(sl->vaddr, sl->busaddr,
1437 case BUS_DMASYNC_PREREAD:
1439 * An mbuf may start in the middle of a cacheline. There
1440 * will be no cpu writes to the beginning of that line
1441 * (which contains the mbuf header) while dma is in
1442 * progress. Handle that case by doing a writeback of
1443 * just the first cacheline before invalidating the
1444 * overall buffer. Any mbuf in a chain may have this
1445 * misalignment. Buffers which are not mbufs bounce if
1446 * they are not aligned to a cacheline.
1449 if (sl->vaddr & arm_dcache_align_mask) {
1450 KASSERT(map->flags & DMAMAP_MBUF,
1451 ("unaligned buffer is not an mbuf"));
1452 cpu_dcache_wb_range(sl->vaddr, 1);
1453 l2cache_wb_range(sl->vaddr,
1456 cpu_dcache_inv_range(sl->vaddr, sl->datacount);
1457 l2cache_inv_range(sl->vaddr, sl->busaddr,
1463 case BUS_DMASYNC_POSTWRITE:
1466 case BUS_DMASYNC_POSTREAD:
1467 case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
1469 l2cache_inv_range(sl->vaddr, sl->busaddr,
1471 cpu_dcache_inv_range(sl->vaddr, sl->datacount);
1477 panic("unsupported combination of sync operations: 0x%08x\n", op);
1484 init_bounce_pages(void *dummy __unused)
1488 STAILQ_INIT(&bounce_zone_list);
1489 STAILQ_INIT(&bounce_map_waitinglist);
1490 STAILQ_INIT(&bounce_map_callbacklist);
1491 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF);
1493 SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL);
1495 static struct sysctl_ctx_list *
1496 busdma_sysctl_tree(struct bounce_zone *bz)
1499 return (&bz->sysctl_tree);
1502 static struct sysctl_oid *
1503 busdma_sysctl_tree_top(struct bounce_zone *bz)
1506 return (bz->sysctl_tree_top);
1510 alloc_bounce_zone(bus_dma_tag_t dmat)
1512 struct bounce_zone *bz;
1514 /* Check to see if we already have a suitable zone */
1515 STAILQ_FOREACH(bz, &bounce_zone_list, links) {
1516 if ((dmat->alignment <= bz->alignment) &&
1517 (dmat->lowaddr >= bz->lowaddr)) {
1518 dmat->bounce_zone = bz;
1523 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF,
1524 M_NOWAIT | M_ZERO)) == NULL)
1527 STAILQ_INIT(&bz->bounce_page_list);
1528 bz->free_bpages = 0;
1529 bz->reserved_bpages = 0;
1530 bz->active_bpages = 0;
1531 bz->lowaddr = dmat->lowaddr;
1532 bz->alignment = MAX(dmat->alignment, PAGE_SIZE);
1534 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount);
1536 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr);
1537 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links);
1538 dmat->bounce_zone = bz;
1540 sysctl_ctx_init(&bz->sysctl_tree);
1541 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree,
1542 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid,
1544 if (bz->sysctl_tree_top == NULL) {
1545 sysctl_ctx_free(&bz->sysctl_tree);
1546 return (0); /* XXX error code? */
1549 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1550 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1551 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0,
1552 "Total bounce pages");
1553 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1554 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1555 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0,
1556 "Free bounce pages");
1557 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1558 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1559 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0,
1560 "Reserved bounce pages");
1561 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1562 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1563 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0,
1564 "Active bounce pages");
1565 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1566 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1567 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0,
1568 "Total bounce requests (pages bounced)");
1569 SYSCTL_ADD_INT(busdma_sysctl_tree(bz),
1570 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1571 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0,
1572 "Total bounce requests that were deferred");
1573 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz),
1574 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1575 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, "");
1576 SYSCTL_ADD_ULONG(busdma_sysctl_tree(bz),
1577 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO,
1578 "alignment", CTLFLAG_RD, &bz->alignment, "");
1584 alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages)
1586 struct bounce_zone *bz;
1589 bz = dmat->bounce_zone;
1591 while (numpages > 0) {
1592 struct bounce_page *bpage;
1594 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF,
1599 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF,
1600 M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0);
1601 if (bpage->vaddr == 0) {
1602 free(bpage, M_DEVBUF);
1605 bpage->busaddr = pmap_kextract(bpage->vaddr);
1606 mtx_lock(&bounce_lock);
1607 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links);
1611 mtx_unlock(&bounce_lock);
1619 reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit)
1621 struct bounce_zone *bz;
1624 mtx_assert(&bounce_lock, MA_OWNED);
1625 bz = dmat->bounce_zone;
1626 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved);
1627 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages))
1628 return (map->pagesneeded - (map->pagesreserved + pages));
1629 bz->free_bpages -= pages;
1630 bz->reserved_bpages += pages;
1631 map->pagesreserved += pages;
1632 pages = map->pagesneeded - map->pagesreserved;
1638 add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr,
1639 bus_addr_t addr, bus_size_t size)
1641 struct bounce_zone *bz;
1642 struct bounce_page *bpage;
1644 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag"));
1645 KASSERT(map != NULL,
1646 ("add_bounce_page: bad map %p", map));
1648 bz = dmat->bounce_zone;
1649 if (map->pagesneeded == 0)
1650 panic("add_bounce_page: map doesn't need any pages");
1653 if (map->pagesreserved == 0)
1654 panic("add_bounce_page: map doesn't need any pages");
1655 map->pagesreserved--;
1657 mtx_lock(&bounce_lock);
1658 bpage = STAILQ_FIRST(&bz->bounce_page_list);
1660 panic("add_bounce_page: free page list is empty");
1662 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links);
1663 bz->reserved_bpages--;
1664 bz->active_bpages++;
1665 mtx_unlock(&bounce_lock);
1667 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
1668 /* Page offset needs to be preserved. */
1669 bpage->vaddr |= addr & PAGE_MASK;
1670 bpage->busaddr |= addr & PAGE_MASK;
1672 bpage->datavaddr = vaddr;
1673 bpage->dataaddr = addr;
1674 bpage->datacount = size;
1675 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links);
1676 return (bpage->busaddr);
1680 free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage)
1682 struct bus_dmamap *map;
1683 struct bounce_zone *bz;
1685 bz = dmat->bounce_zone;
1686 bpage->datavaddr = 0;
1687 bpage->datacount = 0;
1688 if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
1690 * Reset the bounce page to start at offset 0. Other uses
1691 * of this bounce page may need to store a full page of
1692 * data and/or assume it starts on a page boundary.
1694 bpage->vaddr &= ~PAGE_MASK;
1695 bpage->busaddr &= ~PAGE_MASK;
1698 mtx_lock(&bounce_lock);
1699 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links);
1701 bz->active_bpages--;
1702 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) {
1703 if (reserve_bounce_pages(map->dmat, map, 1) == 0) {
1704 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links);
1705 STAILQ_INSERT_TAIL(&bounce_map_callbacklist,
1707 busdma_swi_pending = 1;
1708 bz->total_deferred++;
1709 swi_sched(vm_ih, 0);
1712 mtx_unlock(&bounce_lock);
1719 struct bus_dmamap *map;
1721 mtx_lock(&bounce_lock);
1722 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) {
1723 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links);
1724 mtx_unlock(&bounce_lock);
1726 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_LOCK);
1727 bus_dmamap_load_mem(map->dmat, map, &map->mem, map->callback,
1728 map->callback_arg, BUS_DMA_WAITOK);
1729 dmat->lockfunc(dmat->lockfuncarg, BUS_DMA_UNLOCK);
1730 mtx_lock(&bounce_lock);
1732 mtx_unlock(&bounce_lock);