1 /* $NetBSD: cpufunc_asm_arm10.S,v 1.1 2003/09/06 09:12:29 rearnsha Exp $ */
4 * Copyright (c) 2002 ARM Limited
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31 * ARM10 assembly functions for CPU / MMU / TLB specific operations
35 #include <machine/asm.h>
36 __FBSDID("$FreeBSD$");
39 * Functions to set the MMU Translation Table Base register
41 * We need to clean and flush the cache as it uses virtual
42 * addresses that are about to change.
46 bl _C_LABEL(arm10_idcache_wbinv_all)
49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
57 ENTRY(arm10_tlb_flushID_SE)
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
62 ENTRY(arm10_tlb_flushI_SE)
63 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 * Cache operations. For the entire cache we use the set/index
76 ENTRY_NP(arm10_icache_sync_range)
77 ldr ip, .Larm10_line_size
79 bcs .Larm10_icache_sync_all
86 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
87 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 ENTRY_NP(arm10_icache_sync_all)
95 .Larm10_icache_sync_all:
97 * We assume that the code here can never be out of sync with the
98 * dcache, so that we can safely flush the Icache and fall through
99 * into the Dcache cleaning code.
101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
102 /* Fall through to clean Dcache. */
105 ldr ip, .Larm10_cache_data
106 ldmia ip, {s_max, i_max, s_inc, i_inc}
110 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
112 tst ip, i_max /* Index 0 is last one */
113 bne .Lnext_index /* Next index */
114 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
115 subs s_max, s_max, s_inc
116 bpl .Lnext_set /* Next set */
117 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
121 .word _C_LABEL(arm_pdcache_line_size)
123 ENTRY(arm10_dcache_wb_range)
124 ldr ip, .Larm10_line_size
126 bcs .Larm10_dcache_wb
133 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
137 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
140 ENTRY(arm10_dcache_wbinv_range)
141 ldr ip, .Larm10_line_size
143 bcs .Larm10_dcache_wbinv_all
150 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
153 bpl .Larm10_wbinv_next
154 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
158 * Note, we must not invalidate everything. If the range is too big we
159 * must use wb-inv of the entire cache.
161 ENTRY(arm10_dcache_inv_range)
162 ldr ip, .Larm10_line_size
164 bcs .Larm10_dcache_wbinv_all
171 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
175 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
178 ENTRY(arm10_idcache_wbinv_range)
179 ldr ip, .Larm10_line_size
181 bcs .Larm10_idcache_wbinv_all
187 .Larm10_id_wbinv_next:
188 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
189 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
192 bpl .Larm10_id_wbinv_next
193 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
196 ENTRY_NP(arm10_idcache_wbinv_all)
197 .Larm10_idcache_wbinv_all:
199 * We assume that the code here can never be out of sync with the
200 * dcache, so that we can safely flush the Icache and fall through
201 * into the Dcache purging code.
203 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
204 /* Fall through to purge Dcache. */
206 ENTRY(arm10_dcache_wbinv_all)
207 .Larm10_dcache_wbinv_all:
208 ldr ip, .Larm10_cache_data
209 ldmia ip, {s_max, i_max, s_inc, i_inc}
213 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
215 tst ip, i_max /* Index 0 is last one */
216 bne .Lnext_index_inv /* Next index */
217 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
218 subs s_max, s_max, s_inc
219 bpl .Lnext_set_inv /* Next set */
220 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
224 .word _C_LABEL(arm10_dcache_sets_max)
229 * These is the CPU-specific parts of the context switcher cpu_switch()
230 * These functions actually perform the TTB reload.
232 * NOTE: Special calling convention
233 * r1, r4-r13 must be preserved
235 ENTRY(arm10_context_switch)
237 * We can assume that the caches will only contain kernel addresses
238 * at this point. So no need to flush them again.
240 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
241 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
242 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
244 /* Paranoia -- make sure the pipeline is empty. */
252 /* XXX The following macros should probably be moved to asm.h */
253 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
254 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
257 * Parameters for the cache cleaning code. Note that the order of these
258 * four variables is assumed in the code above. Hence the reason for
259 * declaring them in the assembler file.
262 C_OBJECT(arm10_dcache_sets_max)
264 C_OBJECT(arm10_dcache_index_max)
266 C_OBJECT(arm10_dcache_sets_inc)
268 C_OBJECT(arm10_dcache_index_inc)