1 /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
37 #include <machine/asm.h>
38 __FBSDID("$FreeBSD$");
41 * Functions to set the MMU Translation Table Base register
43 * We need to clean and flush the cache as it uses virtual
44 * addresses that are about to change.
48 bl _C_LABEL(armv5_idcache_wbinv_all)
51 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
53 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
54 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
60 ENTRY(arm11_tlb_flushID_SE)
61 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
62 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
63 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
66 ENTRY(arm11_tlb_flushI_SE)
67 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
75 * These is the CPU-specific parts of the context switcher cpu_switch()
76 * These functions actually perform the TTB reload.
78 * NOTE: Special calling convention
79 * r1, r4-r13 must be preserved
81 ENTRY(arm11_context_switch)
83 * We can assume that the caches will only contain kernel addresses
84 * at this point. So no need to flush them again.
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
87 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
88 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
90 /* Paranoia -- make sure the pipeline is empty. */
99 ENTRY(arm11_tlb_flushID)
100 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
101 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
104 ENTRY(arm11_tlb_flushI)
105 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
106 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
109 ENTRY(arm11_tlb_flushD)
110 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
111 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
114 ENTRY(arm11_tlb_flushD_SE)
115 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
116 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
122 ENTRY(arm11_drain_writebuf)
123 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */