1 /* $NetBSD: cpufunc_asm_armv5.S,v 1.3 2007/01/06 00:50:54 christos Exp $ */
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31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports the set/index
36 #include <machine/asm.h>
37 __FBSDID("$FreeBSD$");
40 * Functions to set the MMU Translation Table Base register
42 * We need to clean and flush the cache as it uses virtual
43 * addresses that are about to change.
47 bl _C_LABEL(armv5_idcache_wbinv_all)
50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
56 * Cache operations. For the entire cache we use the set/index
64 ENTRY_NP(armv5_icache_sync_range)
65 ldr ip, .Larmv5_line_size
67 bcs .Larmv5_icache_sync_all
69 sub r1, r1, #1 /* Don't overrun */
75 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
76 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
83 ENTRY_NP(armv5_icache_sync_all)
84 .Larmv5_icache_sync_all:
86 * We assume that the code here can never be out of sync with the
87 * dcache, so that we can safely flush the Icache and fall through
88 * into the Dcache cleaning code.
90 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
91 /* Fall through to clean Dcache. */
94 ldr ip, .Larmv5_cache_data
95 ldmia ip, {s_max, i_max, s_inc, i_inc}
99 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
101 tst ip, i_max /* Index 0 is last one */
102 bne 2b /* Next index */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
104 subs s_max, s_max, s_inc
105 bpl 1b /* Next set */
106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
110 .word _C_LABEL(arm_pdcache_line_size)
112 ENTRY(armv5_dcache_wb_range)
113 ldr ip, .Larmv5_line_size
115 bcs .Larmv5_dcache_wb
117 sub r1, r1, #1 /* Don't overrun */
123 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
127 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
130 ENTRY(armv5_dcache_wbinv_range)
131 ldr ip, .Larmv5_line_size
133 bcs .Larmv5_dcache_wbinv_all
135 sub r1, r1, #1 /* Don't overrun */
141 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
145 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
149 * Note, we must not invalidate everything. If the range is too big we
150 * must use wb-inv of the entire cache.
152 ENTRY(armv5_dcache_inv_range)
153 ldr ip, .Larmv5_line_size
155 bcs .Larmv5_dcache_wbinv_all
157 sub r1, r1, #1 /* Don't overrun */
163 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
167 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
170 ENTRY(armv5_idcache_wbinv_range)
171 ldr ip, .Larmv5_line_size
173 bcs .Larmv5_idcache_wbinv_all
175 sub r1, r1, #1 /* Don't overrun */
181 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
182 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
186 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
189 ENTRY_NP(armv5_idcache_wbinv_all)
190 .Larmv5_idcache_wbinv_all:
192 * We assume that the code here can never be out of sync with the
193 * dcache, so that we can safely flush the Icache and fall through
194 * into the Dcache purging code.
196 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
197 /* Fall through to purge Dcache. */
199 ENTRY(armv5_dcache_wbinv_all)
200 .Larmv5_dcache_wbinv_all:
201 ldr ip, .Larmv5_cache_data
202 ldmia ip, {s_max, i_max, s_inc, i_inc}
206 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
208 tst ip, i_max /* Index 0 is last one */
209 bne 2b /* Next index */
210 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
211 subs s_max, s_max, s_inc
212 bpl 1b /* Next set */
213 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
217 .word _C_LABEL(armv5_dcache_sets_max)
221 /* XXX The following macros should probably be moved to asm.h */
222 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
223 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
226 * Parameters for the cache cleaning code. Note that the order of these
227 * four variables is assumed in the code above. Hence the reason for
228 * declaring them in the assembler file.
231 C_OBJECT(armv5_dcache_sets_max)
233 C_OBJECT(armv5_dcache_index_max)
235 C_OBJECT(armv5_dcache_sets_inc)
237 C_OBJECT(armv5_dcache_index_inc)