1 /* $NetBSD: cpufunc_asm_fa526.S,v 1.3 2008/10/15 16:56:49 matt Exp $*/
3 * Copyright (c) 2008 The NetBSD Foundation, Inc.
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas <matt@3am-software.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD$");
36 #define CACHELINE_SIZE 16
38 #define CACHELINE_SIZE 32
43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
50 /* If we have updated the TTB we must flush the TLB */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
53 /* Make sure that pipeline is emptied */
62 ENTRY(fa526_tlb_flushID_SE)
63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
65 END(fa526_tlb_flushID_SE)
70 ENTRY(fa526_tlb_flushI_SE)
71 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
73 END(fa526_tlb_flushI_SE)
75 ENTRY(fa526_cpu_sleep)
79 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
83 ENTRY(fa526_flush_prefetchbuf)
85 mcr p15, 0, r0, c7, c5, 4 /* Pre-fetch flush */
87 END(fa526_flush_prefetchbuf)
92 ENTRY(fa526_idcache_wbinv_all)
94 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
95 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
96 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
98 END(fa526_idcache_wbinv_all)
100 ENTRY(fa526_icache_sync_all)
102 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
104 END(fa526_icache_sync_all)
106 ENTRY(fa526_dcache_wbinv_all)
108 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
109 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
111 END(fa526_dcache_wbinv_all)
116 ENTRY(fa526_dcache_wbinv_range)
118 bhs _C_LABEL(fa526_dcache_wbinv_all)
120 and r2, r0, #(CACHELINE_SIZE - 1)
122 bic r0, r0, #(CACHELINE_SIZE - 1)
124 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
125 add r0, r0, #CACHELINE_SIZE
126 subs r1, r1, #CACHELINE_SIZE
129 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
131 END(fa526_dcache_wbinv_range)
133 ENTRY(fa526_dcache_wb_range)
138 mcr p15, 0, r0, c7, c10, 0 /* clean entire D$ */
141 1: and r2, r0, #(CACHELINE_SIZE - 1)
143 bic r0, r0, #(CACHELINE_SIZE - 1)
145 2: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
146 add r0, r0, #CACHELINE_SIZE
147 subs r1, r1, #CACHELINE_SIZE
150 3: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
152 END(fa526_dcache_wb_range)
154 ENTRY(fa526_dcache_inv_range)
155 and r2, r0, #(CACHELINE_SIZE - 1)
157 bic r0, r0, #(CACHELINE_SIZE - 1)
159 1: mcr p15, 0, r0, c7, c6, 1 /* invalidate D$ single entry */
160 add r0, r0, #CACHELINE_SIZE
161 subs r1, r1, #CACHELINE_SIZE
165 END(fa526_dcache_inv_range)
167 ENTRY(fa526_idcache_wbinv_range)
169 bhs _C_LABEL(fa526_idcache_wbinv_all)
171 and r2, r0, #(CACHELINE_SIZE - 1)
173 bic r0, r0, #(CACHELINE_SIZE - 1)
175 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
176 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
177 add r0, r0, #CACHELINE_SIZE
178 subs r1, r1, #CACHELINE_SIZE
181 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
183 END(fa526_idcache_wbinv_range)
185 ENTRY(fa526_icache_sync_range)
187 bhs _C_LABEL(fa526_icache_sync_all)
189 and r2, r0, #(CACHELINE_SIZE - 1)
191 bic r0, r0, #(CACHELINE_SIZE - 1)
193 1: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
194 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
195 add r0, r0, #CACHELINE_SIZE
196 subs r1, r1, #CACHELINE_SIZE
199 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
201 END(fa526_icache_sync_range)
203 ENTRY(fa526_flush_brnchtgt_E)
205 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB cache */
207 END(fa526_flush_brnchtgt_E)
209 ENTRY(fa526_context_switch)
211 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
212 * Thus the data cache will contain only kernel data and the
213 * instruction cache will contain only kernel code, and all
214 * kernel mappings are shared by all processes.
217 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
219 /* If we have updated the TTB we must flush the TLB */
221 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
223 /* Make sure that pipeline is emptied */
227 END(fa526_context_switch)