1 /* $NetBSD: cpufunc_asm_fa526.S,v 1.3 2008/10/15 16:56:49 matt Exp $*/
3 * Copyright (c) 2008 The NetBSD Foundation, Inc.
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Matt Thomas <matt@3am-software.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD$");
36 #define CACHELINE_SIZE 16
38 #define CACHELINE_SIZE 32
43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
50 /* If we have updated the TTB we must flush the TLB */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
53 /* Make sure that pipeline is emptied */
61 ENTRY(fa526_tlb_flushID_SE)
62 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
68 ENTRY(fa526_tlb_flushI_SE)
69 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
72 ENTRY(fa526_cpu_sleep)
76 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
79 ENTRY(fa526_flush_prefetchbuf)
81 mcr p15, 0, r0, c7, c5, 4 /* Pre-fetch flush */
87 ENTRY(fa526_idcache_wbinv_all)
89 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
90 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
91 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
94 ENTRY(fa526_icache_sync_all)
96 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
99 ENTRY(fa526_dcache_wbinv_all)
101 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
102 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
108 ENTRY(fa526_dcache_wbinv_range)
110 bhs _C_LABEL(fa526_dcache_wbinv_all)
112 and r2, r0, #(CACHELINE_SIZE - 1)
114 bic r0, r0, #(CACHELINE_SIZE - 1)
116 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
117 add r0, r0, #CACHELINE_SIZE
118 subs r1, r1, #CACHELINE_SIZE
121 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
124 ENTRY(fa526_dcache_wb_range)
129 mcr p15, 0, r0, c7, c10, 0 /* clean entire D$ */
132 1: and r2, r0, #(CACHELINE_SIZE - 1)
134 bic r0, r0, #(CACHELINE_SIZE - 1)
136 2: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
137 add r0, r0, #CACHELINE_SIZE
138 subs r1, r1, #CACHELINE_SIZE
141 3: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
144 ENTRY(fa526_dcache_inv_range)
145 and r2, r0, #(CACHELINE_SIZE - 1)
147 bic r0, r0, #(CACHELINE_SIZE - 1)
149 1: mcr p15, 0, r0, c7, c6, 1 /* invalidate D$ single entry */
150 add r0, r0, #CACHELINE_SIZE
151 subs r1, r1, #CACHELINE_SIZE
156 ENTRY(fa526_idcache_wbinv_range)
158 bhs _C_LABEL(fa526_idcache_wbinv_all)
160 and r2, r0, #(CACHELINE_SIZE - 1)
162 bic r0, r0, #(CACHELINE_SIZE - 1)
164 1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
165 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
166 add r0, r0, #CACHELINE_SIZE
167 subs r1, r1, #CACHELINE_SIZE
170 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
173 ENTRY(fa526_icache_sync_range)
175 bhs _C_LABEL(fa526_icache_sync_all)
177 and r2, r0, #(CACHELINE_SIZE - 1)
179 bic r0, r0, #(CACHELINE_SIZE - 1)
181 1: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
182 mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
183 add r0, r0, #CACHELINE_SIZE
184 subs r1, r1, #CACHELINE_SIZE
187 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
190 ENTRY(fa526_flush_brnchtgt_E)
192 mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB cache */
195 ENTRY(fa526_context_switch)
197 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
198 * Thus the data cache will contain only kernel data and the
199 * instruction cache will contain only kernel code, and all
200 * kernel mappings are shared by all processes.
203 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
205 /* If we have updated the TTB we must flush the TLB */
207 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
209 /* Make sure that pipeline is emptied */