2 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD$");
35 #include <machine/param.h>
42 /* Cache synchronization is not required as this core has PIPT caches */
43 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
45 orr r0, r0, #2 /* Set TTB shared memory flag */
47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
48 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
52 ENTRY(pj4b_drain_readbuf)
53 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
55 END(pj4b_drain_readbuf)
57 ENTRY(pj4b_flush_brnchtgt_all)
58 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
60 END(pj4b_flush_brnchtgt_all)
62 ENTRY(pj4b_flush_brnchtgt_va)
63 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
65 END(pj4b_flush_brnchtgt_va)
68 mrc p15, 0, r0, c0, c0, 5
74 /* Set Auxiliary Debug Modes Control 0 register */
75 mrc p15, 1, r0, c15, c1, 0
76 /* ARMADAXP errata fix: ARM-CPU-6136 */
77 bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */
79 orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */
80 mcr p15, 1, r0, c15, c1, 0
82 /* Set Auxiliary Debug Modes Control 1 register */
83 mrc p15, 1, r0, c15, c1, 1
84 /* ARMADAXP errata fix: ARM-CPU-6409 */
85 bic r0, r0, #(1 << 2) /* Disable static branch prediction */
87 orr r0, r0, #(1 << 5) /* STREX backoff disable */
88 orr r0, r0, #(1 << 8) /* Internal parity handling disable */
89 orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */
90 mcr p15, 1, r0, c15, c1, 1
92 /* Set Auxiliary Function Modes Control 0 register */
93 mrc p15, 1, r0, c15, c2, 0
95 orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */
97 orr r0, r0, #(1 << 2) /* L1 parite enable */
98 orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */
99 mcr p15, 1, r0, c15, c2, 0
101 /* Set Auxiliary Debug Modes Control 2 register */
102 mrc p15, 1, r0, c15, c1, 2
103 bic r0, r0, #(1 << 23) /* Enable fast LDR */
104 orr r0, r0, #(1 << 25) /* Intervention Interleave disable */
105 orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */
106 orr r0, r0, #(1 << 29) /* Disable MO device read / write */
107 orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/
108 orr r0, r0, #(1 << 31) /* Enable write evict */
109 mcr p15, 1, r0, c15, c1, 2
111 /* Set SMP mode in Auxiliary Control Register */
112 mrc p15, 0, r0, c1, c0, 1
113 orr r0, r0, #(1 << 5)
114 mcr p15, 0, r0, c1, c0, 1
117 /* Load CPU number */
118 mrc p15, 0, r0, c0, c0, 5
121 /* SF Enable and invalidate */
122 ldr r1, .Lpj4b_sf_ctrl_reg
123 ldr r2, [r1, r0, lsl #8]
124 orr r2, r2, #(1 << 0)
125 bic r2, r2, #(1 << 8)
126 str r2, [r1, r0, lsl #8]