1 /* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
7 * Written by Allen Briggs and Jason R. Thorpe for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
40 * Copyright (c) 2001 Matt Thomas.
41 * Copyright (c) 1997,1998 Mark Brinicombe.
42 * Copyright (c) 1997 Causality Limited
43 * All rights reserved.
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. All advertising materials mentioning features or use of this software
54 * must display the following acknowledgement:
55 * This product includes software developed by Causality Limited.
56 * 4. The name of Causality Limited may not be used to endorse or promote
57 * products derived from this software without specific prior written
60 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
61 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
62 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
64 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
65 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 * XScale assembly functions for CPU / MMU / TLB specific operations
75 #include <machine/asm.h>
76 __FBSDID("$FreeBSD$");
79 * Size of the XScale core D-cache.
81 #define DCACHE_SIZE 0x00008000
83 .Lblock_userspace_access:
84 .word _C_LABEL(block_userspace_access)
87 * CPWAIT -- Canonical method to wait for CP15 update.
88 * From: Intel 80200 manual, section 2.3.3.
90 * NOTE: Clobbers the specified temp reg.
92 #define CPWAIT_BRANCH \
96 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
97 mov tmp, tmp /* wait for it to complete */ ;\
98 CPWAIT_BRANCH /* branch to next insn */
100 #define CPWAIT_AND_RETURN_SHIFTER lsr #32
102 #define CPWAIT_AND_RETURN(tmp) \
103 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
104 /* Wait for it to complete and branch to the return address */ \
105 sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER
108 CPWAIT_AND_RETURN(r0)
112 * We need a separate cpu_control() entry point, since we have to
113 * invalidate the Branch Target Buffer in the event the BPRD bit
114 * changes in the control register.
116 ENTRY(xscale_control)
117 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
118 bic r2, r3, r0 /* Clear bits */
119 eor r2, r2, r1 /* XOR bits */
121 teq r2, r3 /* Only write if there was a change */
122 mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
123 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
124 mov r0, r3 /* Return old value */
126 CPWAIT_AND_RETURN(r1)
130 * Functions to set the MMU Translation Table Base register
132 * We need to clean and flush the cache as it uses virtual
133 * addresses that are about to change.
136 #ifdef CACHE_CLEAN_BLOCK_INTR
138 orr r1, r3, #(I32_bit | F32_bit)
141 ldr r3, .Lblock_userspace_access
146 stmfd sp!, {r0-r3, lr}
147 bl _C_LABEL(xscale_cache_cleanID)
148 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
149 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
153 ldmfd sp!, {r0-r3, lr}
156 mcr p15, 0, r0, c2, c0, 0
158 /* If we have updated the TTB we must flush the TLB */
159 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
161 /* The cleanID above means we only need to flush the I cache here */
162 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
166 #ifdef CACHE_CLEAN_BLOCK_INTR
178 ENTRY(xscale_tlb_flushID_SE)
179 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
180 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
181 CPWAIT_AND_RETURN(r0)
182 END(xscale_tlb_flushID_SE)
187 ENTRY(xscale_cache_flushID)
188 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
189 CPWAIT_AND_RETURN(r0)
190 END(xscale_cache_flushID)
192 ENTRY(xscale_cache_flushI)
193 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
194 CPWAIT_AND_RETURN(r0)
195 END(xscale_cache_flushI)
197 ENTRY(xscale_cache_flushD)
198 mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
199 CPWAIT_AND_RETURN(r0)
200 END(xscale_cache_flushD)
202 ENTRY(xscale_cache_flushI_SE)
203 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
204 CPWAIT_AND_RETURN(r0)
205 END(xscale_cache_flushI_SE)
207 ENTRY(xscale_cache_flushD_SE)
209 * Errata (rev < 2): Must clean-dcache-line to an address
210 * before invalidate-dcache-line to an address, or dirty
211 * bits will not be cleared in the dcache array.
213 mcr p15, 0, r0, c7, c10, 1
214 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
215 CPWAIT_AND_RETURN(r0)
216 END(xscale_cache_flushD_SE)
218 ENTRY(xscale_cache_cleanD_E)
219 mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
220 CPWAIT_AND_RETURN(r0)
221 END(xscale_cache_cleanD_E)
224 * Information for the XScale cache clean/purge functions:
226 * * Virtual address of the memory region to use
227 * * Size of memory region
229 * Note the virtual address for the Data cache clean operation
230 * does not need to be backed by physical memory, since no loads
231 * will actually be performed by the allocate-line operation.
233 * Note that the Mini-Data cache MUST be cleaned by executing
234 * loads from memory mapped into a region reserved exclusively
235 * for cleaning of the Mini-Data cache.
239 .global _C_LABEL(xscale_cache_clean_addr)
240 _C_LABEL(xscale_cache_clean_addr):
243 .global _C_LABEL(xscale_cache_clean_size)
244 _C_LABEL(xscale_cache_clean_size):
247 .global _C_LABEL(xscale_minidata_clean_addr)
248 _C_LABEL(xscale_minidata_clean_addr):
251 .global _C_LABEL(xscale_minidata_clean_size)
252 _C_LABEL(xscale_minidata_clean_size):
257 .Lxscale_cache_clean_addr:
258 .word _C_LABEL(xscale_cache_clean_addr)
259 .Lxscale_cache_clean_size:
260 .word _C_LABEL(xscale_cache_clean_size)
262 .Lxscale_minidata_clean_addr:
263 .word _C_LABEL(xscale_minidata_clean_addr)
264 .Lxscale_minidata_clean_size:
265 .word _C_LABEL(xscale_minidata_clean_size)
267 #ifdef CACHE_CLEAN_BLOCK_INTR
268 #define XSCALE_CACHE_CLEAN_BLOCK \
270 orr r0, r3, #(I32_bit | F32_bit) ; \
273 #define XSCALE_CACHE_CLEAN_UNBLOCK \
276 #define XSCALE_CACHE_CLEAN_BLOCK \
277 ldr r3, .Lblock_userspace_access ; \
282 #define XSCALE_CACHE_CLEAN_UNBLOCK \
284 #endif /* CACHE_CLEAN_BLOCK_INTR */
286 #define XSCALE_CACHE_CLEAN_PROLOGUE \
287 XSCALE_CACHE_CLEAN_BLOCK ; \
288 ldr r2, .Lxscale_cache_clean_addr ; \
289 ldmia r2, {r0, r1} ; \
293 * The XScale core has a strange cache eviction bug, which \
294 * requires us to use 2x the cache size for the cache clean \
295 * and for that area to be aligned to 2 * cache size. \
297 * The work-around is to use 2 areas for cache clean, and to \
298 * alternate between them whenever this is done. No one knows \
299 * why the work-around works (mmm!). \
301 eor r0, r0, #(DCACHE_SIZE) ; \
305 #define XSCALE_CACHE_CLEAN_EPILOGUE \
306 XSCALE_CACHE_CLEAN_UNBLOCK
308 ENTRY_NP(xscale_cache_syncI)
309 ENTRY_NP(xscale_cache_purgeID)
310 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
311 ENTRY_NP(xscale_cache_cleanID)
312 ENTRY_NP(xscale_cache_purgeD)
313 ENTRY(xscale_cache_cleanD)
314 XSCALE_CACHE_CLEAN_PROLOGUE
317 mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */
323 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
327 XSCALE_CACHE_CLEAN_EPILOGUE
329 END(xscale_cache_syncI)
330 END(xscale_cache_purgeID)
331 END(xscale_cache_cleanID)
332 END(xscale_cache_purgeD)
333 END(xscale_cache_cleanD)
336 * Clean the mini-data cache.
338 * It's expected that we only use the mini-data cache for
339 * kernel addresses, so there is no need to purge it on
340 * context switch, and no need to prevent userspace access
343 ENTRY(xscale_cache_clean_minidata)
344 ldr r2, .Lxscale_minidata_clean_addr
350 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
352 CPWAIT_AND_RETURN(r1)
353 END(xscale_cache_clean_minidata)
355 ENTRY(xscale_cache_purgeID_E)
356 mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
358 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
359 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
360 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
361 CPWAIT_AND_RETURN(r1)
362 END(xscale_cache_purgeID_E)
364 ENTRY(xscale_cache_purgeD_E)
365 mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
367 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
368 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
369 CPWAIT_AND_RETURN(r1)
370 END(xscale_cache_purgeD_E)
375 /* xscale_cache_syncI is identical to xscale_cache_purgeID */
377 ENTRY(xscale_cache_cleanID_rng)
378 ENTRY(xscale_cache_cleanD_rng)
380 bcs _C_LABEL(xscale_cache_cleanID)
386 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
393 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
395 CPWAIT_AND_RETURN(r0)
396 END(xscale_cache_cleanID_rng)
397 END(xscale_cache_cleanD_rng)
399 ENTRY(xscale_cache_purgeID_rng)
401 bcs _C_LABEL(xscale_cache_purgeID)
407 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
408 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
409 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
416 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
418 CPWAIT_AND_RETURN(r0)
419 END(xscale_cache_purgeID_rng)
421 ENTRY(xscale_cache_purgeD_rng)
423 bcs _C_LABEL(xscale_cache_purgeD)
429 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
430 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
437 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
439 CPWAIT_AND_RETURN(r0)
440 END(xscale_cache_purgeD_rng)
442 ENTRY(xscale_cache_syncI_rng)
444 bcs _C_LABEL(xscale_cache_syncI)
450 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
451 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
458 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
460 CPWAIT_AND_RETURN(r0)
461 END(xscale_cache_syncI_rng)
463 ENTRY(xscale_cache_flushD_rng)
468 1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
473 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
475 CPWAIT_AND_RETURN(r0)
476 END(xscale_cache_flushD_rng)
481 * These is the CPU-specific parts of the context switcher cpu_switch()
482 * These functions actually perform the TTB reload.
484 * NOTE: Special calling convention
485 * r1, r4-r13 must be preserved
487 ENTRY(xscale_context_switch)
489 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
490 * Thus the data cache will contain only kernel data and the
491 * instruction cache will contain only kernel code, and all
492 * kernel mappings are shared by all processes.
496 mcr p15, 0, r0, c2, c0, 0
498 /* If we have updated the TTB we must flush the TLB */
499 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
501 CPWAIT_AND_RETURN(r0)
502 END(xscale_context_switch)
507 * This is called when there is nothing on any of the run queues.
508 * We go into IDLE mode so that any IRQ or FIQ will awaken us.
510 * If this is called with anything other than ARM_SLEEP_MODE_IDLE,
513 ENTRY(xscale_cpu_sleep)
517 mcr p14, 0, r0, c7, c0, 0
521 END(xscale_cpu_sleep)