2 * Copyright 2004-2014 Olivier Houchard <cognet@FreeBSD.org>
3 * Copyright 2012-2014 Ian Lepore <ian@FreeBSD.org>
4 * Copyright 2013-2014 Andrew Turner <andrew@FreeBSD.org>
5 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
6 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/syscall.h>
33 #include <machine/asm.h>
34 #include <machine/asmacros.h>
35 #include <machine/armreg.h>
36 #include <machine/sysreg.h>
37 #include <machine/cpuconf.h>
38 #include <machine/pte.h>
40 __FBSDID("$FreeBSD$");
43 #define PTE1_OFFSET L1_S_OFFSET
44 #define PTE1_SHIFT L1_S_SHIFT
45 #define PTE1_SIZE L1_S_SIZE
48 /* A small statically-allocated stack used only during initarm() and AP startup. */
49 #define INIT_ARM_STACK_SIZE 2048
55 * On entry for FreeBSD boot ABI:
56 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
57 * r1 - if (r0 == 0) then metadata pointer
58 * On entry for Linux boot ABI:
60 * r1 - machine type (passed as arg2 to initarm)
61 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
63 * For both types of boot we gather up the args, put them in a struct arm_boot_params
64 * structure and pass that to initarm.
69 STOP_UNWINDING /* Can't unwind into the bootloader! */
71 /* Make sure interrupts are disabled. */
74 mov r8, r0 /* 0 or boot mode from boot2 */
75 mov r9, r1 /* Save Machine type */
76 mov r10, r2 /* Save meta data */
77 mov r11, r3 /* Future expansion */
80 * Check whether data cache is enabled. If it is, then we know
81 * current tags are valid (not power-on garbage values) and there
82 * might be dirty lines that need cleaning. Disable cache to prevent
83 * new lines being allocated, then call wbinv_poc_all to clean it.
86 tst r7, #CPU_CONTROL_DC_ENABLE
87 blne dcache_wbinv_poc_all
89 /* ! Do not write to memory between wbinv and disabling cache ! */
92 * Now there are no dirty lines, but there may still be lines marked
93 * valid. Disable all caches and the MMU, and invalidate everything
94 * before setting up new page tables and re-enabling the mmu.
97 bic r7, #CPU_CONTROL_DC_ENABLE
98 bic r7, #CPU_CONTROL_MMU_ENABLE
99 bic r7, #CPU_CONTROL_IC_ENABLE
100 bic r7, #CPU_CONTROL_UNAL_ENABLE
101 bic r7, #CPU_CONTROL_BPRD_ENABLE
102 bic r7, #CPU_CONTROL_SW_ENABLE
103 orr r7, #CPU_CONTROL_AFLT_ENABLE
104 orr r7, #CPU_CONTROL_VECRELOC
108 bl dcache_inv_poc_all
114 * Build page table from scratch.
118 * Figure out the physical address we're loaded at by assuming this
119 * entry point code is in the first L1 section and so if we clear the
120 * offset bits of the pc that will give us the section-aligned load
121 * address, which remains in r5 throughout all the following code.
123 ldr r2, =(L1_S_OFFSET)
126 /* Find the delta between VA and PA, result stays in r0 throughout. */
128 bl translate_va_to_pa
131 * First map the entire 4GB address space as VA=PA. It's mapped as
132 * normal (cached) memory because it's for things like accessing the
133 * parameters passed in from the bootloader, which might be at any
134 * physical address, different for every platform.
142 * Next we do 64MiB starting at the physical load address, mapped to
143 * the VA the kernel is linked for.
146 ldr r2, =(KERNVIRTADDR)
150 /* Create a device mapping for early_printf if specified. */
151 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
155 bl build_device_pagetables
159 /* Transition the PC from physical to virtual addressing. */
163 /* Setup stack, clear BSS */
165 ldmia r1, {r1, r2, sp} /* Set initial stack and */
166 add sp, sp, #INIT_ARM_STACK_SIZE
167 sub r2, r2, r1 /* get zero init data */
170 str r3, [r1], #0x0004 /* get zero init data */
174 mov r1, #28 /* loader info size is 28 bytes also second arg */
175 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
176 mov r0, sp /* loader info pointer is first arg */
177 bic sp, sp, #7 /* align stack to 8 bytes */
178 str r1, [r0] /* Store length of loader info */
179 str r8, [r0, #4] /* Store r0 from boot loader */
180 str r9, [r0, #8] /* Store r1 from boot loader */
181 str r10, [r0, #12] /* store r2 from boot loader */
182 str r11, [r0, #16] /* store r3 from boot loader */
183 str r5, [r0, #20] /* store the physical address */
184 adr r4, Lpagetable /* load the pagetable address */
186 str r5, [r0, #24] /* store the pagetable address */
187 mov fp, #0 /* trace back starts here */
188 bl _C_LABEL(initarm) /* Off we go */
190 /* init arm will return the new stack pointer. */
193 bl _C_LABEL(mi_startup) /* call mi_startup()! */
195 ldr r0, =.Lmainreturned
200 #define VA_TO_PA_POINTER(name, table) \
206 * Returns the physical address of a magic va to pa pointer.
207 * r0 - The pagetable data pointer. This must be built using the
208 * VA_TO_PA_POINTER macro.
210 * VA_TO_PA_POINTER(Lpagetable, pagetable)
213 * bl translate_va_to_pa
214 * r0 will now contain the physical address of pagetable
220 /* At this point: r2 = VA - PA */
223 * Find the physical address of the table. After these two
227 * r0 = va(pagetable) - (VA - PA)
228 * = va(pagetable) - VA + PA
237 * r0 - the table base address
242 /* Setup TLB and MMU registers */
243 mcr CP15_TTBR0(r0) /* Set TTB */
245 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */
247 /* Set the Domain Access register */
248 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
253 * Set TEX remap registers
254 * - All is set to uncacheable memory
261 mcr CP15_TLBIALL /* Flush TLB */
267 orr r0, r0, #CPU_CONTROL_MMU_ENABLE
268 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
270 orr r0, r0, #CPU_CONTROL_TR_ENABLE
272 orr r0, r0, #CPU_CONTROL_AF_ENABLE
276 mcr CP15_TLBIALL /* Flush TLB */
277 mcr CP15_BPIALL /* Flush Branch predictor */
286 * Init SMP coherent mode, enable caching and switch to final MMU table.
287 * Called with disabled caches
288 * r0 - The table base address
289 * r1 - clear bits for aux register
290 * r2 - set bits for aux register
292 ASENTRY_NP(reinit_mmu)
298 /* !! Be very paranoid here !! */
299 /* !! We cannot write single bit here !! */
301 #if 0 /* XXX writeback shouldn't be necessary */
302 /* Write back and invalidate all integrated caches */
303 bl dcache_wbinv_poc_all
305 bl dcache_inv_pou_all
311 /* Set auxiliary register */
313 bic r8, r7, r5 /* Mask bits */
314 eor r8, r8, r6 /* Set bits */
322 orr r7, #CPU_CONTROL_DC_ENABLE
323 orr r7, #CPU_CONTROL_IC_ENABLE
324 orr r7, #CPU_CONTROL_BPRD_ENABLE
328 mcr CP15_TTBR0(r4) /* Set new TTB */
332 mcr CP15_TLBIALL /* Flush TLB */
333 mcr CP15_BPIALL /* Flush Branch predictor */
337 #if 0 /* XXX writeback shouldn't be necessary */
338 /* Write back and invalidate all integrated caches */
339 bl dcache_wbinv_poc_all
341 bl dcache_inv_pou_all
352 * Builds the page table
353 * r0 - The table base address
354 * r1 - The physical address (trashed)
355 * r2 - The virtual address (trashed)
356 * r3 - The number of 1MiB sections
359 * Addresses must be 1MiB aligned
361 build_device_pagetables:
362 #if defined(ARM_NEW_PMAP)
363 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
365 ldr r4, =(L1_TYPE_S|L1_S_AP(AP_KRW)|L1_SHARED)
367 ldr r4, =(L1_TYPE_S|L1_S_AP(AP_KRW))
371 /* Set the required page attributed */
372 #if defined(ARM_NEW_PMAP)
373 ldr r4, =PTE1_V|PTE1_A|PTE1_AP_KRW|TEX1_CLASS_0
375 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)|L1_SHARED)
377 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
382 /* Move the virtual address to the correct bit location */
383 lsr r2, #(PTE1_SHIFT - 2)
389 add r1, r1, #(PTE1_SIZE)
395 VA_TO_PA_POINTER(Lpagetable, boot_pt1)
399 .word _edata /* Note that these three items are */
400 .word _ebss /* loaded with a single ldmia and */
401 .word svcstk /* must remain in order together. */
404 .asciz "main() returned"
409 .space INIT_ARM_STACK_SIZE * MAXCPU
412 * Memory for the initial pagetable. We are unable to place this in
413 * the bss as this will be cleared after the table is loaded.
415 .section ".init_pagetable"
416 .align 14 /* 16KiB aligned */
425 .word _C_LABEL(cpufuncs)
430 /* Make sure interrupts are disabled. */
433 /* Setup core, disable all caches. */
435 bic r0, #CPU_CONTROL_MMU_ENABLE
436 bic r0, #CPU_CONTROL_DC_ENABLE
437 bic r0, #CPU_CONTROL_IC_ENABLE
438 bic r0, #CPU_CONTROL_UNAL_ENABLE
439 bic r0, #CPU_CONTROL_BPRD_ENABLE
440 bic r0, #CPU_CONTROL_SW_ENABLE
441 orr r0, #CPU_CONTROL_AFLT_ENABLE
442 orr r0, #CPU_CONTROL_VECRELOC
447 /* Invalidate L1 cache I+D cache */
448 bl dcache_inv_pou_all
453 /* Find the delta between VA and PA */
455 bl translate_va_to_pa
459 adr r1, .Lstart+8 /* Get initstack pointer from */
460 ldr sp, [r1] /* startup data. */
461 mrc CP15_MPIDR(r0) /* Get processor id number. */
463 mov r1, #INIT_ARM_STACK_SIZE
464 mul r2, r1, r0 /* Point sp to initstack */
465 add sp, sp, r2 /* area for this processor. */
467 /* Switch to virtual addresses. */
470 mov fp, #0 /* trace back starts here */
471 bl _C_LABEL(init_secondary)/* Off we go, cpu id in r0. */
479 .asciz "init_secondary() returned"
485 /* XXX re-implement !!! */
487 bl dcache_wbinv_poc_all
489 ldr r4, .Lcpu_reset_address
498 * _cpu_reset_address contains the address to branch to, to complete
499 * the cpu reset after turning the MMU off
500 * This variable is provided by the hardware specific code
503 .word _C_LABEL(cpu_reset_address)
523 .global _C_LABEL(esym)
524 _C_LABEL(esym): .word _C_LABEL(end)
535 * Call the sigreturn system call.
537 * We have to load r7 manually rather than using
538 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
539 * correct. Using the alternative places esigcode at the address
540 * of the data rather than the address one past the data.
543 ldr r7, [pc, #12] /* Load SYS_sigreturn */
546 /* Well if that failed we better exit quick ! */
548 ldr r7, [pc, #8] /* Load SYS_exit */
551 /* Branch back to retry SYS_sigreturn */
558 .global _C_LABEL(esigcode)
564 .long esigcode-sigcode
566 /* End of locore.S */