1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright 2011 Semihalf
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Brini.
20 * 4. The name of Brini may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <sys/syscall.h>
38 #include <machine/asm.h>
39 #include <machine/armreg.h>
40 #include <machine/pte.h>
42 __FBSDID("$FreeBSD$");
44 /* What size should this really be ? It is only used by initarm() */
45 #define INIT_ARM_STACK_SIZE (2048 * 4)
47 #define CPWAIT_BRANCH \
51 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
52 mov tmp, tmp /* wait for it to complete */ ;\
53 CPWAIT_BRANCH /* branch to next insn */
56 * This is for kvm_mkdb, and should be the address of the beginning
57 * of the kernel text segment (not necessarily the same as kernbase).
62 .set kernbase,KERNBASE
64 .set physaddr,PHYSADDR
67 * On entry for FreeBSD boot ABI:
68 * r0 - metadata pointer or 0 (boothowto on AT91's boot2)
69 * r1 - if (r0 == 0) then metadata pointer
70 * On entry for Linux boot ABI:
72 * r1 - machine type (passed as arg2 to initarm)
73 * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm)
75 * For both types of boot we gather up the args, put them in a struct arm_boot_params
76 * structure and pass that to initarm.
80 STOP_UNWINDING /* Can't unwind into the bootloader! */
82 mov r9, r0 /* 0 or boot mode from boot2 */
83 mov r8, r1 /* Save Machine type */
84 mov ip, r2 /* Save meta data */
85 mov fp, r3 /* Future expantion */
87 /* Make sure interrupts are disabled. */
89 orr r7, r7, #(I32_bit|F32_bit)
92 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
93 /* Check if we're running from flash. */
96 * If we're running with MMU disabled, test against the
97 * physical address instead.
99 mrc p15, 0, r2, c1, c0, 0
100 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
102 ldrne r6, =LOADERRAMADDR
124 Lram_offset: .word from_ram-_C_LABEL(_start)
129 bic r7, r7, #0xf0000000
130 orr r7, r7, #PHYSADDR
134 /* Disable MMU for a while */
135 mrc p15, 0, r2, c1, c0, 0
136 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
137 CPU_CONTROL_WBUF_ENABLE)
138 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
139 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
140 mcr p15, 0, r2, c1, c0, 0
148 * Build page table from scratch.
151 /* Load the page tables physical address */
152 ldr r1, Lstartup_pagetable
153 ldr r2, =(KERNVIRTADDR - KERNPHYSADDR)
162 /* Map 64MiB, preserved over calls to build_pagetables */
166 /* Create the kernel map to jump to */
171 #if defined(SOCDEV_PA) && defined(SOCDEV_VA)
172 /* Create the custom map */
179 orr r0, r0, #2 /* Set TTB shared memory flag */
181 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
182 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
184 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
186 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
189 /* Set the Domain Access register. Very important! */
190 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
191 mcr p15, 0, r0, c3, c0, 0
194 * On armv6 enable extended page tables, and set alignment checking
195 * to modulo-4 (CPU_CONTROL_UNAL_ENABLE) for the ldrd/strd
196 * instructions emitted by clang.
198 mrc p15, 0, r0, c1, c0, 0
200 orr r0, r0, #(CPU_CONTROL_V6_EXTPAGE | CPU_CONTROL_UNAL_ENABLE)
201 orr r0, r0, #(CPU_CONTROL_AFLT_ENABLE)
202 orr r0, r0, #(CPU_CONTROL_AF_ENABLE)
204 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE)
205 mcr p15, 0, r0, c1, c0, 0
214 ldmia r1, {r1, r2, sp} /* Set initial stack and */
215 sub r2, r2, r1 /* get zero init data */
218 str r3, [r1], #0x0004 /* get zero init data */
224 mov r1, #24 /* loader info size is 24 bytes also second arg */
225 subs sp, sp, r1 /* allocate arm_boot_params struct on stack */
226 bic sp, sp, #7 /* align stack to 8 bytes */
227 mov r0, sp /* loader info pointer is first arg */
228 str r1, [r0] /* Store length of loader info */
229 str r9, [r0, #4] /* Store r0 from boot loader */
230 str r8, [r0, #8] /* Store r1 from boot loader */
231 str ip, [r0, #12] /* store r2 from boot loader */
232 str fp, [r0, #16] /* store r3 from boot loader */
233 ldr r5, =KERNPHYSADDR /* load KERNPHYSADDR as the physical address */
234 str r5, [r0, #20] /* store the physical address */
235 mov fp, #0 /* trace back starts here */
236 bl _C_LABEL(initarm) /* Off we go */
238 /* init arm will return the new stack pointer. */
241 bl _C_LABEL(mi_startup) /* call mi_startup()! */
243 adr r0, .Lmainreturned
250 * Builds the page table
251 * r0 - The table base address
252 * r1 - The physical address (trashed)
253 * r2 - The virtual address (trashed)
254 * r3 - The number of 1MiB sections
257 * Addresses must be 1MiB aligned
260 /* Set the required page attributed */
261 ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
267 /* Move the virtual address to the correct bit location */
268 lsr r2, #(L1_S_SHIFT - 2)
274 add r1, r1, #(L1_S_SIZE)
280 #define MMU_INIT(va,pa,n_sec,attr) \
282 .word 4*((va)>>L1_S_SHIFT) ; \
296 Lstartup_pagetable_secondary:
303 .word svcstk + INIT_ARM_STACK_SIZE
313 .asciz "main() returned"
318 .space INIT_ARM_STACK_SIZE
321 * Memory for the initial pagetable. We are unable to place this in
322 * the bss as this will be cleared after the table is loaded.
324 .section ".init_pagetable"
325 .align 14 /* 16KiB aligned */
333 .word _C_LABEL(cpufuncs)
340 #define AP_DEBUG(tmp) \
341 mrc p15, 0, r1, c0, c0, 5; \
343 add r0, r1, lsl #2; \
345 str r1, [r0], #0x0000;
347 #define AP_DEBUG(tmp)
353 mcr p15, 0, r0, c7, c7, 0
358 bic r3, r3, #(PSR_MODE)
359 orr r3, r3, #(PSR_SVC32_MODE)
362 mrc p15, 0, r0, c0, c0, 5
363 and r0, #0x0f /* Get CPU ID */
365 /* Read boot address for CPU */
382 /* Make sure interrupts are disabled. */
384 orr r7, r7, #(I32_bit|F32_bit)
389 bic r7, r7, #0xf0000000
390 orr r7, r7, #PHYSADDR
392 /* Disable MMU for a while */
393 mrc p15, 0, r2, c1, c0, 0
394 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
395 CPU_CONTROL_WBUF_ENABLE)
396 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
397 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
398 mcr p15, 0, r2, c1, c0, 0
407 ldr r0, Lstartup_pagetable_secondary
408 bic r0, r0, #0xf0000000
409 orr r0, r0, #PHYSADDR
412 orr r0, r0, #0 /* Set TTB shared memory flag */
414 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
415 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
417 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
419 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
424 /* Set the Domain Access register. Very important! */
425 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
426 mcr p15, 0, r0, c3, c0, 0
428 mrc p15, 0, r0, c1, c0, 0
429 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
430 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
431 orr r0, r0, #CPU_CONTROL_AF_ENABLE
433 orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
434 mcr p15, 0, r0, c1, c0, 0
441 ldmia r1, {r1, r2, sp} /* Set initial stack and */
442 mrc p15, 0, r0, c0, c0, 5
448 ldr pc, .Lmpvirt_done
452 mov fp, #0 /* trace back starts here */
453 bl _C_LABEL(init_secondary) /* Off we go */
460 .asciz "main() returned"
467 bic r2, r2, #(PSR_MODE)
468 orr r2, r2, #(PSR_SVC32_MODE)
469 orr r2, r2, #(I32_bit | F32_bit)
472 ldr r4, .Lcpu_reset_address
477 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
479 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
482 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
486 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
492 * MMU & IDC off, 32 bit program & data space
493 * Hurl ourselves into the ROM
495 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
496 mcr 15, 0, r0, c1, c0, 0
497 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
501 * _cpu_reset_address contains the address to branch to, to complete
502 * the cpu reset after turning the MMU off
503 * This variable is provided by the hardware specific code
506 .word _C_LABEL(cpu_reset_address)
509 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
510 * v4 MMU disable instruction needs executing... it is an illegal instruction
511 * on f.e. ARM6/7 that locks up the computer in an endless illegal
512 * instruction / data-abort / reset loop.
514 .Lcpu_reset_needs_v4_MMU_disable:
515 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
535 .global _C_LABEL(esym)
536 _C_LABEL(esym): .word _C_LABEL(end)
546 * Call the sigreturn system call.
548 * We have to load r7 manually rather than using
549 * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is
550 * correct. Using the alternative places esigcode at the address
551 * of the data rather than the address one past the data.
554 ldr r7, [pc, #12] /* Load SYS_sigreturn */
557 /* Well if that failed we better exit quick ! */
559 ldr r7, [pc, #8] /* Load SYS_exit */
562 /* Branch back to retry SYS_sigreturn */
569 .global _C_LABEL(esigcode)
575 .long esigcode-sigcode
577 /* End of locore.S */