1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependant vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 /* Include header files */
142 #include <sys/cdefs.h>
143 __FBSDID("$FreeBSD$");
144 #include <sys/param.h>
145 #include <sys/systm.h>
146 #include <sys/kernel.h>
148 #include <sys/proc.h>
149 #include <sys/malloc.h>
150 #include <sys/msgbuf.h>
151 #include <sys/vmmeter.h>
152 #include <sys/mman.h>
154 #include <sys/sched.h>
157 #include <vm/vm_param.h>
160 #include <vm/vm_kern.h>
161 #include <vm/vm_object.h>
162 #include <vm/vm_map.h>
163 #include <vm/vm_page.h>
164 #include <vm/vm_pageout.h>
165 #include <vm/vm_extern.h>
166 #include <sys/lock.h>
167 #include <sys/mutex.h>
168 #include <machine/md_var.h>
169 #include <machine/cpu.h>
170 #include <machine/cpufunc.h>
171 #include <machine/pcb.h>
174 #define PDEBUG(_lev_,_stat_) \
175 if (pmap_debug_level >= (_lev_)) \
177 #define dprintf printf
179 int pmap_debug_level = 0;
181 #else /* PMAP_DEBUG */
182 #define PDEBUG(_lev_,_stat_) /* Nothing */
183 #define dprintf(x, arg...)
184 #define PMAP_INLINE __inline
185 #endif /* PMAP_DEBUG */
187 extern struct pv_addr systempage;
189 * Internal function prototypes
191 static void pmap_free_pv_entry (pv_entry_t);
192 static pv_entry_t pmap_get_pv_entry(void);
194 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
195 vm_prot_t, boolean_t, int);
196 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
197 static void pmap_alloc_l1(pmap_t);
198 static void pmap_free_l1(pmap_t);
200 static int pmap_clearbit(struct vm_page *, u_int);
202 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
203 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
204 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
205 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
207 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
209 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
210 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
211 vm_offset_t pmap_curmaxkvaddr;
212 vm_paddr_t kernel_l1pa;
215 vm_offset_t kernel_vm_end = 0;
217 struct pmap kernel_pmap_store;
219 static pt_entry_t *csrc_pte, *cdst_pte;
220 static vm_offset_t csrcp, cdstp;
221 static struct mtx cmtx;
223 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
225 * These routines are called when the CPU type is identified to set up
226 * the PTE prototypes, cache modes, etc.
228 * The variables are always here, just in case LKMs need to reference
229 * them (though, they shouldn't).
232 pt_entry_t pte_l1_s_cache_mode;
233 pt_entry_t pte_l1_s_cache_mode_pt;
234 pt_entry_t pte_l1_s_cache_mask;
236 pt_entry_t pte_l2_l_cache_mode;
237 pt_entry_t pte_l2_l_cache_mode_pt;
238 pt_entry_t pte_l2_l_cache_mask;
240 pt_entry_t pte_l2_s_cache_mode;
241 pt_entry_t pte_l2_s_cache_mode_pt;
242 pt_entry_t pte_l2_s_cache_mask;
244 pt_entry_t pte_l2_s_prot_u;
245 pt_entry_t pte_l2_s_prot_w;
246 pt_entry_t pte_l2_s_prot_mask;
248 pt_entry_t pte_l1_s_proto;
249 pt_entry_t pte_l1_c_proto;
250 pt_entry_t pte_l2_s_proto;
252 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
253 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
254 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
256 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
258 * Which pmap is currently 'live' in the cache
260 * XXXSCW: Fix for SMP ...
262 union pmap_cache_state *pmap_cache_state;
264 struct msgbuf *msgbufp = 0;
269 static caddr_t crashdumpmap;
271 extern void bcopy_page(vm_offset_t, vm_offset_t);
272 extern void bzero_page(vm_offset_t);
274 extern vm_offset_t alloc_firstaddr;
279 * Metadata for L1 translation tables.
282 /* Entry on the L1 Table list */
283 SLIST_ENTRY(l1_ttable) l1_link;
285 /* Entry on the L1 Least Recently Used list */
286 TAILQ_ENTRY(l1_ttable) l1_lru;
288 /* Track how many domains are allocated from this L1 */
289 volatile u_int l1_domain_use_count;
292 * A free-list of domain numbers for this L1.
293 * We avoid using ffs() and a bitmap to track domains since ffs()
296 u_int8_t l1_domain_first;
297 u_int8_t l1_domain_free[PMAP_DOMAINS];
299 /* Physical address of this L1 page table */
300 vm_paddr_t l1_physaddr;
302 /* KVA of this L1 page table */
307 * Convert a virtual address into its L1 table index. That is, the
308 * index used to locate the L2 descriptor table pointer in an L1 table.
309 * This is basically used to index l1->l1_kva[].
311 * Each L2 descriptor table represents 1MB of VA space.
313 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
316 * L1 Page Tables are tracked using a Least Recently Used list.
317 * - New L1s are allocated from the HEAD.
318 * - Freed L1s are added to the TAIl.
319 * - Recently accessed L1s (where an 'access' is some change to one of
320 * the userland pmaps which owns this L1) are moved to the TAIL.
322 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
324 * A list of all L1 tables
326 static SLIST_HEAD(, l1_ttable) l1_list;
327 static struct mtx l1_lru_lock;
330 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
332 * This is normally 16MB worth L2 page descriptors for any given pmap.
333 * Reference counts are maintained for L2 descriptors so they can be
337 /* The number of L2 page descriptors allocated to this l2_dtable */
340 /* List of L2 page descriptors */
342 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
343 vm_paddr_t l2b_phys; /* Physical address of same */
344 u_short l2b_l1idx; /* This L2 table's L1 index */
345 u_short l2b_occupancy; /* How many active descriptors */
346 } l2_bucket[L2_BUCKET_SIZE];
349 /* pmap_kenter_internal flags */
350 #define KENTER_CACHE 0x1
351 #define KENTER_USER 0x2
354 * Given an L1 table index, calculate the corresponding l2_dtable index
355 * and bucket index within the l2_dtable.
357 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
359 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
362 * Given a virtual address, this macro returns the
363 * virtual address required to drop into the next L2 bucket.
365 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
370 #define pmap_alloc_l2_dtable() \
371 (void*)uma_zalloc(l2table_zone, M_NOWAIT|M_USE_RESERVE)
372 #define pmap_free_l2_dtable(l2) \
373 uma_zfree(l2table_zone, l2)
376 * We try to map the page tables write-through, if possible. However, not
377 * all CPUs have a write-through cache mode, so on those we have to sync
378 * the cache when we frob page tables.
380 * We try to evaluate this at compile time, if possible. However, it's
381 * not always possible to do that, hence this run-time var.
383 int pmap_needs_pte_sync;
386 * Macro to determine if a mapping might be resident in the
387 * instruction cache and/or TLB
389 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
392 * Macro to determine if a mapping might be resident in the
393 * data cache and/or TLB
395 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
397 #ifndef PMAP_SHPGPERPROC
398 #define PMAP_SHPGPERPROC 200
401 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
402 curproc->p_vmspace->vm_map.pmap == (pm))
403 static uma_zone_t pvzone = NULL;
405 static uma_zone_t l2table_zone;
406 static vm_offset_t pmap_kernel_l2dtable_kva;
407 static vm_offset_t pmap_kernel_l2ptp_kva;
408 static vm_paddr_t pmap_kernel_l2ptp_phys;
409 static struct vm_object pvzone_obj;
410 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
412 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
413 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
414 #if ARM_MMU_XSCALE == 1
415 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
416 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
420 * This list exists for the benefit of pmap_map_chunk(). It keeps track
421 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
422 * find them as necessary.
424 * Note that the data on this list MUST remain valid after initarm() returns,
425 * as pmap_bootstrap() uses it to contruct L2 table metadata.
427 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
430 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
435 l1->l1_domain_use_count = 0;
436 l1->l1_domain_first = 0;
438 for (i = 0; i < PMAP_DOMAINS; i++)
439 l1->l1_domain_free[i] = i + 1;
442 * Copy the kernel's L1 entries to each new L1.
444 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
445 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
447 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
448 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
449 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
450 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
454 kernel_pt_lookup(vm_paddr_t pa)
458 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
465 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
467 pmap_pte_init_generic(void)
470 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
471 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
473 pte_l2_l_cache_mode = L2_B|L2_C;
474 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
476 pte_l2_s_cache_mode = L2_B|L2_C;
477 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
480 * If we have a write-through cache, set B and C. If
481 * we have a write-back cache, then we assume setting
482 * only C will make those pages write-through.
484 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
485 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
486 pte_l2_l_cache_mode_pt = L2_B|L2_C;
487 pte_l2_s_cache_mode_pt = L2_B|L2_C;
489 pte_l1_s_cache_mode_pt = L1_S_C;
490 pte_l2_l_cache_mode_pt = L2_C;
491 pte_l2_s_cache_mode_pt = L2_C;
494 pte_l2_s_prot_u = L2_S_PROT_U_generic;
495 pte_l2_s_prot_w = L2_S_PROT_W_generic;
496 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
498 pte_l1_s_proto = L1_S_PROTO_generic;
499 pte_l1_c_proto = L1_C_PROTO_generic;
500 pte_l2_s_proto = L2_S_PROTO_generic;
502 pmap_copy_page_func = pmap_copy_page_generic;
503 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
504 pmap_zero_page_func = pmap_zero_page_generic;
507 #if defined(CPU_ARM8)
509 pmap_pte_init_arm8(void)
513 * ARM8 is compatible with generic, but we need to use
514 * the page tables uncached.
516 pmap_pte_init_generic();
518 pte_l1_s_cache_mode_pt = 0;
519 pte_l2_l_cache_mode_pt = 0;
520 pte_l2_s_cache_mode_pt = 0;
522 #endif /* CPU_ARM8 */
524 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
526 pmap_pte_init_arm9(void)
530 * ARM9 is compatible with generic, but we want to use
531 * write-through caching for now.
533 pmap_pte_init_generic();
535 pte_l1_s_cache_mode = L1_S_C;
536 pte_l2_l_cache_mode = L2_C;
537 pte_l2_s_cache_mode = L2_C;
539 pte_l1_s_cache_mode_pt = L1_S_C;
540 pte_l2_l_cache_mode_pt = L2_C;
541 pte_l2_s_cache_mode_pt = L2_C;
543 #endif /* CPU_ARM9 */
544 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
546 #if defined(CPU_ARM10)
548 pmap_pte_init_arm10(void)
552 * ARM10 is compatible with generic, but we want to use
553 * write-through caching for now.
555 pmap_pte_init_generic();
557 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
558 pte_l2_l_cache_mode = L2_B | L2_C;
559 pte_l2_s_cache_mode = L2_B | L2_C;
561 pte_l1_s_cache_mode_pt = L1_S_C;
562 pte_l2_l_cache_mode_pt = L2_C;
563 pte_l2_s_cache_mode_pt = L2_C;
566 #endif /* CPU_ARM10 */
570 pmap_pte_init_sa1(void)
574 * The StrongARM SA-1 cache does not have a write-through
575 * mode. So, do the generic initialization, then reset
576 * the page table cache mode to B=1,C=1, and note that
577 * the PTEs need to be sync'd.
579 pmap_pte_init_generic();
581 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
582 pte_l2_l_cache_mode_pt = L2_B|L2_C;
583 pte_l2_s_cache_mode_pt = L2_B|L2_C;
585 pmap_needs_pte_sync = 1;
587 #endif /* ARM_MMU_SA1 == 1*/
589 #if ARM_MMU_XSCALE == 1
590 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
591 static u_int xscale_use_minidata;
595 pmap_pte_init_xscale(void)
598 int write_through = 0;
600 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
601 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
603 pte_l2_l_cache_mode = L2_B|L2_C;
604 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
606 pte_l2_s_cache_mode = L2_B|L2_C;
607 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
609 pte_l1_s_cache_mode_pt = L1_S_C;
610 pte_l2_l_cache_mode_pt = L2_C;
611 pte_l2_s_cache_mode_pt = L2_C;
612 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
614 * The XScale core has an enhanced mode where writes that
615 * miss the cache cause a cache line to be allocated. This
616 * is significantly faster than the traditional, write-through
617 * behavior of this case.
619 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
620 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
621 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
622 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
623 #ifdef XSCALE_CACHE_WRITE_THROUGH
625 * Some versions of the XScale core have various bugs in
626 * their cache units, the work-around for which is to run
627 * the cache in write-through mode. Unfortunately, this
628 * has a major (negative) impact on performance. So, we
629 * go ahead and run fast-and-loose, in the hopes that we
630 * don't line up the planets in a way that will trip the
633 * However, we give you the option to be slow-but-correct.
636 #elif defined(XSCALE_CACHE_WRITE_BACK)
637 /* force write back cache mode */
639 #elif defined(CPU_XSCALE_PXA2X0)
641 * Intel PXA2[15]0 processors are known to have a bug in
642 * write-back cache on revision 4 and earlier (stepping
643 * A[01] and B[012]). Fixed for C0 and later.
649 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
651 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
652 if ((id & CPU_ID_REVISION_MASK) < 5) {
653 /* write through for stepping A0-1 and B0-2 */
658 #endif /* XSCALE_CACHE_WRITE_THROUGH */
661 pte_l1_s_cache_mode = L1_S_C;
662 pte_l2_l_cache_mode = L2_C;
663 pte_l2_s_cache_mode = L2_C;
667 xscale_use_minidata = 1;
670 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
671 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
672 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
674 pte_l1_s_proto = L1_S_PROTO_xscale;
675 pte_l1_c_proto = L1_C_PROTO_xscale;
676 pte_l2_s_proto = L2_S_PROTO_xscale;
678 #ifdef CPU_XSCALE_CORE3
679 pmap_copy_page_func = pmap_copy_page_generic;
680 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
681 pmap_zero_page_func = pmap_zero_page_generic;
682 xscale_use_minidata = 0;
683 /* Make sure it is L2-cachable */
684 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
685 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
686 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
687 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
688 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
689 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
692 pmap_copy_page_func = pmap_copy_page_xscale;
693 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
694 pmap_zero_page_func = pmap_zero_page_xscale;
698 * Disable ECC protection of page table access, for now.
700 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
701 auxctl &= ~XSCALE_AUXCTL_P;
702 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
706 * xscale_setup_minidata:
708 * Set up the mini-data cache clean area. We require the
709 * caller to allocate the right amount of physically and
710 * virtually contiguous space.
712 extern vm_offset_t xscale_minidata_clean_addr;
713 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
715 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
717 pd_entry_t *pde = (pd_entry_t *) l1pt;
722 xscale_minidata_clean_addr = va;
724 /* Round it to page size. */
725 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
728 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
729 pte = (pt_entry_t *) kernel_pt_lookup(
730 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
732 panic("xscale_setup_minidata: can't find L2 table for "
733 "VA 0x%08x", (u_int32_t) va);
734 pte[l2pte_index(va)] =
735 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
736 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
740 * Configure the mini-data cache for write-back with
741 * read/write-allocate.
743 * NOTE: In order to reconfigure the mini-data cache, we must
744 * make sure it contains no valid data! In order to do that,
745 * we must issue a global data cache invalidate command!
747 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
748 * THIS IS VERY IMPORTANT!
751 /* Invalidate data and mini-data. */
752 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
753 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
754 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
755 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
760 * Allocate an L1 translation table for the specified pmap.
761 * This is called at pmap creation time.
764 pmap_alloc_l1(pmap_t pm)
766 struct l1_ttable *l1;
770 * Remove the L1 at the head of the LRU list
772 mtx_lock(&l1_lru_lock);
773 l1 = TAILQ_FIRST(&l1_lru_list);
774 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
777 * Pick the first available domain number, and update
778 * the link to the next number.
780 domain = l1->l1_domain_first;
781 l1->l1_domain_first = l1->l1_domain_free[domain];
784 * If there are still free domain numbers in this L1,
785 * put it back on the TAIL of the LRU list.
787 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
788 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
790 mtx_unlock(&l1_lru_lock);
793 * Fix up the relevant bits in the pmap structure
796 pm->pm_domain = domain + 1;
800 * Free an L1 translation table.
801 * This is called at pmap destruction time.
804 pmap_free_l1(pmap_t pm)
806 struct l1_ttable *l1 = pm->pm_l1;
808 mtx_lock(&l1_lru_lock);
811 * If this L1 is currently on the LRU list, remove it.
813 if (l1->l1_domain_use_count < PMAP_DOMAINS)
814 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
817 * Free up the domain number which was allocated to the pmap
819 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
820 l1->l1_domain_first = pm->pm_domain - 1;
821 l1->l1_domain_use_count--;
824 * The L1 now must have at least 1 free domain, so add
825 * it back to the LRU list. If the use count is zero,
826 * put it at the head of the list, otherwise it goes
829 if (l1->l1_domain_use_count == 0) {
830 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
832 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
834 mtx_unlock(&l1_lru_lock);
838 * Returns a pointer to the L2 bucket associated with the specified pmap
839 * and VA, or NULL if no L2 bucket exists for the address.
841 static PMAP_INLINE struct l2_bucket *
842 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
844 struct l2_dtable *l2;
845 struct l2_bucket *l2b;
850 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
851 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
858 * Returns a pointer to the L2 bucket associated with the specified pmap
861 * If no L2 bucket exists, perform the necessary allocations to put an L2
862 * bucket/page table in place.
864 * Note that if a new L2 bucket/page was allocated, the caller *must*
865 * increment the bucket occupancy counter appropriately *before*
866 * releasing the pmap's lock to ensure no other thread or cpu deallocates
867 * the bucket/page in the meantime.
869 static struct l2_bucket *
870 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
872 struct l2_dtable *l2;
873 struct l2_bucket *l2b;
878 PMAP_ASSERT_LOCKED(pm);
879 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
880 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
882 * No mapping at this address, as there is
883 * no entry in the L1 table.
884 * Need to allocate a new l2_dtable.
888 vm_page_unlock_queues();
889 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
890 vm_page_lock_queues();
894 vm_page_lock_queues();
896 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
898 vm_page_unlock_queues();
899 uma_zfree(l2table_zone, l2);
900 vm_page_lock_queues();
902 l2 = pm->pm_l2[L2_IDX(l1idx)];
906 * Someone already allocated the l2_dtable while
907 * we were doing the same.
910 bzero(l2, sizeof(*l2));
912 * Link it into the parent pmap
914 pm->pm_l2[L2_IDX(l1idx)] = l2;
918 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
921 * Fetch pointer to the L2 page table associated with the address.
923 if (l2b->l2b_kva == NULL) {
927 * No L2 page table has been allocated. Chances are, this
928 * is because we just allocated the l2_dtable, above.
932 vm_page_unlock_queues();
933 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT|M_USE_RESERVE);
934 vm_page_lock_queues();
936 if (l2b->l2b_kva != 0) {
937 /* We lost the race. */
939 vm_page_unlock_queues();
940 uma_zfree(l2zone, ptep);
941 vm_page_lock_queues();
943 if (l2b->l2b_kva == 0)
947 l2b->l2b_phys = vtophys(ptep);
950 * Oops, no more L2 page tables available at this
951 * time. We may need to deallocate the l2_dtable
952 * if we allocated a new one above.
954 if (l2->l2_occupancy == 0) {
955 pm->pm_l2[L2_IDX(l1idx)] = NULL;
956 pmap_free_l2_dtable(l2);
963 l2b->l2b_l1idx = l1idx;
969 static PMAP_INLINE void
970 #ifndef PMAP_INCLUDE_PTE_SYNC
971 pmap_free_l2_ptp(pt_entry_t *l2)
973 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
976 #ifdef PMAP_INCLUDE_PTE_SYNC
978 * Note: With a write-back cache, we may need to sync this
979 * L2 table before re-using it.
980 * This is because it may have belonged to a non-current
981 * pmap, in which case the cache syncs would have been
982 * skipped when the pages were being unmapped. If the
983 * L2 table were then to be immediately re-allocated to
984 * the *current* pmap, it may well contain stale mappings
985 * which have not yet been cleared by a cache write-back
986 * and so would still be visible to the mmu.
989 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
991 uma_zfree(l2zone, l2);
994 * One or more mappings in the specified L2 descriptor table have just been
997 * Garbage collect the metadata and descriptor table itself if necessary.
999 * The pmap lock must be acquired when this is called (not necessary
1000 * for the kernel pmap).
1003 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1005 struct l2_dtable *l2;
1006 pd_entry_t *pl1pd, l1pd;
1012 * Update the bucket's reference count according to how many
1013 * PTEs the caller has just invalidated.
1015 l2b->l2b_occupancy -= count;
1020 * Level 2 page tables allocated to the kernel pmap are never freed
1021 * as that would require checking all Level 1 page tables and
1022 * removing any references to the Level 2 page table. See also the
1023 * comment elsewhere about never freeing bootstrap L2 descriptors.
1025 * We make do with just invalidating the mapping in the L2 table.
1027 * This isn't really a big deal in practice and, in fact, leads
1028 * to a performance win over time as we don't need to continually
1031 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1035 * There are no more valid mappings in this level 2 page table.
1036 * Go ahead and NULL-out the pointer in the bucket, then
1037 * free the page table.
1039 l1idx = l2b->l2b_l1idx;
1040 ptep = l2b->l2b_kva;
1041 l2b->l2b_kva = NULL;
1043 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1046 * If the L1 slot matches the pmap's domain
1047 * number, then invalidate it.
1049 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1050 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1056 * Release the L2 descriptor table back to the pool cache.
1058 #ifndef PMAP_INCLUDE_PTE_SYNC
1059 pmap_free_l2_ptp(ptep);
1061 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1065 * Update the reference count in the associated l2_dtable
1067 l2 = pm->pm_l2[L2_IDX(l1idx)];
1068 if (--l2->l2_occupancy > 0)
1072 * There are no more valid mappings in any of the Level 1
1073 * slots managed by this l2_dtable. Go ahead and NULL-out
1074 * the pointer in the parent pmap and free the l2_dtable.
1076 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1077 pmap_free_l2_dtable(l2);
1081 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1085 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1087 #ifndef PMAP_INCLUDE_PTE_SYNC
1088 struct l2_bucket *l2b;
1089 pt_entry_t *ptep, pte;
1090 #ifdef ARM_USE_SMALL_ALLOC
1093 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1096 * The mappings for these page tables were initially made using
1097 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1098 * mode will not be right for page table mappings. To avoid
1099 * polluting the pmap_kenter() code with a special case for
1100 * page tables, we simply fix up the cache-mode here if it's not
1103 #ifdef ARM_USE_SMALL_ALLOC
1104 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1105 if (!l1pte_section_p(*pde)) {
1107 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1108 ptep = &l2b->l2b_kva[l2pte_index(va)];
1111 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1113 * Page tables must have the cache-mode set to
1116 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1118 cpu_tlb_flushD_SE(va);
1121 #ifdef ARM_USE_SMALL_ALLOC
1125 memset(mem, 0, L2_TABLE_SIZE_REAL);
1126 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1131 * A bunch of routines to conditionally flush the caches/TLB depending
1132 * on whether the specified pmap actually needs to be flushed at any
1135 static PMAP_INLINE void
1136 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1139 if (pmap_is_current(pm))
1140 cpu_tlb_flushID_SE(va);
1143 static PMAP_INLINE void
1144 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1147 if (pmap_is_current(pm))
1148 cpu_tlb_flushD_SE(va);
1151 static PMAP_INLINE void
1152 pmap_tlb_flushID(pmap_t pm)
1155 if (pmap_is_current(pm))
1158 static PMAP_INLINE void
1159 pmap_tlb_flushD(pmap_t pm)
1162 if (pmap_is_current(pm))
1167 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1172 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1173 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1179 static PMAP_INLINE void
1180 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1184 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1185 " len 0x%x ", pm, pm == pmap_kernel(), va, len);
1187 if (pmap_is_current(pm) || pm == pmap_kernel()) {
1188 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1190 if (pmap_has_valid_mapping(pm, va)) {
1191 cpu_idcache_wbinv_range(va, rest);
1192 cpu_l2cache_wbinv_range(va, rest);
1196 rest = MIN(PAGE_SIZE, len);
1201 static PMAP_INLINE void
1202 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1207 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1208 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1209 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1211 if (pmap_is_current(pm)) {
1212 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1214 if (pmap_has_valid_mapping(pm, va)) {
1215 if (do_inv && rd_only) {
1216 cpu_dcache_inv_range(va, rest);
1217 cpu_l2cache_inv_range(va, rest);
1218 } else if (do_inv) {
1219 cpu_dcache_wbinv_range(va, rest);
1220 cpu_l2cache_wbinv_range(va, rest);
1221 } else if (!rd_only) {
1222 cpu_dcache_wb_range(va, rest);
1223 cpu_l2cache_wb_range(va, rest);
1229 rest = MIN(PAGE_SIZE, len);
1234 static PMAP_INLINE void
1235 pmap_idcache_wbinv_all(pmap_t pm)
1238 if (pmap_is_current(pm)) {
1239 cpu_idcache_wbinv_all();
1240 cpu_l2cache_wbinv_all();
1245 static PMAP_INLINE void
1246 pmap_dcache_wbinv_all(pmap_t pm)
1249 if (pmap_is_current(pm)) {
1250 cpu_dcache_wbinv_all();
1251 cpu_l2cache_wbinv_all();
1259 * Make sure the pte is written out to RAM.
1260 * We need to do this for one of two cases:
1261 * - We're dealing with the kernel pmap
1262 * - There is no pmap active in the cache/tlb.
1263 * - The specified pmap is 'active' in the cache/tlb.
1265 #ifdef PMAP_INCLUDE_PTE_SYNC
1266 #define PTE_SYNC_CURRENT(pm, ptep) \
1268 if (PMAP_NEEDS_PTE_SYNC && \
1269 pmap_is_current(pm)) \
1271 } while (/*CONSTCOND*/0)
1273 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1277 * cacheable == -1 means we must make the entry uncacheable, 1 means
1280 static __inline void
1281 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1283 struct l2_bucket *l2b;
1284 pt_entry_t *ptep, pte;
1286 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1287 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1289 if (cacheable == 1) {
1290 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1291 if (l2pte_valid(pte)) {
1292 if (PV_BEEN_EXECD(pv->pv_flags)) {
1293 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1294 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1295 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1299 pte = *ptep &~ L2_S_CACHE_MASK;
1300 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1302 if (PV_BEEN_EXECD(pv->pv_flags)) {
1303 pmap_idcache_wbinv_range(pv->pv_pmap,
1304 pv->pv_va, PAGE_SIZE);
1305 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1306 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1307 pmap_dcache_wb_range(pv->pv_pmap,
1308 pv->pv_va, PAGE_SIZE, TRUE,
1309 (pv->pv_flags & PVF_WRITE) == 0);
1310 pmap_tlb_flushD_SE(pv->pv_pmap,
1316 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1320 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1323 int writable = 0, kwritable = 0, uwritable = 0;
1324 int entries = 0, kentries = 0, uentries = 0;
1325 struct pv_entry *pv;
1327 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1329 /* the cache gets written back/invalidated on context switch.
1330 * therefore, if a user page shares an entry in the same page or
1331 * with the kernel map and at least one is writable, then the
1332 * cache entry must be set write-through.
1335 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1336 /* generate a count of the pv_entry uses */
1337 if (pv->pv_flags & PVF_WRITE) {
1338 if (pv->pv_pmap == pmap_kernel())
1340 else if (pv->pv_pmap == pm)
1344 if (pv->pv_pmap == pmap_kernel())
1347 if (pv->pv_pmap == pm)
1353 * check if the user duplicate mapping has
1356 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1360 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1361 /* check for user uncachable conditions - order is important */
1362 if (pm != pmap_kernel() &&
1363 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1365 if ((uentries > 1 && uwritable) || uwritable > 1) {
1367 /* user duplicate mapping */
1368 if (pv->pv_pmap != pmap_kernel())
1369 pv->pv_flags |= PVF_MWC;
1371 if (!(pv->pv_flags & PVF_NC)) {
1372 pv->pv_flags |= PVF_NC;
1373 pmap_set_cache_entry(pv, pm, va, -1);
1376 } else /* no longer a duplicate user */
1377 pv->pv_flags &= ~PVF_MWC;
1381 * check for kernel uncachable conditions
1382 * kernel writable or kernel readable with writable user entry
1384 if ((kwritable && (entries || kentries > 1)) ||
1386 ((kwritable != writable) && kentries &&
1387 (pv->pv_pmap == pmap_kernel() ||
1388 (pv->pv_flags & PVF_WRITE) ||
1389 (pv->pv_flags & PVF_MWC)))) {
1391 if (!(pv->pv_flags & PVF_NC)) {
1392 pv->pv_flags |= PVF_NC;
1393 pmap_set_cache_entry(pv, pm, va, -1);
1398 /* kernel and user are cachable */
1399 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1400 (pv->pv_flags & PVF_NC)) {
1402 pv->pv_flags &= ~PVF_NC;
1403 pmap_set_cache_entry(pv, pm, va, 1);
1406 /* user is no longer sharable and writable */
1407 if (pm != pmap_kernel() &&
1408 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1409 !pmwc && (pv->pv_flags & PVF_NC)) {
1411 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1412 pmap_set_cache_entry(pv, pm, va, 1);
1416 if ((kwritable == 0) && (writable == 0)) {
1417 pg->md.pvh_attrs &= ~PVF_MOD;
1418 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1424 * Modify pte bits for all ptes corresponding to the given physical address.
1425 * We use `maskbits' rather than `clearbits' because we're always passing
1426 * constants and the latter would require an extra inversion at run-time.
1429 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1431 struct l2_bucket *l2b;
1432 struct pv_entry *pv;
1433 pt_entry_t *ptep, npte, opte;
1439 vm_page_lock_queues();
1441 if (maskbits & PVF_WRITE)
1442 maskbits |= PVF_MOD;
1444 * Clear saved attributes (modify, reference)
1446 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1448 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1449 vm_page_unlock_queues();
1454 * Loop over all current mappings setting/clearing as appropos
1456 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1459 oflags = pv->pv_flags;
1461 if (!(oflags & maskbits)) {
1462 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1463 /* It is safe to re-enable cacheing here. */
1465 l2b = pmap_get_l2_bucket(pm, va);
1466 ptep = &l2b->l2b_kva[l2pte_index(va)];
1467 *ptep |= pte_l2_s_cache_mode;
1470 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1475 pv->pv_flags &= ~maskbits;
1479 l2b = pmap_get_l2_bucket(pm, va);
1481 ptep = &l2b->l2b_kva[l2pte_index(va)];
1482 npte = opte = *ptep;
1484 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1485 if ((pv->pv_flags & PVF_NC)) {
1487 * Entry is not cacheable:
1489 * Don't turn caching on again if this is a
1490 * modified emulation. This would be
1491 * inconsitent with the settings created by
1492 * pmap_fix_cache(). Otherwise, it's safe
1493 * to re-enable cacheing.
1495 * There's no need to call pmap_fix_cache()
1496 * here: all pages are losing their write
1499 if (maskbits & PVF_WRITE) {
1500 npte |= pte_l2_s_cache_mode;
1501 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1504 if (opte & L2_S_PROT_W) {
1507 * Entry is writable/cacheable: check if pmap
1508 * is current if it is flush it, otherwise it
1509 * won't be in the cache
1511 if (PV_BEEN_EXECD(oflags))
1512 pmap_idcache_wbinv_range(pm, pv->pv_va,
1515 if (PV_BEEN_REFD(oflags))
1516 pmap_dcache_wb_range(pm, pv->pv_va,
1518 (maskbits & PVF_REF) ? TRUE : FALSE,
1522 /* make the pte read only */
1523 npte &= ~L2_S_PROT_W;
1526 if (maskbits & PVF_REF) {
1527 if ((pv->pv_flags & PVF_NC) == 0 &&
1528 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1530 * Check npte here; we may have already
1531 * done the wbinv above, and the validity
1532 * of the PTE is the same for opte and
1535 if (npte & L2_S_PROT_W) {
1536 if (PV_BEEN_EXECD(oflags))
1537 pmap_idcache_wbinv_range(pm,
1538 pv->pv_va, PAGE_SIZE);
1540 if (PV_BEEN_REFD(oflags))
1541 pmap_dcache_wb_range(pm,
1542 pv->pv_va, PAGE_SIZE,
1545 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1546 /* XXXJRT need idcache_inv_range */
1547 if (PV_BEEN_EXECD(oflags))
1548 pmap_idcache_wbinv_range(pm,
1549 pv->pv_va, PAGE_SIZE);
1551 if (PV_BEEN_REFD(oflags))
1552 pmap_dcache_wb_range(pm,
1553 pv->pv_va, PAGE_SIZE,
1559 * Make the PTE invalid so that we will take a
1560 * page fault the next time the mapping is
1563 npte &= ~L2_TYPE_MASK;
1564 npte |= L2_TYPE_INV;
1571 /* Flush the TLB entry if a current pmap. */
1572 if (PV_BEEN_EXECD(oflags))
1573 pmap_tlb_flushID_SE(pm, pv->pv_va);
1575 if (PV_BEEN_REFD(oflags))
1576 pmap_tlb_flushD_SE(pm, pv->pv_va);
1583 if (maskbits & PVF_WRITE)
1584 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1585 vm_page_unlock_queues();
1590 * main pv_entry manipulation functions:
1591 * pmap_enter_pv: enter a mapping onto a vm_page list
1592 * pmap_remove_pv: remove a mappiing from a vm_page list
1594 * NOTE: pmap_enter_pv expects to lock the pvh itself
1595 * pmap_remove_pv expects te caller to lock the pvh before calling
1599 * pmap_enter_pv: enter a mapping onto a vm_page lst
1601 * => caller should hold the proper lock on pmap_main_lock
1602 * => caller should have pmap locked
1603 * => we will gain the lock on the vm_page and allocate the new pv_entry
1604 * => caller should adjust ptp's wire_count before calling
1605 * => caller should not adjust pmap's wire_count
1608 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1609 vm_offset_t va, u_int flags)
1614 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1616 if (pg->md.pv_kva) {
1617 /* PMAP_ASSERT_LOCKED(pmap_kernel()); */
1618 pve->pv_pmap = pmap_kernel();
1619 pve->pv_va = pg->md.pv_kva;
1620 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1623 if (!(km = PMAP_OWNED(pmap_kernel())))
1624 PMAP_LOCK(pmap_kernel());
1625 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1626 TAILQ_INSERT_HEAD(&pve->pv_pmap->pm_pvlist, pve, pv_plist);
1627 PMAP_UNLOCK(pmap_kernel());
1628 vm_page_unlock_queues();
1629 if ((pve = pmap_get_pv_entry()) == NULL)
1630 panic("pmap_kenter_internal: no pv entries");
1631 vm_page_lock_queues();
1633 PMAP_LOCK(pmap_kernel());
1636 PMAP_ASSERT_LOCKED(pm);
1639 pve->pv_flags = flags;
1641 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1642 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1643 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1644 if (pve->pv_flags & PVF_WIRED)
1645 ++pm->pm_stats.wired_count;
1646 vm_page_aflag_set(pg, PGA_REFERENCED);
1651 * pmap_find_pv: Find a pv entry
1653 * => caller should hold lock on vm_page
1655 static PMAP_INLINE struct pv_entry *
1656 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1658 struct pv_entry *pv;
1660 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1661 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1662 if (pm == pv->pv_pmap && va == pv->pv_va)
1668 * vector_page_setprot:
1670 * Manipulate the protection of the vector page.
1673 vector_page_setprot(int prot)
1675 struct l2_bucket *l2b;
1678 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1680 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1682 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1684 cpu_tlb_flushD_SE(vector_page);
1689 * pmap_remove_pv: try to remove a mapping from a pv_list
1691 * => caller should hold proper lock on pmap_main_lock
1692 * => pmap should be locked
1693 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1694 * => caller should adjust ptp's wire_count and free PTP if needed
1695 * => caller should NOT adjust pmap's wire_count
1696 * => we return the removed pve
1700 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1703 struct pv_entry *pv;
1704 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1705 PMAP_ASSERT_LOCKED(pm);
1706 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1707 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1708 if (pve->pv_flags & PVF_WIRED)
1709 --pm->pm_stats.wired_count;
1710 if (pg->md.pvh_attrs & PVF_MOD)
1712 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1713 pg->md.pvh_attrs &= ~PVF_REF;
1715 vm_page_aflag_set(pg, PGA_REFERENCED);
1716 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1717 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1718 pmap_fix_cache(pg, pm, 0);
1719 else if (pve->pv_flags & PVF_WRITE) {
1720 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1721 if (pve->pv_flags & PVF_WRITE)
1724 pg->md.pvh_attrs &= ~PVF_MOD;
1725 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1728 pv = TAILQ_FIRST(&pg->md.pv_list);
1729 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1730 TAILQ_NEXT(pv, pv_list) == NULL) {
1732 pg->md.pv_kva = pv->pv_va;
1733 /* a recursive pmap_nuke_pv */
1734 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1735 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1736 if (pv->pv_flags & PVF_WIRED)
1737 --pm->pm_stats.wired_count;
1738 pg->md.pvh_attrs &= ~PVF_REF;
1739 pg->md.pvh_attrs &= ~PVF_MOD;
1740 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1741 pmap_free_pv_entry(pv);
1745 static struct pv_entry *
1746 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1748 struct pv_entry *pve;
1750 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1751 pve = TAILQ_FIRST(&pg->md.pv_list);
1754 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1755 pmap_nuke_pv(pg, pm, pve);
1758 pve = TAILQ_NEXT(pve, pv_list);
1761 if (pve == NULL && pg->md.pv_kva == va)
1764 return(pve); /* return removed pve */
1768 * pmap_modify_pv: Update pv flags
1770 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1771 * => caller should NOT adjust pmap's wire_count
1772 * => we return the old flags
1774 * Modify a physical-virtual mapping in the pv table
1777 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1778 u_int clr_mask, u_int set_mask)
1780 struct pv_entry *npv;
1781 u_int flags, oflags;
1783 PMAP_ASSERT_LOCKED(pm);
1784 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1785 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1789 * There is at least one VA mapping this page.
1792 if (clr_mask & (PVF_REF | PVF_MOD))
1793 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1795 oflags = npv->pv_flags;
1796 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1798 if ((flags ^ oflags) & PVF_WIRED) {
1799 if (flags & PVF_WIRED)
1800 ++pm->pm_stats.wired_count;
1802 --pm->pm_stats.wired_count;
1805 if ((flags ^ oflags) & PVF_WRITE)
1806 pmap_fix_cache(pg, pm, 0);
1811 /* Function to set the debug level of the pmap code */
1814 pmap_debug(int level)
1816 pmap_debug_level = level;
1817 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1819 #endif /* PMAP_DEBUG */
1822 pmap_pinit0(struct pmap *pmap)
1824 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1826 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1827 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1828 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1829 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1830 PMAP_LOCK_INIT(pmap);
1834 * Initialize a vm_page's machine-dependent fields.
1837 pmap_page_init(vm_page_t m)
1840 TAILQ_INIT(&m->md.pv_list);
1844 * Initialize the pmap module.
1845 * Called by vm_init, to initialize any structures that the pmap
1846 * system needs to map virtual memory.
1851 int shpgperproc = PMAP_SHPGPERPROC;
1853 PDEBUG(1, printf("pmap_init: phys_start = %08x\n", PHYSADDR));
1856 * init the pv free list
1858 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1859 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1861 * Now it is safe to enable pv_table recording.
1863 PDEBUG(1, printf("pmap_init: done!\n"));
1865 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1867 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1868 pv_entry_high_water = 9 * (pv_entry_max / 10);
1869 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1870 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1871 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
1872 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1873 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1875 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1880 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1882 struct l2_dtable *l2;
1883 struct l2_bucket *l2b;
1884 pd_entry_t *pl1pd, l1pd;
1885 pt_entry_t *ptep, pte;
1891 vm_page_lock_queues();
1895 * If there is no l2_dtable for this address, then the process
1896 * has no business accessing it.
1898 * Note: This will catch userland processes trying to access
1901 l2 = pm->pm_l2[L2_IDX(l1idx)];
1906 * Likewise if there is no L2 descriptor table
1908 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1909 if (l2b->l2b_kva == NULL)
1913 * Check the PTE itself.
1915 ptep = &l2b->l2b_kva[l2pte_index(va)];
1921 * Catch a userland access to the vector page mapped at 0x0
1923 if (user && (pte & L2_S_PROT_U) == 0)
1925 if (va == vector_page)
1930 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1932 * This looks like a good candidate for "page modified"
1935 struct pv_entry *pv;
1938 /* Extract the physical address of the page */
1939 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1942 /* Get the current flags for this page. */
1944 pv = pmap_find_pv(pg, pm, va);
1950 * Do the flags say this page is writable? If not then it
1951 * is a genuine write fault. If yes then the write fault is
1952 * our fault as we did not reflect the write access in the
1953 * PTE. Now we know a write has occurred we can correct this
1954 * and also set the modified bit
1956 if ((pv->pv_flags & PVF_WRITE) == 0) {
1960 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1962 pv->pv_flags |= PVF_REF | PVF_MOD;
1965 * Re-enable write permissions for the page. No need to call
1966 * pmap_fix_cache(), since this is just a
1967 * modified-emulation fault, and the PVF_WRITE bit isn't
1968 * changing. We've already set the cacheable bits based on
1969 * the assumption that we can write to this page.
1971 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1975 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1977 * This looks like a good candidate for "page referenced"
1980 struct pv_entry *pv;
1983 /* Extract the physical address of the page */
1984 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1986 /* Get the current flags for this page. */
1988 pv = pmap_find_pv(pg, pm, va);
1992 pg->md.pvh_attrs |= PVF_REF;
1993 pv->pv_flags |= PVF_REF;
1996 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2002 * We know there is a valid mapping here, so simply
2003 * fix up the L1 if necessary.
2005 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2006 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2007 if (*pl1pd != l1pd) {
2015 * There are bugs in the rev K SA110. This is a check for one
2018 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2019 curcpu()->ci_arm_cpurev < 3) {
2020 /* Always current pmap */
2021 if (l2pte_valid(pte)) {
2022 extern int kernel_debug;
2023 if (kernel_debug & 1) {
2024 struct proc *p = curlwp->l_proc;
2025 printf("prefetch_abort: page is already "
2026 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2027 printf("prefetch_abort: pc=%08lx proc=%p "
2028 "process=%s\n", va, p, p->p_comm);
2029 printf("prefetch_abort: far=%08x fs=%x\n",
2030 cpu_faultaddress(), cpu_faultstatus());
2033 if (kernel_debug & 2)
2039 #endif /* CPU_SA110 */
2043 * If 'rv == 0' at this point, it generally indicates that there is a
2044 * stale TLB entry for the faulting address. This happens when two or
2045 * more processes are sharing an L1. Since we don't flush the TLB on
2046 * a context switch between such processes, we can take domain faults
2047 * for mappings which exist at the same VA in both processes. EVEN IF
2048 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2051 * This is extremely likely to happen if pmap_enter() updated the L1
2052 * entry for a recently entered mapping. In this case, the TLB is
2053 * flushed for the new mapping, but there may still be TLB entries for
2054 * other mappings belonging to other processes in the 1MB range
2055 * covered by the L1 entry.
2057 * Since 'rv == 0', we know that the L1 already contains the correct
2058 * value, so the fault must be due to a stale TLB entry.
2060 * Since we always need to flush the TLB anyway in the case where we
2061 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2062 * stale TLB entries dynamically.
2064 * However, the above condition can ONLY happen if the current L1 is
2065 * being shared. If it happens when the L1 is unshared, it indicates
2066 * that other parts of the pmap are not doing their job WRT managing
2069 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2070 extern int last_fault_code;
2071 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2073 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2074 l2, l2b, ptep, pl1pd);
2075 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2076 pte, l1pd, last_fault_code);
2083 cpu_tlb_flushID_SE(va);
2089 vm_page_unlock_queues();
2097 struct l2_bucket *l2b;
2098 struct l1_ttable *l1;
2100 pt_entry_t *ptep, pte;
2101 vm_offset_t va, eva;
2104 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2106 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2108 for (loop = 0; loop < needed; loop++, l1++) {
2109 /* Allocate a L1 page table */
2110 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2111 0xffffffff, L1_TABLE_SIZE, 0);
2114 panic("Cannot allocate L1 KVM");
2116 eva = va + L1_TABLE_SIZE;
2117 pl1pt = (pd_entry_t *)va;
2120 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2121 ptep = &l2b->l2b_kva[l2pte_index(va)];
2123 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2126 cpu_tlb_flushD_SE(va);
2130 pmap_init_l1(l1, pl1pt);
2135 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2141 * This is used to stuff certain critical values into the PCB where they
2142 * can be accessed quickly from cpu_switch() et al.
2145 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2147 struct l2_bucket *l2b;
2149 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2150 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2151 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2153 if (vector_page < KERNBASE) {
2154 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2155 l2b = pmap_get_l2_bucket(pm, vector_page);
2156 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2157 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2159 pcb->pcb_pl1vec = NULL;
2163 pmap_activate(struct thread *td)
2168 pm = vmspace_pmap(td->td_proc->p_vmspace);
2172 pmap_set_pcb_pagedir(pm, pcb);
2174 if (td == curthread) {
2175 u_int cur_dacr, cur_ttb;
2177 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2178 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2180 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2182 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2183 cur_dacr == pcb->pcb_dacr) {
2185 * No need to switch address spaces.
2193 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2194 * to 'vector_page' in the incoming L1 table before switching
2195 * to it otherwise subsequent interrupts/exceptions (including
2196 * domain faults!) will jump into hyperspace.
2198 if (pcb->pcb_pl1vec) {
2200 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2202 * Don't need to PTE_SYNC() at this point since
2203 * cpu_setttb() is about to flush both the cache
2208 cpu_domains(pcb->pcb_dacr);
2209 cpu_setttb(pcb->pcb_pagedir);
2215 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2217 pd_entry_t *pdep, pde;
2218 pt_entry_t *ptep, pte;
2223 * Make sure the descriptor itself has the correct cache mode
2225 pdep = &kl1[L1_IDX(va)];
2228 if (l1pte_section_p(pde)) {
2229 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2230 *pdep = (pde & ~L1_S_CACHE_MASK) |
2231 pte_l1_s_cache_mode_pt;
2233 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2235 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2240 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2241 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2243 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2245 ptep = &ptep[l2pte_index(va)];
2247 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2248 *ptep = (pte & ~L2_S_CACHE_MASK) |
2249 pte_l2_s_cache_mode_pt;
2251 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2253 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2263 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2266 vm_offset_t va = *availp;
2267 struct l2_bucket *l2b;
2270 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2272 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2274 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2278 *availp = va + (PAGE_SIZE * pages);
2282 * Bootstrap the system enough to run with virtual memory.
2284 * On the arm this is called after mapping has already been enabled
2285 * and just syncs the pmap module with what has already been done.
2286 * [We can't call it easily with mapping off since the kernel is not
2287 * mapped with PA == VA, hence we would have to relocate every address
2288 * from the linked base (virtual) address "KERNBASE" to the actual
2289 * (physical) address starting relative to 0]
2291 #define PMAP_STATIC_L2_SIZE 16
2292 #ifdef ARM_USE_SMALL_ALLOC
2293 extern struct mtx smallalloc_mtx;
2297 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2299 static struct l1_ttable static_l1;
2300 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2301 struct l1_ttable *l1 = &static_l1;
2302 struct l2_dtable *l2;
2303 struct l2_bucket *l2b;
2305 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2310 int l1idx, l2idx, l2next = 0;
2312 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2313 firstaddr, lastaddr));
2315 virtual_avail = firstaddr;
2316 kernel_pmap->pm_l1 = l1;
2317 kernel_l1pa = l1pt->pv_pa;
2320 * Scan the L1 translation table created by initarm() and create
2321 * the required metadata for all valid mappings found in it.
2323 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2324 pde = kernel_l1pt[l1idx];
2327 * We're only interested in Coarse mappings.
2328 * pmap_extract() can deal with section mappings without
2329 * recourse to checking L2 metadata.
2331 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2335 * Lookup the KVA of this L2 descriptor table
2337 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2338 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2341 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2342 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2346 * Fetch the associated L2 metadata structure.
2347 * Allocate a new one if necessary.
2349 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2350 if (l2next == PMAP_STATIC_L2_SIZE)
2351 panic("pmap_bootstrap: out of static L2s");
2352 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2353 &static_l2[l2next++];
2357 * One more L1 slot tracked...
2362 * Fill in the details of the L2 descriptor in the
2363 * appropriate bucket.
2365 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2366 l2b->l2b_kva = ptep;
2368 l2b->l2b_l1idx = l1idx;
2371 * Establish an initial occupancy count for this descriptor
2374 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2376 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2377 l2b->l2b_occupancy++;
2382 * Make sure the descriptor itself has the correct cache mode.
2383 * If not, fix it, but whine about the problem. Port-meisters
2384 * should consider this a clue to fix up their initarm()
2387 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2388 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2389 "L2 pte @ %p\n", ptep);
2395 * Ensure the primary (kernel) L1 has the correct cache mode for
2396 * a page table. Bitch if it is not correctly set.
2398 for (va = (vm_offset_t)kernel_l1pt;
2399 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2400 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2401 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2402 "primary L1 @ 0x%x\n", va);
2405 cpu_dcache_wbinv_all();
2406 cpu_l2cache_wbinv_all();
2410 PMAP_LOCK_INIT(kernel_pmap);
2411 CPU_FILL(&kernel_pmap->pm_active);
2412 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2413 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2416 * Reserve some special page table entries/VA space for temporary
2419 #define SYSMAP(c, p, v, n) \
2420 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2422 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2423 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2424 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2425 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2426 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2427 pmap_alloc_specials(&virtual_avail,
2428 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2429 &pmap_kernel_l2ptp_kva, NULL);
2431 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2432 pmap_alloc_specials(&virtual_avail,
2433 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2434 &pmap_kernel_l2dtable_kva, NULL);
2436 pmap_alloc_specials(&virtual_avail,
2437 1, (vm_offset_t*)&_tmppt, NULL);
2438 pmap_alloc_specials(&virtual_avail,
2439 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2440 SLIST_INIT(&l1_list);
2441 TAILQ_INIT(&l1_lru_list);
2442 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2443 pmap_init_l1(l1, kernel_l1pt);
2444 cpu_dcache_wbinv_all();
2445 cpu_l2cache_wbinv_all();
2447 virtual_avail = round_page(virtual_avail);
2448 virtual_end = lastaddr;
2449 kernel_vm_end = pmap_curmaxkvaddr;
2450 arm_nocache_startaddr = lastaddr;
2451 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2453 #ifdef ARM_USE_SMALL_ALLOC
2454 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2455 arm_init_smallalloc();
2457 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2460 /***************************************************
2461 * Pmap allocation/deallocation routines.
2462 ***************************************************/
2465 * Release any resources held by the given physical map.
2466 * Called when a pmap initialized by pmap_pinit is being released.
2467 * Should only be called if the map contains no valid mappings.
2470 pmap_release(pmap_t pmap)
2474 pmap_idcache_wbinv_all(pmap);
2475 cpu_l2cache_wbinv_all();
2476 pmap_tlb_flushID(pmap);
2478 if (vector_page < KERNBASE) {
2479 struct pcb *curpcb = PCPU_GET(curpcb);
2480 pcb = thread0.td_pcb;
2481 if (pmap_is_current(pmap)) {
2483 * Frob the L1 entry corresponding to the vector
2484 * page so that it contains the kernel pmap's domain
2485 * number. This will ensure pmap_remove() does not
2486 * pull the current vector page out from under us.
2489 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2490 cpu_domains(pcb->pcb_dacr);
2491 cpu_setttb(pcb->pcb_pagedir);
2494 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2496 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2497 * since this process has no remaining mappings of its own.
2499 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2500 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2501 curpcb->pcb_dacr = pcb->pcb_dacr;
2502 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2506 PMAP_LOCK_DESTROY(pmap);
2508 dprintf("pmap_release()\n");
2514 * Helper function for pmap_grow_l2_bucket()
2517 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2519 struct l2_bucket *l2b;
2524 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2527 pa = VM_PAGE_TO_PHYS(pg);
2532 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2534 ptep = &l2b->l2b_kva[l2pte_index(va)];
2535 *ptep = L2_S_PROTO | pa | cache_mode |
2536 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2542 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2543 * used by pmap_growkernel().
2545 static __inline struct l2_bucket *
2546 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2548 struct l2_dtable *l2;
2549 struct l2_bucket *l2b;
2550 struct l1_ttable *l1;
2557 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2559 * No mapping at this address, as there is
2560 * no entry in the L1 table.
2561 * Need to allocate a new l2_dtable.
2563 nva = pmap_kernel_l2dtable_kva;
2564 if ((nva & PAGE_MASK) == 0) {
2566 * Need to allocate a backing page
2568 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2572 l2 = (struct l2_dtable *)nva;
2573 nva += sizeof(struct l2_dtable);
2575 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2578 * The new l2_dtable straddles a page boundary.
2579 * Map in another page to cover it.
2581 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2585 pmap_kernel_l2dtable_kva = nva;
2588 * Link it into the parent pmap
2590 pm->pm_l2[L2_IDX(l1idx)] = l2;
2591 memset(l2, 0, sizeof(*l2));
2594 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2597 * Fetch pointer to the L2 page table associated with the address.
2599 if (l2b->l2b_kva == NULL) {
2603 * No L2 page table has been allocated. Chances are, this
2604 * is because we just allocated the l2_dtable, above.
2606 nva = pmap_kernel_l2ptp_kva;
2607 ptep = (pt_entry_t *)nva;
2608 if ((nva & PAGE_MASK) == 0) {
2610 * Need to allocate a backing page
2612 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2613 &pmap_kernel_l2ptp_phys))
2615 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2617 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2619 l2b->l2b_kva = ptep;
2620 l2b->l2b_l1idx = l1idx;
2621 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2623 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2624 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2627 /* Distribute new L1 entry to all other L1s */
2628 SLIST_FOREACH(l1, &l1_list, l1_link) {
2629 pl1pd = &l1->l1_kva[L1_IDX(va)];
2630 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2640 * grow the number of kernel page table entries, if needed
2643 pmap_growkernel(vm_offset_t addr)
2645 pmap_t kpm = pmap_kernel();
2647 if (addr <= pmap_curmaxkvaddr)
2648 return; /* we are OK */
2651 * whoops! we need to add kernel PTPs
2654 /* Map 1MB at a time */
2655 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2656 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2659 * flush out the cache, expensive but growkernel will happen so
2662 cpu_dcache_wbinv_all();
2663 cpu_l2cache_wbinv_all();
2666 kernel_vm_end = pmap_curmaxkvaddr;
2671 * Remove all pages from specified address space
2672 * this aids process exit speeds. Also, this code
2673 * is special cased for current process only, but
2674 * can have the more generic (and slightly slower)
2675 * mode enabled. This is much faster than pmap_remove
2676 * in the case of running down an entire address space.
2679 pmap_remove_pages(pmap_t pmap)
2681 struct pv_entry *pv, *npv;
2682 struct l2_bucket *l2b = NULL;
2686 vm_page_lock_queues();
2688 cpu_idcache_wbinv_all();
2689 cpu_l2cache_wbinv_all();
2690 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2691 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2692 /* Cannot remove wired or unmanaged pages now. */
2693 npv = TAILQ_NEXT(pv, pv_plist);
2696 pmap->pm_stats.resident_count--;
2697 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2698 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2699 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2700 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2701 #ifdef ARM_USE_SMALL_ALLOC
2702 KASSERT((vm_offset_t)m >= alloc_firstaddr, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2704 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2708 npv = TAILQ_NEXT(pv, pv_plist);
2709 pmap_nuke_pv(m, pmap, pv);
2710 if (TAILQ_EMPTY(&m->md.pv_list))
2711 vm_page_aflag_clear(m, PGA_WRITEABLE);
2712 pmap_free_pv_entry(pv);
2713 pmap_free_l2_bucket(pmap, l2b, 1);
2715 vm_page_unlock_queues();
2722 /***************************************************
2723 * Low level mapping routines.....
2724 ***************************************************/
2726 #ifdef ARM_HAVE_SUPERSECTIONS
2727 /* Map a super section into the KVA. */
2730 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2732 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2733 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2734 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2735 struct l1_ttable *l1;
2736 vm_offset_t va0, va_end;
2738 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2739 ("Not a valid super section mapping"));
2740 if (flags & SECTION_CACHE)
2741 pd |= pte_l1_s_cache_mode;
2742 else if (flags & SECTION_PT)
2743 pd |= pte_l1_s_cache_mode_pt;
2744 va0 = va & L1_SUP_FRAME;
2745 va_end = va + L1_SUP_SIZE;
2746 SLIST_FOREACH(l1, &l1_list, l1_link) {
2748 for (; va < va_end; va += L1_S_SIZE) {
2749 l1->l1_kva[L1_IDX(va)] = pd;
2750 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2756 /* Map a section into the KVA. */
2759 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2761 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2762 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2763 struct l1_ttable *l1;
2765 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2766 ("Not a valid section mapping"));
2767 if (flags & SECTION_CACHE)
2768 pd |= pte_l1_s_cache_mode;
2769 else if (flags & SECTION_PT)
2770 pd |= pte_l1_s_cache_mode_pt;
2771 SLIST_FOREACH(l1, &l1_list, l1_link) {
2772 l1->l1_kva[L1_IDX(va)] = pd;
2773 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2778 * Make a temporary mapping for a physical address. This is only intended
2779 * to be used for panic dumps.
2782 pmap_kenter_temp(vm_paddr_t pa, int i)
2786 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2787 pmap_kenter(va, pa);
2788 return ((void *)crashdumpmap);
2792 * add a wired page to the kva
2793 * note that in order for the mapping to take effect -- you
2794 * should do a invltlb after doing the pmap_kenter...
2796 static PMAP_INLINE void
2797 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2799 struct l2_bucket *l2b;
2802 struct pv_entry *pve;
2805 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2806 (uint32_t) va, (uint32_t) pa));
2809 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2811 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2812 KASSERT(l2b != NULL, ("No L2 Bucket"));
2813 pte = &l2b->l2b_kva[l2pte_index(va)];
2815 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2816 (uint32_t) pte, opte, *pte));
2817 if (l2pte_valid(opte)) {
2821 l2b->l2b_occupancy++;
2823 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2824 VM_PROT_READ | VM_PROT_WRITE);
2825 if (flags & KENTER_CACHE)
2826 *pte |= pte_l2_s_cache_mode;
2827 if (flags & KENTER_USER)
2828 *pte |= L2_S_PROT_U;
2831 /* kernel direct mappings can be shared, so use a pv_entry
2832 * to ensure proper caching.
2834 * The pvzone is used to delay the recording of kernel
2835 * mappings until the VM is running.
2837 * This expects the physical memory to have vm_page_array entry.
2839 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa))) {
2840 vm_page_lock_queues();
2841 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva) {
2842 /* release vm_page lock for pv_entry UMA */
2843 vm_page_unlock_queues();
2844 if ((pve = pmap_get_pv_entry()) == NULL)
2845 panic("pmap_kenter_internal: no pv entries");
2846 vm_page_lock_queues();
2847 PMAP_LOCK(pmap_kernel());
2848 pmap_enter_pv(m, pve, pmap_kernel(), va,
2849 PVF_WRITE | PVF_UNMAN);
2850 pmap_fix_cache(m, pmap_kernel(), va);
2851 PMAP_UNLOCK(pmap_kernel());
2855 vm_page_unlock_queues();
2860 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2862 pmap_kenter_internal(va, pa, KENTER_CACHE);
2866 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2869 pmap_kenter_internal(va, pa, 0);
2873 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2876 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2878 * Call pmap_fault_fixup now, to make sure we'll have no exception
2879 * at the first use of the new address, or bad things will happen,
2880 * as we use one of these addresses in the exception handlers.
2882 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2886 * remove a page from the kernel pagetables
2889 pmap_kremove(vm_offset_t va)
2891 struct l2_bucket *l2b;
2892 pt_entry_t *pte, opte;
2893 struct pv_entry *pve;
2897 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2900 KASSERT(l2b != NULL, ("No L2 Bucket"));
2901 pte = &l2b->l2b_kva[l2pte_index(va)];
2903 if (l2pte_valid(opte)) {
2904 /* pa = vtophs(va) taken from pmap_extract() */
2905 switch (opte & L2_TYPE_MASK) {
2907 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2910 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2913 /* note: should never have to remove an allocation
2914 * before the pvzone is initialized.
2916 vm_page_lock_queues();
2917 PMAP_LOCK(pmap_kernel());
2918 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2919 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2920 pmap_free_pv_entry(pve);
2921 PMAP_UNLOCK(pmap_kernel());
2922 vm_page_unlock_queues();
2923 va = va & ~PAGE_MASK;
2924 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2925 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2926 cpu_tlb_flushD_SE(va);
2934 * Used to map a range of physical addresses into kernel
2935 * virtual address space.
2937 * The value passed in '*virt' is a suggested virtual address for
2938 * the mapping. Architectures which can support a direct-mapped
2939 * physical to virtual region can return the appropriate address
2940 * within that region, leaving '*virt' unchanged. Other
2941 * architectures should map the pages starting at '*virt' and
2942 * update '*virt' with the first usable address after the mapped
2946 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2948 #ifdef ARM_USE_SMALL_ALLOC
2949 return (arm_ptovirt(start));
2951 vm_offset_t sva = *virt;
2952 vm_offset_t va = sva;
2954 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2955 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2958 while (start < end) {
2959 pmap_kenter(va, start);
2969 pmap_wb_page(vm_page_t m)
2971 struct pv_entry *pv;
2973 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2974 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2975 (pv->pv_flags & PVF_WRITE) == 0);
2979 pmap_inv_page(vm_page_t m)
2981 struct pv_entry *pv;
2983 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2984 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2987 * Add a list of wired pages to the kva
2988 * this routine is only used for temporary
2989 * kernel mappings that do not need to have
2990 * page modification or references recorded.
2991 * Note that old mappings are simply written
2992 * over. The page *must* be wired.
2995 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2999 for (i = 0; i < count; i++) {
3001 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3009 * this routine jerks page mappings from the
3010 * kernel -- it is meant only for temporary mappings.
3013 pmap_qremove(vm_offset_t va, int count)
3018 for (i = 0; i < count; i++) {
3021 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
3030 * pmap_object_init_pt preloads the ptes for a given object
3031 * into the specified pmap. This eliminates the blast of soft
3032 * faults on process startup and immediately after an mmap.
3035 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3036 vm_pindex_t pindex, vm_size_t size)
3039 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3040 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3041 ("pmap_object_init_pt: non-device object"));
3046 * pmap_is_prefaultable:
3048 * Return whether or not the specified virtual address is elgible
3052 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3057 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3059 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3066 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3067 * Returns TRUE if the mapping exists, else FALSE.
3069 * NOTE: This function is only used by a couple of arm-specific modules.
3070 * It is not safe to take any pmap locks here, since we could be right
3071 * in the middle of debugging the pmap anyway...
3073 * It is possible for this routine to return FALSE even though a valid
3074 * mapping does exist. This is because we don't lock, so the metadata
3075 * state may be inconsistent.
3077 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3078 * a "section" mapping.
3081 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3083 struct l2_dtable *l2;
3084 pd_entry_t *pl1pd, l1pd;
3088 if (pm->pm_l1 == NULL)
3092 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3095 if (l1pte_section_p(l1pd)) {
3100 if (pm->pm_l2 == NULL)
3103 l2 = pm->pm_l2[L2_IDX(l1idx)];
3106 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3110 *ptp = &ptep[l2pte_index(va)];
3115 * Routine: pmap_remove_all
3117 * Removes this physical page from
3118 * all physical maps in which it resides.
3119 * Reflects back modify bits to the pager.
3122 * Original versions of this routine were very
3123 * inefficient because they iteratively called
3124 * pmap_remove (slow...)
3127 pmap_remove_all(vm_page_t m)
3131 struct l2_bucket *l2b;
3132 boolean_t flush = FALSE;
3136 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3137 ("pmap_remove_all: page %p is not managed", m));
3138 if (TAILQ_EMPTY(&m->md.pv_list))
3140 vm_page_lock_queues();
3141 pmap_remove_write(m);
3142 curpm = vmspace_pmap(curproc->p_vmspace);
3143 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3144 if (flush == FALSE && (pv->pv_pmap == curpm ||
3145 pv->pv_pmap == pmap_kernel()))
3148 PMAP_LOCK(pv->pv_pmap);
3150 * Cached contents were written-back in pmap_remove_write(),
3151 * but we still have to invalidate the cache entry to make
3152 * sure stale data are not retrieved when another page will be
3153 * mapped under this virtual address.
3155 if (pmap_is_current(pv->pv_pmap)) {
3156 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3157 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3158 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3161 if (pv->pv_flags & PVF_UNMAN) {
3162 /* remove the pv entry, but do not remove the mapping
3163 * and remember this is a kernel mapped page
3165 m->md.pv_kva = pv->pv_va;
3167 /* remove the mapping and pv entry */
3168 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3169 KASSERT(l2b != NULL, ("No l2 bucket"));
3170 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3172 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3173 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3174 pv->pv_pmap->pm_stats.resident_count--;
3175 flags |= pv->pv_flags;
3177 pmap_nuke_pv(m, pv->pv_pmap, pv);
3178 PMAP_UNLOCK(pv->pv_pmap);
3179 pmap_free_pv_entry(pv);
3183 if (PV_BEEN_EXECD(flags))
3184 pmap_tlb_flushID(curpm);
3186 pmap_tlb_flushD(curpm);
3188 vm_page_aflag_clear(m, PGA_WRITEABLE);
3189 vm_page_unlock_queues();
3194 * Set the physical protection on the
3195 * specified range of this map as requested.
3198 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3200 struct l2_bucket *l2b;
3201 pt_entry_t *ptep, pte;
3202 vm_offset_t next_bucket;
3206 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3207 pm, sva, eva, prot);
3209 if ((prot & VM_PROT_READ) == 0) {
3210 pmap_remove(pm, sva, eva);
3214 if (prot & VM_PROT_WRITE) {
3216 * If this is a read->write transition, just ignore it and let
3217 * vm_fault() take care of it later.
3222 vm_page_lock_queues();
3226 * OK, at this point, we know we're doing write-protect operation.
3227 * If the pmap is active, write-back the range.
3229 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3231 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3235 next_bucket = L2_NEXT_BUCKET(sva);
3236 if (next_bucket > eva)
3239 l2b = pmap_get_l2_bucket(pm, sva);
3245 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3247 while (sva < next_bucket) {
3248 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3252 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3253 pte &= ~L2_S_PROT_W;
3258 if (!(pg->oflags & VPO_UNMANAGED)) {
3259 f = pmap_modify_pv(pg, pm, sva,
3265 f = PVF_REF | PVF_EXEC;
3271 if (PV_BEEN_EXECD(f))
3272 pmap_tlb_flushID_SE(pm, sva);
3274 if (PV_BEEN_REFD(f))
3275 pmap_tlb_flushD_SE(pm, sva);
3285 if (PV_BEEN_EXECD(flags))
3286 pmap_tlb_flushID(pm);
3288 if (PV_BEEN_REFD(flags))
3289 pmap_tlb_flushD(pm);
3291 vm_page_unlock_queues();
3298 * Insert the given physical page (p) at
3299 * the specified virtual address (v) in the
3300 * target physical map with the protection requested.
3302 * If specified, the page will be wired down, meaning
3303 * that the related pte can not be reclaimed.
3305 * NB: This is the only routine which MAY NOT lazy-evaluate
3306 * or lose information. That is, this routine must actually
3307 * insert this page into the given map NOW.
3311 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3312 vm_prot_t prot, boolean_t wired)
3315 vm_page_lock_queues();
3317 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3318 vm_page_unlock_queues();
3323 * The page queues and pmap must be locked.
3326 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3327 boolean_t wired, int flags)
3329 struct l2_bucket *l2b = NULL;
3330 struct vm_page *opg;
3331 struct pv_entry *pve = NULL;
3332 pt_entry_t *ptep, npte, opte;
3337 PMAP_ASSERT_LOCKED(pmap);
3338 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3339 if (va == vector_page) {
3340 pa = systempage.pv_pa;
3343 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3344 (flags & M_NOWAIT) != 0,
3345 ("pmap_enter_locked: page %p is not busy", m));
3346 pa = VM_PAGE_TO_PHYS(m);
3349 if (prot & VM_PROT_WRITE)
3350 nflags |= PVF_WRITE;
3351 if (prot & VM_PROT_EXECUTE)
3354 nflags |= PVF_WIRED;
3355 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3356 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3358 if (pmap == pmap_kernel()) {
3359 l2b = pmap_get_l2_bucket(pmap, va);
3361 l2b = pmap_grow_l2_bucket(pmap, va);
3364 l2b = pmap_alloc_l2_bucket(pmap, va);
3366 if (flags & M_WAITOK) {
3368 vm_page_unlock_queues();
3370 vm_page_lock_queues();
3378 ptep = &l2b->l2b_kva[l2pte_index(va)];
3385 * There is already a mapping at this address.
3386 * If the physical address is different, lookup the
3389 if (l2pte_pa(opte) != pa)
3390 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3396 if ((prot & (VM_PROT_ALL)) ||
3397 (!m || m->md.pvh_attrs & PVF_REF)) {
3399 * - The access type indicates that we don't need
3400 * to do referenced emulation.
3402 * - The physical page has already been referenced
3403 * so no need to re-do referenced emulation here.
3409 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3410 (m->md.pvh_attrs & PVF_MOD))) {
3412 * This is a writable mapping, and the
3413 * page's mod state indicates it has
3414 * already been modified. Make it
3415 * writable from the outset.
3418 if (!(m->md.pvh_attrs & PVF_MOD))
3422 vm_page_aflag_set(m, PGA_REFERENCED);
3425 * Need to do page referenced emulation.
3427 npte |= L2_TYPE_INV;
3430 if (prot & VM_PROT_WRITE) {
3431 npte |= L2_S_PROT_W;
3433 (m->oflags & VPO_UNMANAGED) == 0)
3434 vm_page_aflag_set(m, PGA_WRITEABLE);
3436 npte |= pte_l2_s_cache_mode;
3437 if (m && m == opg) {
3439 * We're changing the attrs of an existing mapping.
3441 oflags = pmap_modify_pv(m, pmap, va,
3442 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3443 PVF_MOD | PVF_REF, nflags);
3446 * We may need to flush the cache if we're
3449 if (pmap_is_current(pmap) &&
3450 (oflags & PVF_NC) == 0 &&
3451 (opte & L2_S_PROT_W) != 0 &&
3452 (prot & VM_PROT_WRITE) == 0 &&
3453 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3454 cpu_dcache_wb_range(va, PAGE_SIZE);
3455 cpu_l2cache_wb_range(va, PAGE_SIZE);
3459 * New mapping, or changing the backing page
3460 * of an existing mapping.
3464 * Replacing an existing mapping with a new one.
3465 * It is part of our managed memory so we
3466 * must remove it from the PV list
3468 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3470 /* note for patch: the oflags/invalidation was moved
3471 * because PG_FICTITIOUS pages could free the pve
3473 oflags = pve->pv_flags;
3475 * If the old mapping was valid (ref/mod
3476 * emulation creates 'invalid' mappings
3477 * initially) then make sure to frob
3480 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3481 if (PV_BEEN_EXECD(oflags)) {
3482 pmap_idcache_wbinv_range(pmap, va,
3485 if (PV_BEEN_REFD(oflags)) {
3486 pmap_dcache_wb_range(pmap, va,
3488 (oflags & PVF_WRITE) == 0);
3492 /* free/allocate a pv_entry for UNMANAGED pages if
3493 * this physical page is not/is already mapped.
3496 if (m && (m->oflags & VPO_UNMANAGED) &&
3498 TAILQ_EMPTY(&m->md.pv_list)) {
3499 pmap_free_pv_entry(pve);
3503 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3504 !TAILQ_EMPTY(&m->md.pv_list)))
3505 pve = pmap_get_pv_entry();
3507 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3508 !TAILQ_EMPTY(&m->md.pv_list)))
3509 pve = pmap_get_pv_entry();
3512 if ((m->oflags & VPO_UNMANAGED)) {
3513 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3515 KASSERT(pve != NULL, ("No pv"));
3516 nflags |= PVF_UNMAN;
3517 pmap_enter_pv(m, pve, pmap, va, nflags);
3521 KASSERT(va < kmi.clean_sva ||
3522 va >= kmi.clean_eva,
3523 ("pmap_enter: managed mapping within the clean submap"));
3524 KASSERT(pve != NULL, ("No pv"));
3525 pmap_enter_pv(m, pve, pmap, va, nflags);
3530 * Make sure userland mappings get the right permissions
3532 if (pmap != pmap_kernel() && va != vector_page) {
3533 npte |= L2_S_PROT_U;
3537 * Keep the stats up to date
3540 l2b->l2b_occupancy++;
3541 pmap->pm_stats.resident_count++;
3545 * If this is just a wiring change, the two PTEs will be
3546 * identical, so there's no need to update the page table.
3549 boolean_t is_cached = pmap_is_current(pmap);
3554 * We only need to frob the cache/tlb if this pmap
3558 if (L1_IDX(va) != L1_IDX(vector_page) &&
3559 l2pte_valid(npte)) {
3561 * This mapping is likely to be accessed as
3562 * soon as we return to userland. Fix up the
3563 * L1 entry to avoid taking another
3564 * page/domain fault.
3566 pd_entry_t *pl1pd, l1pd;
3568 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3569 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3571 if (*pl1pd != l1pd) {
3578 if (PV_BEEN_EXECD(oflags))
3579 pmap_tlb_flushID_SE(pmap, va);
3580 else if (PV_BEEN_REFD(oflags))
3581 pmap_tlb_flushD_SE(pmap, va);
3585 pmap_fix_cache(m, pmap, va);
3590 * Maps a sequence of resident pages belonging to the same object.
3591 * The sequence begins with the given page m_start. This page is
3592 * mapped at the given virtual address start. Each subsequent page is
3593 * mapped at a virtual address that is offset from start by the same
3594 * amount as the page is offset from m_start within the object. The
3595 * last page in the sequence is the page with the largest offset from
3596 * m_start that can be mapped at a virtual address less than the given
3597 * virtual address end. Not every virtual page between start and end
3598 * is mapped; only those for which a resident page exists with the
3599 * corresponding offset from m_start are mapped.
3602 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3603 vm_page_t m_start, vm_prot_t prot)
3606 vm_pindex_t diff, psize;
3608 psize = atop(end - start);
3610 vm_page_lock_queues();
3612 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3613 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3614 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3615 m = TAILQ_NEXT(m, listq);
3617 vm_page_unlock_queues();
3622 * this code makes some *MAJOR* assumptions:
3623 * 1. Current pmap & pmap exists.
3626 * 4. No page table pages.
3627 * but is *MUCH* faster than pmap_enter...
3631 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3634 vm_page_lock_queues();
3636 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3638 vm_page_unlock_queues();
3643 * Routine: pmap_change_wiring
3644 * Function: Change the wiring attribute for a map/virtual-address
3646 * In/out conditions:
3647 * The mapping must already exist in the pmap.
3650 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3652 struct l2_bucket *l2b;
3653 pt_entry_t *ptep, pte;
3656 vm_page_lock_queues();
3658 l2b = pmap_get_l2_bucket(pmap, va);
3659 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3660 ptep = &l2b->l2b_kva[l2pte_index(va)];
3662 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3664 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0);
3665 vm_page_unlock_queues();
3671 * Copy the range specified by src_addr/len
3672 * from the source map to the range dst_addr/len
3673 * in the destination map.
3675 * This routine is only advisory and need not do anything.
3678 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3679 vm_size_t len, vm_offset_t src_addr)
3685 * Routine: pmap_extract
3687 * Extract the physical page address associated
3688 * with the given map/virtual_address pair.
3691 pmap_extract(pmap_t pm, vm_offset_t va)
3693 struct l2_dtable *l2;
3695 pt_entry_t *ptep, pte;
3701 l1pd = pm->pm_l1->l1_kva[l1idx];
3702 if (l1pte_section_p(l1pd)) {
3704 * These should only happen for pmap_kernel()
3706 KASSERT(pm == pmap_kernel(), ("huh"));
3707 /* XXX: what to do about the bits > 32 ? */
3708 if (l1pd & L1_S_SUPERSEC)
3709 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3711 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3714 * Note that we can't rely on the validity of the L1
3715 * descriptor as an indication that a mapping exists.
3716 * We have to look it up in the L2 dtable.
3718 l2 = pm->pm_l2[L2_IDX(l1idx)];
3721 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3726 ptep = &ptep[l2pte_index(va)];
3734 switch (pte & L2_TYPE_MASK) {
3736 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3740 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3750 * Atomically extract and hold the physical page with the given
3751 * pmap and virtual address pair if that mapping permits the given
3756 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3758 struct l2_dtable *l2;
3760 pt_entry_t *ptep, pte;
3761 vm_paddr_t pa, paddr;
3769 l1pd = pmap->pm_l1->l1_kva[l1idx];
3770 if (l1pte_section_p(l1pd)) {
3772 * These should only happen for pmap_kernel()
3774 KASSERT(pmap == pmap_kernel(), ("huh"));
3775 /* XXX: what to do about the bits > 32 ? */
3776 if (l1pd & L1_S_SUPERSEC)
3777 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3779 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3780 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3782 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3783 m = PHYS_TO_VM_PAGE(pa);
3789 * Note that we can't rely on the validity of the L1
3790 * descriptor as an indication that a mapping exists.
3791 * We have to look it up in the L2 dtable.
3793 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3796 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3801 ptep = &ptep[l2pte_index(va)];
3808 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3809 switch (pte & L2_TYPE_MASK) {
3811 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3815 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3818 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3820 m = PHYS_TO_VM_PAGE(pa);
3826 PA_UNLOCK_COND(paddr);
3831 * Initialize a preallocated and zeroed pmap structure,
3832 * such as one in a vmspace structure.
3836 pmap_pinit(pmap_t pmap)
3838 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3840 PMAP_LOCK_INIT(pmap);
3841 pmap_alloc_l1(pmap);
3842 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3844 CPU_ZERO(&pmap->pm_active);
3846 TAILQ_INIT(&pmap->pm_pvlist);
3847 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3848 pmap->pm_stats.resident_count = 1;
3849 if (vector_page < KERNBASE) {
3850 pmap_enter(pmap, vector_page,
3851 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3858 /***************************************************
3859 * page management routines.
3860 ***************************************************/
3864 pmap_free_pv_entry(pv_entry_t pv)
3867 uma_zfree(pvzone, pv);
3872 * get a new pv_entry, allocating a block from the system
3874 * the memory allocation is performed bypassing the malloc code
3875 * because of the possibility of allocations at interrupt time.
3878 pmap_get_pv_entry(void)
3880 pv_entry_t ret_value;
3883 if (pv_entry_count > pv_entry_high_water)
3884 pagedaemon_wakeup();
3885 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3890 * Remove the given range of addresses from the specified map.
3892 * It is assumed that the start and end are properly
3893 * rounded to the page size.
3895 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3897 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3899 struct l2_bucket *l2b;
3900 vm_offset_t next_bucket;
3903 u_int mappings, is_exec, is_refd;
3908 * we lock in the pmap => pv_head direction
3911 vm_page_lock_queues();
3916 * Do one L2 bucket's worth at a time.
3918 next_bucket = L2_NEXT_BUCKET(sva);
3919 if (next_bucket > eva)
3922 l2b = pmap_get_l2_bucket(pm, sva);
3928 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3931 while (sva < next_bucket) {
3940 * Nothing here, move along
3947 pm->pm_stats.resident_count--;
3953 * Update flags. In a number of circumstances,
3954 * we could cluster a lot of these and do a
3955 * number of sequential pages in one go.
3957 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3958 struct pv_entry *pve;
3960 pve = pmap_remove_pv(pg, pm, sva);
3962 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3963 is_refd = PV_BEEN_REFD(pve->pv_flags);
3964 pmap_free_pv_entry(pve);
3968 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3969 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3972 cpu_idcache_wbinv_range(sva,
3974 cpu_l2cache_wbinv_range(sva,
3976 cpu_tlb_flushID_SE(sva);
3977 } else if (is_refd) {
3978 cpu_dcache_wbinv_range(sva,
3980 cpu_l2cache_wbinv_range(sva,
3982 cpu_tlb_flushD_SE(sva);
3984 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3985 /* flushall will also only get set for
3986 * for a current pmap
3988 cpu_idcache_wbinv_all();
3989 cpu_l2cache_wbinv_all();
4002 pmap_free_l2_bucket(pm, l2b, mappings);
4005 vm_page_unlock_queues();
4014 * Zero a given physical page by mapping it at a page hook point.
4015 * In doing the zero page op, the page we zero is mapped cachable, as with
4016 * StrongARM accesses to non-cached pages are non-burst making writing
4017 * _any_ bulk data very slow.
4019 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
4021 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4023 #ifdef ARM_USE_SMALL_ALLOC
4028 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4030 if (pg->md.pvh_list != NULL)
4031 panic("pmap_zero_page: page has mappings");
4034 if (_arm_bzero && size >= _min_bzero_size &&
4035 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4038 #ifdef ARM_USE_SMALL_ALLOC
4039 dstpg = (char *)arm_ptovirt(phys);
4040 if (off || size != PAGE_SIZE) {
4041 bzero(dstpg + off, size);
4042 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4043 cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size);
4045 bzero_page((vm_offset_t)dstpg);
4046 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4047 cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4053 * Hook in the page, zero it, invalidate the TLB as needed.
4055 * Note the temporary zero-page mapping must be a non-cached page in
4056 * order to work without corruption when write-allocate is enabled.
4058 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
4060 cpu_tlb_flushD_SE(cdstp);
4062 if (off || size != PAGE_SIZE)
4063 bzero((void *)(cdstp + off), size);
4070 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4072 #if ARM_MMU_XSCALE == 1
4074 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4076 #ifdef ARM_USE_SMALL_ALLOC
4080 if (_arm_bzero && size >= _min_bzero_size &&
4081 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4083 #ifdef ARM_USE_SMALL_ALLOC
4084 dstpg = (char *)arm_ptovirt(phys);
4085 if (off || size != PAGE_SIZE) {
4086 bzero(dstpg + off, size);
4087 cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size);
4089 bzero_page((vm_offset_t)dstpg);
4090 cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE);
4095 * Hook in the page, zero it, and purge the cache for that
4096 * zeroed page. Invalidate the TLB as needed.
4098 *cdst_pte = L2_S_PROTO | phys |
4099 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4100 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4102 cpu_tlb_flushD_SE(cdstp);
4104 if (off || size != PAGE_SIZE)
4105 bzero((void *)(cdstp + off), size);
4109 xscale_cache_clean_minidata();
4114 * Change the PTEs for the specified kernel mappings such that they
4115 * will use the mini data cache instead of the main data cache.
4118 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4120 struct l2_bucket *l2b;
4121 pt_entry_t *ptep, *sptep, pte;
4122 vm_offset_t next_bucket, eva;
4124 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4125 if (xscale_use_minidata == 0)
4132 next_bucket = L2_NEXT_BUCKET(va);
4133 if (next_bucket > eva)
4136 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4138 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4140 while (va < next_bucket) {
4142 if (!l2pte_minidata(pte)) {
4143 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4144 cpu_tlb_flushD_SE(va);
4145 *ptep = pte & ~L2_B;
4150 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4154 #endif /* ARM_MMU_XSCALE == 1 */
4157 * pmap_zero_page zeros the specified hardware page by mapping
4158 * the page into KVM and using bzero to clear its contents.
4161 pmap_zero_page(vm_page_t m)
4163 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4168 * pmap_zero_page_area zeros the specified hardware page by mapping
4169 * the page into KVM and using bzero to clear its contents.
4171 * off and size may not cover an area beyond a single hardware page.
4174 pmap_zero_page_area(vm_page_t m, int off, int size)
4177 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4182 * pmap_zero_page_idle zeros the specified hardware page by mapping
4183 * the page into KVM and using bzero to clear its contents. This
4184 * is intended to be called from the vm_pagezero process only and
4188 pmap_zero_page_idle(vm_page_t m)
4198 * This is a local function used to work out the best strategy to clean
4199 * a single page referenced by its entry in the PV table. It should be used by
4200 * pmap_copy_page, pmap_zero page and maybe some others later on.
4202 * Its policy is effectively:
4203 * o If there are no mappings, we don't bother doing anything with the cache.
4204 * o If there is one mapping, we clean just that page.
4205 * o If there are multiple mappings, we clean the entire cache.
4207 * So that some functions can be further optimised, it returns 0 if it didn't
4208 * clean the entire cache, or 1 if it did.
4210 * XXX One bug in this routine is that if the pv_entry has a single page
4211 * mapped at 0x00000000 a whole cache clean will be performed rather than
4212 * just the 1 page. Since this should not occur in everyday use and if it does
4213 * it will just result in not the most efficient clean for the page.
4215 * We don't yet use this function but may want to.
4218 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4220 pmap_t pm, pm_to_clean = NULL;
4221 struct pv_entry *npv;
4222 u_int cache_needs_cleaning = 0;
4224 vm_offset_t page_to_clean = 0;
4227 /* nothing mapped in so nothing to flush */
4232 * Since we flush the cache each time we change to a different
4233 * user vmspace, we only need to flush the page if it is in the
4237 pm = vmspace_pmap(curproc->p_vmspace);
4241 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4242 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4243 flags |= npv->pv_flags;
4245 * The page is mapped non-cacheable in
4246 * this map. No need to flush the cache.
4248 if (npv->pv_flags & PVF_NC) {
4250 if (cache_needs_cleaning)
4251 panic("pmap_clean_page: "
4252 "cache inconsistency");
4255 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4257 if (cache_needs_cleaning) {
4261 page_to_clean = npv->pv_va;
4262 pm_to_clean = npv->pv_pmap;
4264 cache_needs_cleaning = 1;
4267 if (page_to_clean) {
4268 if (PV_BEEN_EXECD(flags))
4269 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4272 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4273 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4274 } else if (cache_needs_cleaning) {
4275 if (PV_BEEN_EXECD(flags))
4276 pmap_idcache_wbinv_all(pm);
4278 pmap_dcache_wbinv_all(pm);
4286 * pmap_copy_page copies the specified (machine independent)
4287 * page by mapping the page into virtual memory and using
4288 * bcopy to copy the page, one machine dependent page at a
4295 * Copy one physical page into another, by mapping the pages into
4296 * hook points. The same comment regarding cachability as in
4297 * pmap_zero_page also applies here.
4299 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4301 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4304 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4307 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4309 if (dst_pg->md.pvh_list != NULL)
4310 panic("pmap_copy_page: dst page has mappings");
4315 * Clean the source page. Hold the source page's lock for
4316 * the duration of the copy so that no other mappings can
4317 * be created while we have a potentially aliased mapping.
4321 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4324 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4327 * Map the pages into the page hook points, copy them, and purge
4328 * the cache for the appropriate page. Invalidate the TLB
4332 *csrc_pte = L2_S_PROTO | src |
4333 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4335 *cdst_pte = L2_S_PROTO | dst |
4336 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4338 cpu_tlb_flushD_SE(csrcp);
4339 cpu_tlb_flushD_SE(cdstp);
4341 bcopy_page(csrcp, cdstp);
4343 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4344 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4345 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4346 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4350 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4351 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4355 *csrc_pte = L2_S_PROTO | a_phys |
4356 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4358 *cdst_pte = L2_S_PROTO | b_phys |
4359 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4361 cpu_tlb_flushD_SE(csrcp);
4362 cpu_tlb_flushD_SE(cdstp);
4364 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4366 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4367 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4368 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4369 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4371 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4373 #if ARM_MMU_XSCALE == 1
4375 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4378 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4379 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4382 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4384 if (dst_pg->md.pvh_list != NULL)
4385 panic("pmap_copy_page: dst page has mappings");
4390 * Clean the source page. Hold the source page's lock for
4391 * the duration of the copy so that no other mappings can
4392 * be created while we have a potentially aliased mapping.
4396 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4399 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4402 * Map the pages into the page hook points, copy them, and purge
4403 * the cache for the appropriate page. Invalidate the TLB
4407 *csrc_pte = L2_S_PROTO | src |
4408 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4409 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4411 *cdst_pte = L2_S_PROTO | dst |
4412 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4413 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4415 cpu_tlb_flushD_SE(csrcp);
4416 cpu_tlb_flushD_SE(cdstp);
4418 bcopy_page(csrcp, cdstp);
4420 xscale_cache_clean_minidata();
4424 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4425 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4429 *csrc_pte = L2_S_PROTO | a_phys |
4430 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4431 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4433 *cdst_pte = L2_S_PROTO | b_phys |
4434 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4435 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4437 cpu_tlb_flushD_SE(csrcp);
4438 cpu_tlb_flushD_SE(cdstp);
4440 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4442 xscale_cache_clean_minidata();
4444 #endif /* ARM_MMU_XSCALE == 1 */
4447 pmap_copy_page(vm_page_t src, vm_page_t dst)
4449 #ifdef ARM_USE_SMALL_ALLOC
4450 vm_offset_t srcpg, dstpg;
4453 cpu_dcache_wbinv_all();
4454 cpu_l2cache_wbinv_all();
4455 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4456 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4457 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4459 #ifdef ARM_USE_SMALL_ALLOC
4460 srcpg = arm_ptovirt(VM_PAGE_TO_PHYS(src));
4461 dstpg = arm_ptovirt(VM_PAGE_TO_PHYS(dst));
4462 bcopy_page(srcpg, dstpg);
4463 cpu_dcache_wbinv_range(dstpg, PAGE_SIZE);
4464 cpu_l2cache_wbinv_range(dstpg, PAGE_SIZE);
4466 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4471 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4472 vm_offset_t b_offset, int xfersize)
4474 vm_page_t a_pg, b_pg;
4475 vm_offset_t a_pg_offset, b_pg_offset;
4477 #ifdef ARM_USE_SMALL_ALLOC
4478 vm_offset_t a_va, b_va;
4481 cpu_dcache_wbinv_all();
4482 cpu_l2cache_wbinv_all();
4483 while (xfersize > 0) {
4484 a_pg = ma[a_offset >> PAGE_SHIFT];
4485 a_pg_offset = a_offset & PAGE_MASK;
4486 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4487 b_pg = mb[b_offset >> PAGE_SHIFT];
4488 b_pg_offset = b_offset & PAGE_MASK;
4489 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4490 #ifdef ARM_USE_SMALL_ALLOC
4491 a_va = arm_ptovirt(VM_PAGE_TO_PHYS(a_pg)) + a_pg_offset;
4492 b_va = arm_ptovirt(VM_PAGE_TO_PHYS(b_pg)) + b_pg_offset;
4493 bcopy((char *)a_va, (char *)b_va, cnt);
4494 cpu_dcache_wbinv_range(b_va, cnt);
4495 cpu_l2cache_wbinv_range(b_va, cnt);
4497 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4498 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4507 * this routine returns true if a physical page resides
4508 * in the given pmap.
4511 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4517 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4518 ("pmap_page_exists_quick: page %p is not managed", m));
4520 vm_page_lock_queues();
4521 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4522 if (pv->pv_pmap == pmap) {
4530 vm_page_unlock_queues();
4535 * pmap_page_wired_mappings:
4537 * Return the number of managed mappings to the given physical page
4541 pmap_page_wired_mappings(vm_page_t m)
4547 if ((m->oflags & VPO_UNMANAGED) != 0)
4549 vm_page_lock_queues();
4550 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4551 if ((pv->pv_flags & PVF_WIRED) != 0)
4553 vm_page_unlock_queues();
4558 * pmap_ts_referenced:
4560 * Return the count of reference bits for a page, clearing all of them.
4563 pmap_ts_referenced(vm_page_t m)
4566 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4567 ("pmap_ts_referenced: page %p is not managed", m));
4568 return (pmap_clearbit(m, PVF_REF));
4573 pmap_is_modified(vm_page_t m)
4576 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4577 ("pmap_is_modified: page %p is not managed", m));
4578 if (m->md.pvh_attrs & PVF_MOD)
4586 * Clear the modify bits on the specified physical page.
4589 pmap_clear_modify(vm_page_t m)
4592 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4593 ("pmap_clear_modify: page %p is not managed", m));
4594 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4595 KASSERT((m->oflags & VPO_BUSY) == 0,
4596 ("pmap_clear_modify: page %p is busy", m));
4599 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4600 * If the object containing the page is locked and the page is not
4601 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4603 if ((m->aflags & PGA_WRITEABLE) == 0)
4605 if (m->md.pvh_attrs & PVF_MOD)
4606 pmap_clearbit(m, PVF_MOD);
4611 * pmap_is_referenced:
4613 * Return whether or not the specified physical page was referenced
4614 * in any physical maps.
4617 pmap_is_referenced(vm_page_t m)
4620 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4621 ("pmap_is_referenced: page %p is not managed", m));
4622 return ((m->md.pvh_attrs & PVF_REF) != 0);
4626 * pmap_clear_reference:
4628 * Clear the reference bit on the specified physical page.
4631 pmap_clear_reference(vm_page_t m)
4634 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4635 ("pmap_clear_reference: page %p is not managed", m));
4636 if (m->md.pvh_attrs & PVF_REF)
4637 pmap_clearbit(m, PVF_REF);
4642 * Clear the write and modified bits in each of the given page's mappings.
4645 pmap_remove_write(vm_page_t m)
4648 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4649 ("pmap_remove_write: page %p is not managed", m));
4652 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4653 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4654 * is clear, no page table entries need updating.
4656 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4657 if ((m->oflags & VPO_BUSY) != 0 ||
4658 (m->aflags & PGA_WRITEABLE) != 0)
4659 pmap_clearbit(m, PVF_WRITE);
4664 * perform the pmap work for mincore
4667 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4669 printf("pmap_mincore()\n");
4676 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4682 * Increase the starting virtual address of the given mapping if a
4683 * different alignment might result in more superpage mappings.
4686 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4687 vm_offset_t *addr, vm_size_t size)
4693 * Map a set of physical memory pages into the kernel virtual
4694 * address space. Return a pointer to where it is mapped. This
4695 * routine is intended to be used for mapping device memory,
4699 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4701 vm_offset_t va, tmpva, offset;
4703 offset = pa & PAGE_MASK;
4704 size = roundup(size, PAGE_SIZE);
4708 va = kmem_alloc_nofault(kernel_map, size);
4710 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4711 for (tmpva = va; size > 0;) {
4712 pmap_kenter_internal(tmpva, pa, 0);
4718 return ((void *)(va + offset));
4721 #define BOOTSTRAP_DEBUG
4726 * Create a single section mapping.
4729 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4730 int prot, int cache)
4732 pd_entry_t *pde = (pd_entry_t *) l1pt;
4735 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4744 fl = pte_l1_s_cache_mode;
4748 fl = pte_l1_s_cache_mode_pt;
4752 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4753 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4754 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4761 * Link the L2 page table specified by l2pv.pv_pa into the L1
4762 * page table at the slot for "va".
4765 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4767 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4768 u_int slot = va >> L1_S_SHIFT;
4770 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4772 #ifdef VERBOSE_INIT_ARM
4773 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4776 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4778 PTE_SYNC(&pde[slot]);
4780 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4788 * Create a single page mapping.
4791 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4794 pd_entry_t *pde = (pd_entry_t *) l1pt;
4798 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4807 fl = pte_l2_s_cache_mode;
4811 fl = pte_l2_s_cache_mode_pt;
4815 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4816 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4818 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4821 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4823 pte[l2pte_index(va)] =
4824 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4825 PTE_SYNC(&pte[l2pte_index(va)]);
4831 * Map a chunk of memory using the most efficient mappings
4832 * possible (section. large page, small page) into the
4833 * provided L1 and L2 tables at the specified virtual address.
4836 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4837 vm_size_t size, int prot, int cache)
4839 pd_entry_t *pde = (pd_entry_t *) l1pt;
4840 pt_entry_t *pte, f1, f2s, f2l;
4844 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4847 panic("pmap_map_chunk: no L1 table provided");
4849 #ifdef VERBOSE_INIT_ARM
4850 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4851 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4863 f1 = pte_l1_s_cache_mode;
4864 f2l = pte_l2_l_cache_mode;
4865 f2s = pte_l2_s_cache_mode;
4869 f1 = pte_l1_s_cache_mode_pt;
4870 f2l = pte_l2_l_cache_mode_pt;
4871 f2s = pte_l2_s_cache_mode_pt;
4878 /* See if we can use a section mapping. */
4879 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4880 #ifdef VERBOSE_INIT_ARM
4883 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4884 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4885 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4886 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4894 * Ok, we're going to use an L2 table. Make sure
4895 * one is actually in the corresponding L1 slot
4896 * for the current VA.
4898 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4899 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4901 pte = (pt_entry_t *) kernel_pt_lookup(
4902 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4904 panic("pmap_map_chunk: can't find L2 table for VA"
4906 /* See if we can use a L2 large page mapping. */
4907 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4908 #ifdef VERBOSE_INIT_ARM
4911 for (i = 0; i < 16; i++) {
4912 pte[l2pte_index(va) + i] =
4914 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4915 PTE_SYNC(&pte[l2pte_index(va) + i]);
4923 /* Use a small page mapping. */
4924 #ifdef VERBOSE_INIT_ARM
4927 pte[l2pte_index(va)] =
4928 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4929 PTE_SYNC(&pte[l2pte_index(va)]);
4934 #ifdef VERBOSE_INIT_ARM
4941 /********************** Static device map routines ***************************/
4943 static const struct pmap_devmap *pmap_devmap_table;
4946 * Register the devmap table. This is provided in case early console
4947 * initialization needs to register mappings created by bootstrap code
4948 * before pmap_devmap_bootstrap() is called.
4951 pmap_devmap_register(const struct pmap_devmap *table)
4954 pmap_devmap_table = table;
4958 * Map all of the static regions in the devmap table, and remember
4959 * the devmap table so other parts of the kernel can look up entries
4963 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4967 pmap_devmap_table = table;
4969 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4970 #ifdef VERBOSE_INIT_ARM
4971 printf("devmap: %08x -> %08x @ %08x\n",
4972 pmap_devmap_table[i].pd_pa,
4973 pmap_devmap_table[i].pd_pa +
4974 pmap_devmap_table[i].pd_size - 1,
4975 pmap_devmap_table[i].pd_va);
4977 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4978 pmap_devmap_table[i].pd_pa,
4979 pmap_devmap_table[i].pd_size,
4980 pmap_devmap_table[i].pd_prot,
4981 pmap_devmap_table[i].pd_cache);
4985 const struct pmap_devmap *
4986 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4990 if (pmap_devmap_table == NULL)
4993 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4994 if (pa >= pmap_devmap_table[i].pd_pa &&
4995 pa + size <= pmap_devmap_table[i].pd_pa +
4996 pmap_devmap_table[i].pd_size)
4997 return (&pmap_devmap_table[i]);
5003 const struct pmap_devmap *
5004 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
5008 if (pmap_devmap_table == NULL)
5011 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
5012 if (va >= pmap_devmap_table[i].pd_va &&
5013 va + size <= pmap_devmap_table[i].pd_va +
5014 pmap_devmap_table[i].pd_size)
5015 return (&pmap_devmap_table[i]);