1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
82 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
83 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
84 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
85 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
86 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
87 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
88 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
89 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
90 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
91 * POSSIBILITY OF SUCH DAMAGE.
95 * Copyright (c) 1994-1998 Mark Brinicombe.
96 * Copyright (c) 1994 Brini.
97 * All rights reserved.
99 * This code is derived from software written for Brini by Mark Brinicombe
101 * Redistribution and use in source and binary forms, with or without
102 * modification, are permitted provided that the following conditions
104 * 1. Redistributions of source code must retain the above copyright
105 * notice, this list of conditions and the following disclaimer.
106 * 2. Redistributions in binary form must reproduce the above copyright
107 * notice, this list of conditions and the following disclaimer in the
108 * documentation and/or other materials provided with the distribution.
109 * 3. All advertising materials mentioning features or use of this software
110 * must display the following acknowledgement:
111 * This product includes software developed by Mark Brinicombe.
112 * 4. The name of the author may not be used to endorse or promote products
113 * derived from this software without specific prior written permission.
115 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
116 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
117 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
118 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
119 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
120 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
121 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
122 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
123 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
125 * RiscBSD kernel project
129 * Machine dependant vm stuff
135 * Special compilation symbols
136 * PMAP_DEBUG - Build in pmap_debug_level code
138 * Note that pmap_mapdev() and pmap_unmapdev() are implemented in arm/devmap.c
140 /* Include header files */
144 #include <sys/cdefs.h>
145 __FBSDID("$FreeBSD$");
146 #include <sys/param.h>
147 #include <sys/systm.h>
148 #include <sys/kernel.h>
150 #include <sys/lock.h>
151 #include <sys/proc.h>
152 #include <sys/malloc.h>
153 #include <sys/msgbuf.h>
154 #include <sys/mutex.h>
155 #include <sys/vmmeter.h>
156 #include <sys/mman.h>
157 #include <sys/rwlock.h>
159 #include <sys/sched.h>
162 #include <vm/vm_param.h>
165 #include <vm/vm_kern.h>
166 #include <vm/vm_object.h>
167 #include <vm/vm_map.h>
168 #include <vm/vm_page.h>
169 #include <vm/vm_pageout.h>
170 #include <vm/vm_phys.h>
171 #include <vm/vm_extern.h>
173 #include <machine/md_var.h>
174 #include <machine/cpu.h>
175 #include <machine/cpufunc.h>
176 #include <machine/pcb.h>
179 #define PDEBUG(_lev_,_stat_) \
180 if (pmap_debug_level >= (_lev_)) \
182 #define dprintf printf
184 int pmap_debug_level = 0;
186 #else /* PMAP_DEBUG */
187 #define PDEBUG(_lev_,_stat_) /* Nothing */
188 #define dprintf(x, arg...)
189 #define PMAP_INLINE __inline
190 #endif /* PMAP_DEBUG */
192 extern struct pv_addr systempage;
194 extern int last_fault_code;
197 * Internal function prototypes
199 static void pmap_free_pv_entry (pv_entry_t);
200 static pv_entry_t pmap_get_pv_entry(void);
202 static void pmap_enter_locked(pmap_t, vm_offset_t, vm_page_t,
203 vm_prot_t, boolean_t, int);
204 static vm_paddr_t pmap_extract_locked(pmap_t pmap, vm_offset_t va);
205 static void pmap_fix_cache(struct vm_page *, pmap_t, vm_offset_t);
206 static void pmap_alloc_l1(pmap_t);
207 static void pmap_free_l1(pmap_t);
209 static int pmap_clearbit(struct vm_page *, u_int);
211 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
212 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
213 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
214 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
216 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
218 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
219 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
220 vm_offset_t pmap_curmaxkvaddr;
221 vm_paddr_t kernel_l1pa;
223 vm_offset_t kernel_vm_end = 0;
225 vm_offset_t vm_max_kernel_address;
227 struct pmap kernel_pmap_store;
229 static pt_entry_t *csrc_pte, *cdst_pte;
230 static vm_offset_t csrcp, cdstp;
231 static struct mtx cmtx;
233 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
235 * These routines are called when the CPU type is identified to set up
236 * the PTE prototypes, cache modes, etc.
238 * The variables are always here, just in case LKMs need to reference
239 * them (though, they shouldn't).
242 pt_entry_t pte_l1_s_cache_mode;
243 pt_entry_t pte_l1_s_cache_mode_pt;
244 pt_entry_t pte_l1_s_cache_mask;
246 pt_entry_t pte_l2_l_cache_mode;
247 pt_entry_t pte_l2_l_cache_mode_pt;
248 pt_entry_t pte_l2_l_cache_mask;
250 pt_entry_t pte_l2_s_cache_mode;
251 pt_entry_t pte_l2_s_cache_mode_pt;
252 pt_entry_t pte_l2_s_cache_mask;
254 pt_entry_t pte_l2_s_prot_u;
255 pt_entry_t pte_l2_s_prot_w;
256 pt_entry_t pte_l2_s_prot_mask;
258 pt_entry_t pte_l1_s_proto;
259 pt_entry_t pte_l1_c_proto;
260 pt_entry_t pte_l2_s_proto;
262 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
263 void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
264 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs,
266 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
268 struct msgbuf *msgbufp = 0;
273 static caddr_t crashdumpmap;
275 extern void bcopy_page(vm_offset_t, vm_offset_t);
276 extern void bzero_page(vm_offset_t);
278 extern vm_offset_t alloc_firstaddr;
283 * Metadata for L1 translation tables.
286 /* Entry on the L1 Table list */
287 SLIST_ENTRY(l1_ttable) l1_link;
289 /* Entry on the L1 Least Recently Used list */
290 TAILQ_ENTRY(l1_ttable) l1_lru;
292 /* Track how many domains are allocated from this L1 */
293 volatile u_int l1_domain_use_count;
296 * A free-list of domain numbers for this L1.
297 * We avoid using ffs() and a bitmap to track domains since ffs()
300 u_int8_t l1_domain_first;
301 u_int8_t l1_domain_free[PMAP_DOMAINS];
303 /* Physical address of this L1 page table */
304 vm_paddr_t l1_physaddr;
306 /* KVA of this L1 page table */
311 * Convert a virtual address into its L1 table index. That is, the
312 * index used to locate the L2 descriptor table pointer in an L1 table.
313 * This is basically used to index l1->l1_kva[].
315 * Each L2 descriptor table represents 1MB of VA space.
317 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
320 * L1 Page Tables are tracked using a Least Recently Used list.
321 * - New L1s are allocated from the HEAD.
322 * - Freed L1s are added to the TAIl.
323 * - Recently accessed L1s (where an 'access' is some change to one of
324 * the userland pmaps which owns this L1) are moved to the TAIL.
326 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
328 * A list of all L1 tables
330 static SLIST_HEAD(, l1_ttable) l1_list;
331 static struct mtx l1_lru_lock;
334 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
336 * This is normally 16MB worth L2 page descriptors for any given pmap.
337 * Reference counts are maintained for L2 descriptors so they can be
341 /* The number of L2 page descriptors allocated to this l2_dtable */
344 /* List of L2 page descriptors */
346 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
347 vm_paddr_t l2b_phys; /* Physical address of same */
348 u_short l2b_l1idx; /* This L2 table's L1 index */
349 u_short l2b_occupancy; /* How many active descriptors */
350 } l2_bucket[L2_BUCKET_SIZE];
353 /* pmap_kenter_internal flags */
354 #define KENTER_CACHE 0x1
355 #define KENTER_USER 0x2
358 * Given an L1 table index, calculate the corresponding l2_dtable index
359 * and bucket index within the l2_dtable.
361 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
363 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
366 * Given a virtual address, this macro returns the
367 * virtual address required to drop into the next L2 bucket.
369 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
372 * We try to map the page tables write-through, if possible. However, not
373 * all CPUs have a write-through cache mode, so on those we have to sync
374 * the cache when we frob page tables.
376 * We try to evaluate this at compile time, if possible. However, it's
377 * not always possible to do that, hence this run-time var.
379 int pmap_needs_pte_sync;
382 * Macro to determine if a mapping might be resident in the
383 * instruction cache and/or TLB
385 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
388 * Macro to determine if a mapping might be resident in the
389 * data cache and/or TLB
391 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
393 #ifndef PMAP_SHPGPERPROC
394 #define PMAP_SHPGPERPROC 200
397 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
398 curproc->p_vmspace->vm_map.pmap == (pm))
399 static uma_zone_t pvzone = NULL;
401 static uma_zone_t l2table_zone;
402 static vm_offset_t pmap_kernel_l2dtable_kva;
403 static vm_offset_t pmap_kernel_l2ptp_kva;
404 static vm_paddr_t pmap_kernel_l2ptp_phys;
405 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
406 static struct rwlock pvh_global_lock;
408 void pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
409 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
410 #if ARM_MMU_XSCALE == 1
411 void pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
412 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
416 * This list exists for the benefit of pmap_map_chunk(). It keeps track
417 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
418 * find them as necessary.
420 * Note that the data on this list MUST remain valid after initarm() returns,
421 * as pmap_bootstrap() uses it to contruct L2 table metadata.
423 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
426 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
431 l1->l1_domain_use_count = 0;
432 l1->l1_domain_first = 0;
434 for (i = 0; i < PMAP_DOMAINS; i++)
435 l1->l1_domain_free[i] = i + 1;
438 * Copy the kernel's L1 entries to each new L1.
440 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
441 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
443 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
444 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
445 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
446 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
450 kernel_pt_lookup(vm_paddr_t pa)
454 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
461 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
463 pmap_pte_init_generic(void)
466 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
467 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
469 pte_l2_l_cache_mode = L2_B|L2_C;
470 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
472 pte_l2_s_cache_mode = L2_B|L2_C;
473 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
476 * If we have a write-through cache, set B and C. If
477 * we have a write-back cache, then we assume setting
478 * only C will make those pages write-through.
480 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
481 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
482 pte_l2_l_cache_mode_pt = L2_B|L2_C;
483 pte_l2_s_cache_mode_pt = L2_B|L2_C;
485 pte_l1_s_cache_mode_pt = L1_S_C;
486 pte_l2_l_cache_mode_pt = L2_C;
487 pte_l2_s_cache_mode_pt = L2_C;
490 pte_l2_s_prot_u = L2_S_PROT_U_generic;
491 pte_l2_s_prot_w = L2_S_PROT_W_generic;
492 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
494 pte_l1_s_proto = L1_S_PROTO_generic;
495 pte_l1_c_proto = L1_C_PROTO_generic;
496 pte_l2_s_proto = L2_S_PROTO_generic;
498 pmap_copy_page_func = pmap_copy_page_generic;
499 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
500 pmap_zero_page_func = pmap_zero_page_generic;
503 #if defined(CPU_ARM8)
505 pmap_pte_init_arm8(void)
509 * ARM8 is compatible with generic, but we need to use
510 * the page tables uncached.
512 pmap_pte_init_generic();
514 pte_l1_s_cache_mode_pt = 0;
515 pte_l2_l_cache_mode_pt = 0;
516 pte_l2_s_cache_mode_pt = 0;
518 #endif /* CPU_ARM8 */
520 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
522 pmap_pte_init_arm9(void)
526 * ARM9 is compatible with generic, but we want to use
527 * write-through caching for now.
529 pmap_pte_init_generic();
531 pte_l1_s_cache_mode = L1_S_C;
532 pte_l2_l_cache_mode = L2_C;
533 pte_l2_s_cache_mode = L2_C;
535 pte_l1_s_cache_mode_pt = L1_S_C;
536 pte_l2_l_cache_mode_pt = L2_C;
537 pte_l2_s_cache_mode_pt = L2_C;
539 #endif /* CPU_ARM9 */
540 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
542 #if defined(CPU_ARM10)
544 pmap_pte_init_arm10(void)
548 * ARM10 is compatible with generic, but we want to use
549 * write-through caching for now.
551 pmap_pte_init_generic();
553 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
554 pte_l2_l_cache_mode = L2_B | L2_C;
555 pte_l2_s_cache_mode = L2_B | L2_C;
557 pte_l1_s_cache_mode_pt = L1_S_C;
558 pte_l2_l_cache_mode_pt = L2_C;
559 pte_l2_s_cache_mode_pt = L2_C;
562 #endif /* CPU_ARM10 */
566 pmap_pte_init_sa1(void)
570 * The StrongARM SA-1 cache does not have a write-through
571 * mode. So, do the generic initialization, then reset
572 * the page table cache mode to B=1,C=1, and note that
573 * the PTEs need to be sync'd.
575 pmap_pte_init_generic();
577 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
578 pte_l2_l_cache_mode_pt = L2_B|L2_C;
579 pte_l2_s_cache_mode_pt = L2_B|L2_C;
581 pmap_needs_pte_sync = 1;
583 #endif /* ARM_MMU_SA1 == 1*/
585 #if ARM_MMU_XSCALE == 1
586 #if (ARM_NMMUS > 1) || defined (CPU_XSCALE_CORE3)
587 static u_int xscale_use_minidata;
591 pmap_pte_init_xscale(void)
594 int write_through = 0;
596 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
597 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
599 pte_l2_l_cache_mode = L2_B|L2_C;
600 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
602 pte_l2_s_cache_mode = L2_B|L2_C;
603 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
605 pte_l1_s_cache_mode_pt = L1_S_C;
606 pte_l2_l_cache_mode_pt = L2_C;
607 pte_l2_s_cache_mode_pt = L2_C;
608 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
610 * The XScale core has an enhanced mode where writes that
611 * miss the cache cause a cache line to be allocated. This
612 * is significantly faster than the traditional, write-through
613 * behavior of this case.
615 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
616 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
617 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
618 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
619 #ifdef XSCALE_CACHE_WRITE_THROUGH
621 * Some versions of the XScale core have various bugs in
622 * their cache units, the work-around for which is to run
623 * the cache in write-through mode. Unfortunately, this
624 * has a major (negative) impact on performance. So, we
625 * go ahead and run fast-and-loose, in the hopes that we
626 * don't line up the planets in a way that will trip the
629 * However, we give you the option to be slow-but-correct.
632 #elif defined(XSCALE_CACHE_WRITE_BACK)
633 /* force write back cache mode */
635 #elif defined(CPU_XSCALE_PXA2X0)
637 * Intel PXA2[15]0 processors are known to have a bug in
638 * write-back cache on revision 4 and earlier (stepping
639 * A[01] and B[012]). Fixed for C0 and later.
645 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
647 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
648 if ((id & CPU_ID_REVISION_MASK) < 5) {
649 /* write through for stepping A0-1 and B0-2 */
654 #endif /* XSCALE_CACHE_WRITE_THROUGH */
657 pte_l1_s_cache_mode = L1_S_C;
658 pte_l2_l_cache_mode = L2_C;
659 pte_l2_s_cache_mode = L2_C;
663 xscale_use_minidata = 1;
666 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
667 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
668 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
670 pte_l1_s_proto = L1_S_PROTO_xscale;
671 pte_l1_c_proto = L1_C_PROTO_xscale;
672 pte_l2_s_proto = L2_S_PROTO_xscale;
674 #ifdef CPU_XSCALE_CORE3
675 pmap_copy_page_func = pmap_copy_page_generic;
676 pmap_copy_page_offs_func = pmap_copy_page_offs_generic;
677 pmap_zero_page_func = pmap_zero_page_generic;
678 xscale_use_minidata = 0;
679 /* Make sure it is L2-cachable */
680 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_T);
681 pte_l1_s_cache_mode_pt = pte_l1_s_cache_mode &~ L1_S_XSCALE_P;
682 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_T) ;
683 pte_l2_l_cache_mode_pt = pte_l1_s_cache_mode;
684 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_T);
685 pte_l2_s_cache_mode_pt = pte_l2_s_cache_mode;
688 pmap_copy_page_func = pmap_copy_page_xscale;
689 pmap_copy_page_offs_func = pmap_copy_page_offs_xscale;
690 pmap_zero_page_func = pmap_zero_page_xscale;
694 * Disable ECC protection of page table access, for now.
696 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
697 auxctl &= ~XSCALE_AUXCTL_P;
698 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
702 * xscale_setup_minidata:
704 * Set up the mini-data cache clean area. We require the
705 * caller to allocate the right amount of physically and
706 * virtually contiguous space.
708 extern vm_offset_t xscale_minidata_clean_addr;
709 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
711 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
713 pd_entry_t *pde = (pd_entry_t *) l1pt;
718 xscale_minidata_clean_addr = va;
720 /* Round it to page size. */
721 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
724 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
725 pte = (pt_entry_t *) kernel_pt_lookup(
726 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
728 panic("xscale_setup_minidata: can't find L2 table for "
729 "VA 0x%08x", (u_int32_t) va);
730 pte[l2pte_index(va)] =
731 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
732 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
736 * Configure the mini-data cache for write-back with
737 * read/write-allocate.
739 * NOTE: In order to reconfigure the mini-data cache, we must
740 * make sure it contains no valid data! In order to do that,
741 * we must issue a global data cache invalidate command!
743 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
744 * THIS IS VERY IMPORTANT!
747 /* Invalidate data and mini-data. */
748 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
749 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
750 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
751 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
756 * Allocate an L1 translation table for the specified pmap.
757 * This is called at pmap creation time.
760 pmap_alloc_l1(pmap_t pm)
762 struct l1_ttable *l1;
766 * Remove the L1 at the head of the LRU list
768 mtx_lock(&l1_lru_lock);
769 l1 = TAILQ_FIRST(&l1_lru_list);
770 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
773 * Pick the first available domain number, and update
774 * the link to the next number.
776 domain = l1->l1_domain_first;
777 l1->l1_domain_first = l1->l1_domain_free[domain];
780 * If there are still free domain numbers in this L1,
781 * put it back on the TAIL of the LRU list.
783 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
784 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
786 mtx_unlock(&l1_lru_lock);
789 * Fix up the relevant bits in the pmap structure
792 pm->pm_domain = domain + 1;
796 * Free an L1 translation table.
797 * This is called at pmap destruction time.
800 pmap_free_l1(pmap_t pm)
802 struct l1_ttable *l1 = pm->pm_l1;
804 mtx_lock(&l1_lru_lock);
807 * If this L1 is currently on the LRU list, remove it.
809 if (l1->l1_domain_use_count < PMAP_DOMAINS)
810 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
813 * Free up the domain number which was allocated to the pmap
815 l1->l1_domain_free[pm->pm_domain - 1] = l1->l1_domain_first;
816 l1->l1_domain_first = pm->pm_domain - 1;
817 l1->l1_domain_use_count--;
820 * The L1 now must have at least 1 free domain, so add
821 * it back to the LRU list. If the use count is zero,
822 * put it at the head of the list, otherwise it goes
825 if (l1->l1_domain_use_count == 0) {
826 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
828 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
830 mtx_unlock(&l1_lru_lock);
834 * Returns a pointer to the L2 bucket associated with the specified pmap
835 * and VA, or NULL if no L2 bucket exists for the address.
837 static PMAP_INLINE struct l2_bucket *
838 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
840 struct l2_dtable *l2;
841 struct l2_bucket *l2b;
846 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
847 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
854 * Returns a pointer to the L2 bucket associated with the specified pmap
857 * If no L2 bucket exists, perform the necessary allocations to put an L2
858 * bucket/page table in place.
860 * Note that if a new L2 bucket/page was allocated, the caller *must*
861 * increment the bucket occupancy counter appropriately *before*
862 * releasing the pmap's lock to ensure no other thread or cpu deallocates
863 * the bucket/page in the meantime.
865 static struct l2_bucket *
866 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
868 struct l2_dtable *l2;
869 struct l2_bucket *l2b;
874 PMAP_ASSERT_LOCKED(pm);
875 rw_assert(&pvh_global_lock, RA_WLOCKED);
876 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
878 * No mapping at this address, as there is
879 * no entry in the L1 table.
880 * Need to allocate a new l2_dtable.
883 rw_wunlock(&pvh_global_lock);
884 if ((l2 = uma_zalloc(l2table_zone, M_NOWAIT)) == NULL) {
885 rw_wlock(&pvh_global_lock);
889 rw_wlock(&pvh_global_lock);
891 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
893 * Someone already allocated the l2_dtable while
894 * we were doing the same.
896 uma_zfree(l2table_zone, l2);
897 l2 = pm->pm_l2[L2_IDX(l1idx)];
899 bzero(l2, sizeof(*l2));
901 * Link it into the parent pmap
903 pm->pm_l2[L2_IDX(l1idx)] = l2;
907 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
910 * Fetch pointer to the L2 page table associated with the address.
912 if (l2b->l2b_kva == NULL) {
916 * No L2 page table has been allocated. Chances are, this
917 * is because we just allocated the l2_dtable, above.
920 rw_wunlock(&pvh_global_lock);
921 ptep = uma_zalloc(l2zone, M_NOWAIT);
922 rw_wlock(&pvh_global_lock);
924 if (l2b->l2b_kva != 0) {
925 /* We lost the race. */
926 uma_zfree(l2zone, ptep);
929 l2b->l2b_phys = vtophys(ptep);
932 * Oops, no more L2 page tables available at this
933 * time. We may need to deallocate the l2_dtable
934 * if we allocated a new one above.
936 if (l2->l2_occupancy == 0) {
937 pm->pm_l2[L2_IDX(l1idx)] = NULL;
938 uma_zfree(l2table_zone, l2);
945 l2b->l2b_l1idx = l1idx;
951 static PMAP_INLINE void
952 #ifndef PMAP_INCLUDE_PTE_SYNC
953 pmap_free_l2_ptp(pt_entry_t *l2)
955 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
958 #ifdef PMAP_INCLUDE_PTE_SYNC
960 * Note: With a write-back cache, we may need to sync this
961 * L2 table before re-using it.
962 * This is because it may have belonged to a non-current
963 * pmap, in which case the cache syncs would have been
964 * skipped when the pages were being unmapped. If the
965 * L2 table were then to be immediately re-allocated to
966 * the *current* pmap, it may well contain stale mappings
967 * which have not yet been cleared by a cache write-back
968 * and so would still be visible to the mmu.
971 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
973 uma_zfree(l2zone, l2);
976 * One or more mappings in the specified L2 descriptor table have just been
979 * Garbage collect the metadata and descriptor table itself if necessary.
981 * The pmap lock must be acquired when this is called (not necessary
982 * for the kernel pmap).
985 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
987 struct l2_dtable *l2;
988 pd_entry_t *pl1pd, l1pd;
994 * Update the bucket's reference count according to how many
995 * PTEs the caller has just invalidated.
997 l2b->l2b_occupancy -= count;
1002 * Level 2 page tables allocated to the kernel pmap are never freed
1003 * as that would require checking all Level 1 page tables and
1004 * removing any references to the Level 2 page table. See also the
1005 * comment elsewhere about never freeing bootstrap L2 descriptors.
1007 * We make do with just invalidating the mapping in the L2 table.
1009 * This isn't really a big deal in practice and, in fact, leads
1010 * to a performance win over time as we don't need to continually
1013 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1017 * There are no more valid mappings in this level 2 page table.
1018 * Go ahead and NULL-out the pointer in the bucket, then
1019 * free the page table.
1021 l1idx = l2b->l2b_l1idx;
1022 ptep = l2b->l2b_kva;
1023 l2b->l2b_kva = NULL;
1025 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1028 * If the L1 slot matches the pmap's domain
1029 * number, then invalidate it.
1031 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1032 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1038 * Release the L2 descriptor table back to the pool cache.
1040 #ifndef PMAP_INCLUDE_PTE_SYNC
1041 pmap_free_l2_ptp(ptep);
1043 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1047 * Update the reference count in the associated l2_dtable
1049 l2 = pm->pm_l2[L2_IDX(l1idx)];
1050 if (--l2->l2_occupancy > 0)
1054 * There are no more valid mappings in any of the Level 1
1055 * slots managed by this l2_dtable. Go ahead and NULL-out
1056 * the pointer in the parent pmap and free the l2_dtable.
1058 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1059 uma_zfree(l2table_zone, l2);
1063 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1067 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1069 #ifndef PMAP_INCLUDE_PTE_SYNC
1070 struct l2_bucket *l2b;
1071 pt_entry_t *ptep, pte;
1073 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1076 * The mappings for these page tables were initially made using
1077 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1078 * mode will not be right for page table mappings. To avoid
1079 * polluting the pmap_kenter() code with a special case for
1080 * page tables, we simply fix up the cache-mode here if it's not
1083 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1084 ptep = &l2b->l2b_kva[l2pte_index(va)];
1087 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1089 * Page tables must have the cache-mode set to
1092 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1094 cpu_tlb_flushD_SE(va);
1098 memset(mem, 0, L2_TABLE_SIZE_REAL);
1099 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1104 * A bunch of routines to conditionally flush the caches/TLB depending
1105 * on whether the specified pmap actually needs to be flushed at any
1108 static PMAP_INLINE void
1109 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1112 if (pmap_is_current(pm))
1113 cpu_tlb_flushID_SE(va);
1116 static PMAP_INLINE void
1117 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1120 if (pmap_is_current(pm))
1121 cpu_tlb_flushD_SE(va);
1124 static PMAP_INLINE void
1125 pmap_tlb_flushID(pmap_t pm)
1128 if (pmap_is_current(pm))
1131 static PMAP_INLINE void
1132 pmap_tlb_flushD(pmap_t pm)
1135 if (pmap_is_current(pm))
1140 pmap_has_valid_mapping(pmap_t pm, vm_offset_t va)
1145 if (pmap_get_pde_pte(pm, va, &pde, &ptep) &&
1146 ptep && ((*ptep & L2_TYPE_MASK) != L2_TYPE_INV))
1152 static PMAP_INLINE void
1153 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1157 CTR4(KTR_PMAP, "pmap_dcache_wbinv_range: pmap %p is_kernel %d va 0x%08x"
1158 " len 0x%x ", pm, pm == pmap_kernel(), va, len);
1160 if (pmap_is_current(pm) || pm == pmap_kernel()) {
1161 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1163 if (pmap_has_valid_mapping(pm, va)) {
1164 cpu_idcache_wbinv_range(va, rest);
1165 cpu_l2cache_wbinv_range(va, rest);
1169 rest = MIN(PAGE_SIZE, len);
1174 static PMAP_INLINE void
1175 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv,
1180 CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x "
1181 "len 0x%x ", pm, pm == pmap_kernel(), va, len);
1182 CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only);
1184 if (pmap_is_current(pm)) {
1185 rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len);
1187 if (pmap_has_valid_mapping(pm, va)) {
1188 if (do_inv && rd_only) {
1189 cpu_dcache_inv_range(va, rest);
1190 cpu_l2cache_inv_range(va, rest);
1191 } else if (do_inv) {
1192 cpu_dcache_wbinv_range(va, rest);
1193 cpu_l2cache_wbinv_range(va, rest);
1194 } else if (!rd_only) {
1195 cpu_dcache_wb_range(va, rest);
1196 cpu_l2cache_wb_range(va, rest);
1202 rest = MIN(PAGE_SIZE, len);
1207 static PMAP_INLINE void
1208 pmap_idcache_wbinv_all(pmap_t pm)
1211 if (pmap_is_current(pm)) {
1212 cpu_idcache_wbinv_all();
1213 cpu_l2cache_wbinv_all();
1218 static PMAP_INLINE void
1219 pmap_dcache_wbinv_all(pmap_t pm)
1222 if (pmap_is_current(pm)) {
1223 cpu_dcache_wbinv_all();
1224 cpu_l2cache_wbinv_all();
1232 * Make sure the pte is written out to RAM.
1233 * We need to do this for one of two cases:
1234 * - We're dealing with the kernel pmap
1235 * - There is no pmap active in the cache/tlb.
1236 * - The specified pmap is 'active' in the cache/tlb.
1238 #ifdef PMAP_INCLUDE_PTE_SYNC
1239 #define PTE_SYNC_CURRENT(pm, ptep) \
1241 if (PMAP_NEEDS_PTE_SYNC && \
1242 pmap_is_current(pm)) \
1244 } while (/*CONSTCOND*/0)
1246 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1250 * cacheable == -1 means we must make the entry uncacheable, 1 means
1253 static __inline void
1254 pmap_set_cache_entry(pv_entry_t pv, pmap_t pm, vm_offset_t va, int cacheable)
1256 struct l2_bucket *l2b;
1257 pt_entry_t *ptep, pte;
1259 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1260 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1262 if (cacheable == 1) {
1263 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1264 if (l2pte_valid(pte)) {
1265 if (PV_BEEN_EXECD(pv->pv_flags)) {
1266 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1267 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1268 pmap_tlb_flushD_SE(pv->pv_pmap, pv->pv_va);
1272 pte = *ptep &~ L2_S_CACHE_MASK;
1273 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1275 if (PV_BEEN_EXECD(pv->pv_flags)) {
1276 pmap_idcache_wbinv_range(pv->pv_pmap,
1277 pv->pv_va, PAGE_SIZE);
1278 pmap_tlb_flushID_SE(pv->pv_pmap, pv->pv_va);
1279 } else if (PV_BEEN_REFD(pv->pv_flags)) {
1280 pmap_dcache_wb_range(pv->pv_pmap,
1281 pv->pv_va, PAGE_SIZE, TRUE,
1282 (pv->pv_flags & PVF_WRITE) == 0);
1283 pmap_tlb_flushD_SE(pv->pv_pmap,
1289 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1293 pmap_fix_cache(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1296 int writable = 0, kwritable = 0, uwritable = 0;
1297 int entries = 0, kentries = 0, uentries = 0;
1298 struct pv_entry *pv;
1300 rw_assert(&pvh_global_lock, RA_WLOCKED);
1302 /* the cache gets written back/invalidated on context switch.
1303 * therefore, if a user page shares an entry in the same page or
1304 * with the kernel map and at least one is writable, then the
1305 * cache entry must be set write-through.
1308 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1309 /* generate a count of the pv_entry uses */
1310 if (pv->pv_flags & PVF_WRITE) {
1311 if (pv->pv_pmap == pmap_kernel())
1313 else if (pv->pv_pmap == pm)
1317 if (pv->pv_pmap == pmap_kernel())
1320 if (pv->pv_pmap == pm)
1326 * check if the user duplicate mapping has
1329 if ((pm != pmap_kernel()) && (((uentries > 1) && uwritable) ||
1333 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1334 /* check for user uncachable conditions - order is important */
1335 if (pm != pmap_kernel() &&
1336 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel())) {
1338 if ((uentries > 1 && uwritable) || uwritable > 1) {
1340 /* user duplicate mapping */
1341 if (pv->pv_pmap != pmap_kernel())
1342 pv->pv_flags |= PVF_MWC;
1344 if (!(pv->pv_flags & PVF_NC)) {
1345 pv->pv_flags |= PVF_NC;
1346 pmap_set_cache_entry(pv, pm, va, -1);
1349 } else /* no longer a duplicate user */
1350 pv->pv_flags &= ~PVF_MWC;
1354 * check for kernel uncachable conditions
1355 * kernel writable or kernel readable with writable user entry
1357 if ((kwritable && (entries || kentries > 1)) ||
1359 ((kwritable != writable) && kentries &&
1360 (pv->pv_pmap == pmap_kernel() ||
1361 (pv->pv_flags & PVF_WRITE) ||
1362 (pv->pv_flags & PVF_MWC)))) {
1364 if (!(pv->pv_flags & PVF_NC)) {
1365 pv->pv_flags |= PVF_NC;
1366 pmap_set_cache_entry(pv, pm, va, -1);
1371 /* kernel and user are cachable */
1372 if ((pm == pmap_kernel()) && !(pv->pv_flags & PVF_MWC) &&
1373 (pv->pv_flags & PVF_NC)) {
1375 pv->pv_flags &= ~PVF_NC;
1376 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1377 pmap_set_cache_entry(pv, pm, va, 1);
1380 /* user is no longer sharable and writable */
1381 if (pm != pmap_kernel() &&
1382 (pv->pv_pmap == pm || pv->pv_pmap == pmap_kernel()) &&
1383 !pmwc && (pv->pv_flags & PVF_NC)) {
1385 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1386 if (pg->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
1387 pmap_set_cache_entry(pv, pm, va, 1);
1391 if ((kwritable == 0) && (writable == 0)) {
1392 pg->md.pvh_attrs &= ~PVF_MOD;
1393 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1399 * Modify pte bits for all ptes corresponding to the given physical address.
1400 * We use `maskbits' rather than `clearbits' because we're always passing
1401 * constants and the latter would require an extra inversion at run-time.
1404 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1406 struct l2_bucket *l2b;
1407 struct pv_entry *pv;
1408 pt_entry_t *ptep, npte, opte;
1414 rw_wlock(&pvh_global_lock);
1416 if (maskbits & PVF_WRITE)
1417 maskbits |= PVF_MOD;
1419 * Clear saved attributes (modify, reference)
1421 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1423 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1424 rw_wunlock(&pvh_global_lock);
1429 * Loop over all current mappings setting/clearing as appropos
1431 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1434 oflags = pv->pv_flags;
1436 if (!(oflags & maskbits)) {
1437 if ((maskbits & PVF_WRITE) && (pv->pv_flags & PVF_NC)) {
1438 if (pg->md.pv_memattr !=
1439 VM_MEMATTR_UNCACHEABLE) {
1441 l2b = pmap_get_l2_bucket(pm, va);
1442 ptep = &l2b->l2b_kva[l2pte_index(va)];
1443 *ptep |= pte_l2_s_cache_mode;
1447 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1451 pv->pv_flags &= ~maskbits;
1455 l2b = pmap_get_l2_bucket(pm, va);
1457 ptep = &l2b->l2b_kva[l2pte_index(va)];
1458 npte = opte = *ptep;
1460 if (maskbits & (PVF_WRITE|PVF_MOD)) {
1461 if ((pv->pv_flags & PVF_NC)) {
1463 * Entry is not cacheable:
1465 * Don't turn caching on again if this is a
1466 * modified emulation. This would be
1467 * inconsitent with the settings created by
1468 * pmap_fix_cache(). Otherwise, it's safe
1469 * to re-enable cacheing.
1471 * There's no need to call pmap_fix_cache()
1472 * here: all pages are losing their write
1475 if (maskbits & PVF_WRITE) {
1476 if (pg->md.pv_memattr !=
1477 VM_MEMATTR_UNCACHEABLE)
1478 npte |= pte_l2_s_cache_mode;
1479 pv->pv_flags &= ~(PVF_NC | PVF_MWC);
1482 if (opte & L2_S_PROT_W) {
1485 * Entry is writable/cacheable: check if pmap
1486 * is current if it is flush it, otherwise it
1487 * won't be in the cache
1489 if (PV_BEEN_EXECD(oflags))
1490 pmap_idcache_wbinv_range(pm, pv->pv_va,
1493 if (PV_BEEN_REFD(oflags))
1494 pmap_dcache_wb_range(pm, pv->pv_va,
1496 (maskbits & PVF_REF) ? TRUE : FALSE,
1500 /* make the pte read only */
1501 npte &= ~L2_S_PROT_W;
1504 if (maskbits & PVF_REF) {
1505 if ((pv->pv_flags & PVF_NC) == 0 &&
1506 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1508 * Check npte here; we may have already
1509 * done the wbinv above, and the validity
1510 * of the PTE is the same for opte and
1513 if (npte & L2_S_PROT_W) {
1514 if (PV_BEEN_EXECD(oflags))
1515 pmap_idcache_wbinv_range(pm,
1516 pv->pv_va, PAGE_SIZE);
1518 if (PV_BEEN_REFD(oflags))
1519 pmap_dcache_wb_range(pm,
1520 pv->pv_va, PAGE_SIZE,
1523 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1524 /* XXXJRT need idcache_inv_range */
1525 if (PV_BEEN_EXECD(oflags))
1526 pmap_idcache_wbinv_range(pm,
1527 pv->pv_va, PAGE_SIZE);
1529 if (PV_BEEN_REFD(oflags))
1530 pmap_dcache_wb_range(pm,
1531 pv->pv_va, PAGE_SIZE,
1537 * Make the PTE invalid so that we will take a
1538 * page fault the next time the mapping is
1541 npte &= ~L2_TYPE_MASK;
1542 npte |= L2_TYPE_INV;
1549 /* Flush the TLB entry if a current pmap. */
1550 if (PV_BEEN_EXECD(oflags))
1551 pmap_tlb_flushID_SE(pm, pv->pv_va);
1553 if (PV_BEEN_REFD(oflags))
1554 pmap_tlb_flushD_SE(pm, pv->pv_va);
1561 if (maskbits & PVF_WRITE)
1562 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1563 rw_wunlock(&pvh_global_lock);
1568 * main pv_entry manipulation functions:
1569 * pmap_enter_pv: enter a mapping onto a vm_page list
1570 * pmap_remove_pv: remove a mappiing from a vm_page list
1572 * NOTE: pmap_enter_pv expects to lock the pvh itself
1573 * pmap_remove_pv expects the caller to lock the pvh before calling
1577 * pmap_enter_pv: enter a mapping onto a vm_page's PV list
1579 * => caller should hold the proper lock on pvh_global_lock
1580 * => caller should have pmap locked
1581 * => we will (someday) gain the lock on the vm_page's PV list
1582 * => caller should adjust ptp's wire_count before calling
1583 * => caller should not adjust pmap's wire_count
1586 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1587 vm_offset_t va, u_int flags)
1590 rw_assert(&pvh_global_lock, RA_WLOCKED);
1591 PMAP_ASSERT_LOCKED(pm);
1592 if (pg->md.pv_kva != 0) {
1593 pve->pv_pmap = kernel_pmap;
1594 pve->pv_va = pg->md.pv_kva;
1595 pve->pv_flags = PVF_WRITE | PVF_UNMAN;
1596 if (pm != kernel_pmap)
1597 PMAP_LOCK(kernel_pmap);
1598 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1599 TAILQ_INSERT_HEAD(&kernel_pmap->pm_pvlist, pve, pv_plist);
1600 if (pm != kernel_pmap)
1601 PMAP_UNLOCK(kernel_pmap);
1603 if ((pve = pmap_get_pv_entry()) == NULL)
1604 panic("pmap_kenter_pv: no pv entries");
1608 pve->pv_flags = flags;
1609 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1610 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1611 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1612 if (pve->pv_flags & PVF_WIRED)
1613 ++pm->pm_stats.wired_count;
1614 vm_page_aflag_set(pg, PGA_REFERENCED);
1619 * pmap_find_pv: Find a pv entry
1621 * => caller should hold lock on vm_page
1623 static PMAP_INLINE struct pv_entry *
1624 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1626 struct pv_entry *pv;
1628 rw_assert(&pvh_global_lock, RA_WLOCKED);
1629 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1630 if (pm == pv->pv_pmap && va == pv->pv_va)
1636 * vector_page_setprot:
1638 * Manipulate the protection of the vector page.
1641 vector_page_setprot(int prot)
1643 struct l2_bucket *l2b;
1646 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1648 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1650 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1652 cpu_tlb_flushD_SE(vector_page);
1657 * pmap_remove_pv: try to remove a mapping from a pv_list
1659 * => caller should hold proper lock on pmap_main_lock
1660 * => pmap should be locked
1661 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1662 * => caller should adjust ptp's wire_count and free PTP if needed
1663 * => caller should NOT adjust pmap's wire_count
1664 * => we return the removed pve
1668 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1671 struct pv_entry *pv;
1672 rw_assert(&pvh_global_lock, RA_WLOCKED);
1673 PMAP_ASSERT_LOCKED(pm);
1674 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1675 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1676 if (pve->pv_flags & PVF_WIRED)
1677 --pm->pm_stats.wired_count;
1678 if (pg->md.pvh_attrs & PVF_MOD)
1680 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1681 pg->md.pvh_attrs &= ~PVF_REF;
1683 vm_page_aflag_set(pg, PGA_REFERENCED);
1684 if ((pve->pv_flags & PVF_NC) && ((pm == pmap_kernel()) ||
1685 (pve->pv_flags & PVF_WRITE) || !(pve->pv_flags & PVF_MWC)))
1686 pmap_fix_cache(pg, pm, 0);
1687 else if (pve->pv_flags & PVF_WRITE) {
1688 TAILQ_FOREACH(pve, &pg->md.pv_list, pv_list)
1689 if (pve->pv_flags & PVF_WRITE)
1692 pg->md.pvh_attrs &= ~PVF_MOD;
1693 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1696 pv = TAILQ_FIRST(&pg->md.pv_list);
1697 if (pv != NULL && (pv->pv_flags & PVF_UNMAN) &&
1698 TAILQ_NEXT(pv, pv_list) == NULL) {
1700 pg->md.pv_kva = pv->pv_va;
1701 /* a recursive pmap_nuke_pv */
1702 TAILQ_REMOVE(&pg->md.pv_list, pv, pv_list);
1703 TAILQ_REMOVE(&pm->pm_pvlist, pv, pv_plist);
1704 if (pv->pv_flags & PVF_WIRED)
1705 --pm->pm_stats.wired_count;
1706 pg->md.pvh_attrs &= ~PVF_REF;
1707 pg->md.pvh_attrs &= ~PVF_MOD;
1708 vm_page_aflag_clear(pg, PGA_WRITEABLE);
1709 pmap_free_pv_entry(pv);
1713 static struct pv_entry *
1714 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1716 struct pv_entry *pve;
1718 rw_assert(&pvh_global_lock, RA_WLOCKED);
1719 pve = TAILQ_FIRST(&pg->md.pv_list);
1722 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1723 pmap_nuke_pv(pg, pm, pve);
1726 pve = TAILQ_NEXT(pve, pv_list);
1729 if (pve == NULL && pg->md.pv_kva == va)
1732 return(pve); /* return removed pve */
1736 * pmap_modify_pv: Update pv flags
1738 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1739 * => caller should NOT adjust pmap's wire_count
1740 * => we return the old flags
1742 * Modify a physical-virtual mapping in the pv table
1745 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1746 u_int clr_mask, u_int set_mask)
1748 struct pv_entry *npv;
1749 u_int flags, oflags;
1751 PMAP_ASSERT_LOCKED(pm);
1752 rw_assert(&pvh_global_lock, RA_WLOCKED);
1753 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1757 * There is at least one VA mapping this page.
1760 if (clr_mask & (PVF_REF | PVF_MOD))
1761 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1763 oflags = npv->pv_flags;
1764 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1766 if ((flags ^ oflags) & PVF_WIRED) {
1767 if (flags & PVF_WIRED)
1768 ++pm->pm_stats.wired_count;
1770 --pm->pm_stats.wired_count;
1773 if ((flags ^ oflags) & PVF_WRITE)
1774 pmap_fix_cache(pg, pm, 0);
1779 /* Function to set the debug level of the pmap code */
1782 pmap_debug(int level)
1784 pmap_debug_level = level;
1785 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1787 #endif /* PMAP_DEBUG */
1790 pmap_pinit0(struct pmap *pmap)
1792 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1794 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1795 bzero(&pmap->pm_mtx, sizeof(pmap->pm_mtx));
1796 PMAP_LOCK_INIT(pmap);
1800 * Initialize a vm_page's machine-dependent fields.
1803 pmap_page_init(vm_page_t m)
1806 TAILQ_INIT(&m->md.pv_list);
1807 m->md.pv_memattr = VM_MEMATTR_DEFAULT;
1811 * Initialize the pmap module.
1812 * Called by vm_init, to initialize any structures that the pmap
1813 * system needs to map virtual memory.
1818 int shpgperproc = PMAP_SHPGPERPROC;
1820 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
1821 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1822 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable), NULL,
1823 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1826 * Initialize the PV entry allocator.
1828 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1829 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1830 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1831 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1832 uma_zone_reserve_kva(pvzone, pv_entry_max);
1833 pv_entry_high_water = 9 * (pv_entry_max / 10);
1836 * Now it is safe to enable pv_table recording.
1838 PDEBUG(1, printf("pmap_init: done!\n"));
1842 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
1844 struct l2_dtable *l2;
1845 struct l2_bucket *l2b;
1846 pd_entry_t *pl1pd, l1pd;
1847 pt_entry_t *ptep, pte;
1853 rw_wlock(&pvh_global_lock);
1857 * If there is no l2_dtable for this address, then the process
1858 * has no business accessing it.
1860 * Note: This will catch userland processes trying to access
1863 l2 = pm->pm_l2[L2_IDX(l1idx)];
1868 * Likewise if there is no L2 descriptor table
1870 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
1871 if (l2b->l2b_kva == NULL)
1875 * Check the PTE itself.
1877 ptep = &l2b->l2b_kva[l2pte_index(va)];
1883 * Catch a userland access to the vector page mapped at 0x0
1885 if (user && (pte & L2_S_PROT_U) == 0)
1887 if (va == vector_page)
1892 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
1894 * This looks like a good candidate for "page modified"
1897 struct pv_entry *pv;
1900 /* Extract the physical address of the page */
1901 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
1904 /* Get the current flags for this page. */
1906 pv = pmap_find_pv(pg, pm, va);
1912 * Do the flags say this page is writable? If not then it
1913 * is a genuine write fault. If yes then the write fault is
1914 * our fault as we did not reflect the write access in the
1915 * PTE. Now we know a write has occurred we can correct this
1916 * and also set the modified bit
1918 if ((pv->pv_flags & PVF_WRITE) == 0) {
1922 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
1924 pv->pv_flags |= PVF_REF | PVF_MOD;
1927 * Re-enable write permissions for the page. No need to call
1928 * pmap_fix_cache(), since this is just a
1929 * modified-emulation fault, and the PVF_WRITE bit isn't
1930 * changing. We've already set the cacheable bits based on
1931 * the assumption that we can write to this page.
1933 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
1937 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
1939 * This looks like a good candidate for "page referenced"
1942 struct pv_entry *pv;
1945 /* Extract the physical address of the page */
1946 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL)
1948 /* Get the current flags for this page. */
1950 pv = pmap_find_pv(pg, pm, va);
1954 pg->md.pvh_attrs |= PVF_REF;
1955 pv->pv_flags |= PVF_REF;
1958 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
1964 * We know there is a valid mapping here, so simply
1965 * fix up the L1 if necessary.
1967 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1968 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
1969 if (*pl1pd != l1pd) {
1977 * There are bugs in the rev K SA110. This is a check for one
1980 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
1981 curcpu()->ci_arm_cpurev < 3) {
1982 /* Always current pmap */
1983 if (l2pte_valid(pte)) {
1984 extern int kernel_debug;
1985 if (kernel_debug & 1) {
1986 struct proc *p = curlwp->l_proc;
1987 printf("prefetch_abort: page is already "
1988 "mapped - pte=%p *pte=%08x\n", ptep, pte);
1989 printf("prefetch_abort: pc=%08lx proc=%p "
1990 "process=%s\n", va, p, p->p_comm);
1991 printf("prefetch_abort: far=%08x fs=%x\n",
1992 cpu_faultaddress(), cpu_faultstatus());
1995 if (kernel_debug & 2)
2001 #endif /* CPU_SA110 */
2005 * If 'rv == 0' at this point, it generally indicates that there is a
2006 * stale TLB entry for the faulting address. This happens when two or
2007 * more processes are sharing an L1. Since we don't flush the TLB on
2008 * a context switch between such processes, we can take domain faults
2009 * for mappings which exist at the same VA in both processes. EVEN IF
2010 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2013 * This is extremely likely to happen if pmap_enter() updated the L1
2014 * entry for a recently entered mapping. In this case, the TLB is
2015 * flushed for the new mapping, but there may still be TLB entries for
2016 * other mappings belonging to other processes in the 1MB range
2017 * covered by the L1 entry.
2019 * Since 'rv == 0', we know that the L1 already contains the correct
2020 * value, so the fault must be due to a stale TLB entry.
2022 * Since we always need to flush the TLB anyway in the case where we
2023 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2024 * stale TLB entries dynamically.
2026 * However, the above condition can ONLY happen if the current L1 is
2027 * being shared. If it happens when the L1 is unshared, it indicates
2028 * that other parts of the pmap are not doing their job WRT managing
2031 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2032 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2033 pm, (u_long)va, ftype);
2034 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2035 l2, l2b, ptep, pl1pd);
2036 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2037 pte, l1pd, last_fault_code);
2044 cpu_tlb_flushID_SE(va);
2050 rw_wunlock(&pvh_global_lock);
2058 struct l2_bucket *l2b;
2059 struct l1_ttable *l1;
2061 pt_entry_t *ptep, pte;
2062 vm_offset_t va, eva;
2065 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2067 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2069 for (loop = 0; loop < needed; loop++, l1++) {
2070 /* Allocate a L1 page table */
2071 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2072 0xffffffff, L1_TABLE_SIZE, 0);
2075 panic("Cannot allocate L1 KVM");
2077 eva = va + L1_TABLE_SIZE;
2078 pl1pt = (pd_entry_t *)va;
2081 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2082 ptep = &l2b->l2b_kva[l2pte_index(va)];
2084 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2087 cpu_tlb_flushD_SE(va);
2091 pmap_init_l1(l1, pl1pt);
2096 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2102 * This is used to stuff certain critical values into the PCB where they
2103 * can be accessed quickly from cpu_switch() et al.
2106 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2108 struct l2_bucket *l2b;
2110 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2111 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2112 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2114 if (vector_page < KERNBASE) {
2115 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2116 l2b = pmap_get_l2_bucket(pm, vector_page);
2117 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2118 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2120 pcb->pcb_pl1vec = NULL;
2124 pmap_activate(struct thread *td)
2129 pm = vmspace_pmap(td->td_proc->p_vmspace);
2133 pmap_set_pcb_pagedir(pm, pcb);
2135 if (td == curthread) {
2136 u_int cur_dacr, cur_ttb;
2138 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2139 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2141 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2143 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2144 cur_dacr == pcb->pcb_dacr) {
2146 * No need to switch address spaces.
2154 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2155 * to 'vector_page' in the incoming L1 table before switching
2156 * to it otherwise subsequent interrupts/exceptions (including
2157 * domain faults!) will jump into hyperspace.
2159 if (pcb->pcb_pl1vec) {
2161 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2163 * Don't need to PTE_SYNC() at this point since
2164 * cpu_setttb() is about to flush both the cache
2169 cpu_domains(pcb->pcb_dacr);
2170 cpu_setttb(pcb->pcb_pagedir);
2176 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2178 pd_entry_t *pdep, pde;
2179 pt_entry_t *ptep, pte;
2184 * Make sure the descriptor itself has the correct cache mode
2186 pdep = &kl1[L1_IDX(va)];
2189 if (l1pte_section_p(pde)) {
2190 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2191 *pdep = (pde & ~L1_S_CACHE_MASK) |
2192 pte_l1_s_cache_mode_pt;
2194 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2196 cpu_l2cache_wbinv_range((vm_offset_t)pdep,
2201 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2202 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2204 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2206 ptep = &ptep[l2pte_index(va)];
2208 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2209 *ptep = (pte & ~L2_S_CACHE_MASK) |
2210 pte_l2_s_cache_mode_pt;
2212 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2214 cpu_l2cache_wbinv_range((vm_offset_t)ptep,
2224 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2227 vm_offset_t va = *availp;
2228 struct l2_bucket *l2b;
2231 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2233 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2235 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2239 *availp = va + (PAGE_SIZE * pages);
2243 * Bootstrap the system enough to run with virtual memory.
2245 * On the arm this is called after mapping has already been enabled
2246 * and just syncs the pmap module with what has already been done.
2247 * [We can't call it easily with mapping off since the kernel is not
2248 * mapped with PA == VA, hence we would have to relocate every address
2249 * from the linked base (virtual) address "KERNBASE" to the actual
2250 * (physical) address starting relative to 0]
2252 #define PMAP_STATIC_L2_SIZE 16
2254 pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt)
2256 static struct l1_ttable static_l1;
2257 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2258 struct l1_ttable *l1 = &static_l1;
2259 struct l2_dtable *l2;
2260 struct l2_bucket *l2b;
2262 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2267 int l1idx, l2idx, l2next = 0;
2269 PDEBUG(1, printf("firstaddr = %08x, lastaddr = %08x\n",
2270 firstaddr, vm_max_kernel_address));
2272 virtual_avail = firstaddr;
2273 kernel_pmap->pm_l1 = l1;
2274 kernel_l1pa = l1pt->pv_pa;
2277 * Scan the L1 translation table created by initarm() and create
2278 * the required metadata for all valid mappings found in it.
2280 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2281 pde = kernel_l1pt[l1idx];
2284 * We're only interested in Coarse mappings.
2285 * pmap_extract() can deal with section mappings without
2286 * recourse to checking L2 metadata.
2288 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2292 * Lookup the KVA of this L2 descriptor table
2294 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2295 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2298 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2299 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2303 * Fetch the associated L2 metadata structure.
2304 * Allocate a new one if necessary.
2306 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2307 if (l2next == PMAP_STATIC_L2_SIZE)
2308 panic("pmap_bootstrap: out of static L2s");
2309 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2310 &static_l2[l2next++];
2314 * One more L1 slot tracked...
2319 * Fill in the details of the L2 descriptor in the
2320 * appropriate bucket.
2322 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2323 l2b->l2b_kva = ptep;
2325 l2b->l2b_l1idx = l1idx;
2328 * Establish an initial occupancy count for this descriptor
2331 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2333 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2334 l2b->l2b_occupancy++;
2339 * Make sure the descriptor itself has the correct cache mode.
2340 * If not, fix it, but whine about the problem. Port-meisters
2341 * should consider this a clue to fix up their initarm()
2344 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2345 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2346 "L2 pte @ %p\n", ptep);
2352 * Ensure the primary (kernel) L1 has the correct cache mode for
2353 * a page table. Bitch if it is not correctly set.
2355 for (va = (vm_offset_t)kernel_l1pt;
2356 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2357 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2358 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2359 "primary L1 @ 0x%x\n", va);
2362 cpu_dcache_wbinv_all();
2363 cpu_l2cache_wbinv_all();
2367 PMAP_LOCK_INIT(kernel_pmap);
2368 CPU_FILL(&kernel_pmap->pm_active);
2369 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2370 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2373 * Initialize the global pv list lock.
2375 rw_init_flags(&pvh_global_lock, "pmap pv global", RW_RECURSE);
2378 * Reserve some special page table entries/VA space for temporary
2381 #define SYSMAP(c, p, v, n) \
2382 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2384 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2385 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2386 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2387 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2388 size = ((vm_max_kernel_address - pmap_curmaxkvaddr) + L1_S_OFFSET) /
2390 pmap_alloc_specials(&virtual_avail,
2391 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2392 &pmap_kernel_l2ptp_kva, NULL);
2394 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2395 pmap_alloc_specials(&virtual_avail,
2396 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2397 &pmap_kernel_l2dtable_kva, NULL);
2399 pmap_alloc_specials(&virtual_avail,
2400 1, (vm_offset_t*)&_tmppt, NULL);
2401 pmap_alloc_specials(&virtual_avail,
2402 MAXDUMPPGS, (vm_offset_t *)&crashdumpmap, NULL);
2403 SLIST_INIT(&l1_list);
2404 TAILQ_INIT(&l1_lru_list);
2405 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2406 pmap_init_l1(l1, kernel_l1pt);
2407 cpu_dcache_wbinv_all();
2408 cpu_l2cache_wbinv_all();
2410 virtual_avail = round_page(virtual_avail);
2411 virtual_end = vm_max_kernel_address;
2412 kernel_vm_end = pmap_curmaxkvaddr;
2413 mtx_init(&cmtx, "TMP mappings mtx", NULL, MTX_DEF);
2415 pmap_set_pcb_pagedir(kernel_pmap, thread0.td_pcb);
2418 /***************************************************
2419 * Pmap allocation/deallocation routines.
2420 ***************************************************/
2423 * Release any resources held by the given physical map.
2424 * Called when a pmap initialized by pmap_pinit is being released.
2425 * Should only be called if the map contains no valid mappings.
2428 pmap_release(pmap_t pmap)
2432 pmap_idcache_wbinv_all(pmap);
2433 cpu_l2cache_wbinv_all();
2434 pmap_tlb_flushID(pmap);
2436 if (vector_page < KERNBASE) {
2437 struct pcb *curpcb = PCPU_GET(curpcb);
2438 pcb = thread0.td_pcb;
2439 if (pmap_is_current(pmap)) {
2441 * Frob the L1 entry corresponding to the vector
2442 * page so that it contains the kernel pmap's domain
2443 * number. This will ensure pmap_remove() does not
2444 * pull the current vector page out from under us.
2447 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2448 cpu_domains(pcb->pcb_dacr);
2449 cpu_setttb(pcb->pcb_pagedir);
2452 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2454 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2455 * since this process has no remaining mappings of its own.
2457 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2458 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2459 curpcb->pcb_dacr = pcb->pcb_dacr;
2460 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2465 dprintf("pmap_release()\n");
2471 * Helper function for pmap_grow_l2_bucket()
2474 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2476 struct l2_bucket *l2b;
2481 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2484 pa = VM_PAGE_TO_PHYS(pg);
2489 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2491 ptep = &l2b->l2b_kva[l2pte_index(va)];
2492 *ptep = L2_S_PROTO | pa | cache_mode |
2493 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2499 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2500 * used by pmap_growkernel().
2502 static __inline struct l2_bucket *
2503 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2505 struct l2_dtable *l2;
2506 struct l2_bucket *l2b;
2507 struct l1_ttable *l1;
2514 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2516 * No mapping at this address, as there is
2517 * no entry in the L1 table.
2518 * Need to allocate a new l2_dtable.
2520 nva = pmap_kernel_l2dtable_kva;
2521 if ((nva & PAGE_MASK) == 0) {
2523 * Need to allocate a backing page
2525 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2529 l2 = (struct l2_dtable *)nva;
2530 nva += sizeof(struct l2_dtable);
2532 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2535 * The new l2_dtable straddles a page boundary.
2536 * Map in another page to cover it.
2538 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2542 pmap_kernel_l2dtable_kva = nva;
2545 * Link it into the parent pmap
2547 pm->pm_l2[L2_IDX(l1idx)] = l2;
2548 memset(l2, 0, sizeof(*l2));
2551 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2554 * Fetch pointer to the L2 page table associated with the address.
2556 if (l2b->l2b_kva == NULL) {
2560 * No L2 page table has been allocated. Chances are, this
2561 * is because we just allocated the l2_dtable, above.
2563 nva = pmap_kernel_l2ptp_kva;
2564 ptep = (pt_entry_t *)nva;
2565 if ((nva & PAGE_MASK) == 0) {
2567 * Need to allocate a backing page
2569 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2570 &pmap_kernel_l2ptp_phys))
2572 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2574 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2576 l2b->l2b_kva = ptep;
2577 l2b->l2b_l1idx = l1idx;
2578 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2580 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2581 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2584 /* Distribute new L1 entry to all other L1s */
2585 SLIST_FOREACH(l1, &l1_list, l1_link) {
2586 pl1pd = &l1->l1_kva[L1_IDX(va)];
2587 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2597 * grow the number of kernel page table entries, if needed
2600 pmap_growkernel(vm_offset_t addr)
2602 pmap_t kpm = pmap_kernel();
2604 if (addr <= pmap_curmaxkvaddr)
2605 return; /* we are OK */
2608 * whoops! we need to add kernel PTPs
2611 /* Map 1MB at a time */
2612 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2613 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2616 * flush out the cache, expensive but growkernel will happen so
2619 cpu_dcache_wbinv_all();
2620 cpu_l2cache_wbinv_all();
2623 kernel_vm_end = pmap_curmaxkvaddr;
2628 * Remove all pages from specified address space
2629 * this aids process exit speeds. Also, this code
2630 * is special cased for current process only, but
2631 * can have the more generic (and slightly slower)
2632 * mode enabled. This is much faster than pmap_remove
2633 * in the case of running down an entire address space.
2636 pmap_remove_pages(pmap_t pmap)
2638 struct pv_entry *pv, *npv;
2639 struct l2_bucket *l2b = NULL;
2643 rw_wlock(&pvh_global_lock);
2645 cpu_idcache_wbinv_all();
2646 cpu_l2cache_wbinv_all();
2647 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2648 if (pv->pv_flags & PVF_WIRED || pv->pv_flags & PVF_UNMAN) {
2649 /* Cannot remove wired or unmanaged pages now. */
2650 npv = TAILQ_NEXT(pv, pv_plist);
2653 pmap->pm_stats.resident_count--;
2654 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2655 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2656 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2657 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2658 KASSERT((vm_offset_t)m >= KERNBASE, ("Trying to access non-existent page va %x pte %x", pv->pv_va, *pt));
2661 npv = TAILQ_NEXT(pv, pv_plist);
2662 pmap_nuke_pv(m, pmap, pv);
2663 if (TAILQ_EMPTY(&m->md.pv_list))
2664 vm_page_aflag_clear(m, PGA_WRITEABLE);
2665 pmap_free_pv_entry(pv);
2666 pmap_free_l2_bucket(pmap, l2b, 1);
2668 rw_wunlock(&pvh_global_lock);
2675 /***************************************************
2676 * Low level mapping routines.....
2677 ***************************************************/
2679 #ifdef ARM_HAVE_SUPERSECTIONS
2680 /* Map a super section into the KVA. */
2683 pmap_kenter_supersection(vm_offset_t va, uint64_t pa, int flags)
2685 pd_entry_t pd = L1_S_PROTO | L1_S_SUPERSEC | (pa & L1_SUP_FRAME) |
2686 (((pa >> 32) & 0xf) << 20) | L1_S_PROT(PTE_KERNEL,
2687 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2688 struct l1_ttable *l1;
2689 vm_offset_t va0, va_end;
2691 KASSERT(((va | pa) & L1_SUP_OFFSET) == 0,
2692 ("Not a valid super section mapping"));
2693 if (flags & SECTION_CACHE)
2694 pd |= pte_l1_s_cache_mode;
2695 else if (flags & SECTION_PT)
2696 pd |= pte_l1_s_cache_mode_pt;
2697 va0 = va & L1_SUP_FRAME;
2698 va_end = va + L1_SUP_SIZE;
2699 SLIST_FOREACH(l1, &l1_list, l1_link) {
2701 for (; va < va_end; va += L1_S_SIZE) {
2702 l1->l1_kva[L1_IDX(va)] = pd;
2703 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2709 /* Map a section into the KVA. */
2712 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2714 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2715 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2716 struct l1_ttable *l1;
2718 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2719 ("Not a valid section mapping"));
2720 if (flags & SECTION_CACHE)
2721 pd |= pte_l1_s_cache_mode;
2722 else if (flags & SECTION_PT)
2723 pd |= pte_l1_s_cache_mode_pt;
2724 SLIST_FOREACH(l1, &l1_list, l1_link) {
2725 l1->l1_kva[L1_IDX(va)] = pd;
2726 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2731 * Make a temporary mapping for a physical address. This is only intended
2732 * to be used for panic dumps.
2735 pmap_kenter_temp(vm_paddr_t pa, int i)
2739 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
2740 pmap_kenter(va, pa);
2741 return ((void *)crashdumpmap);
2745 * add a wired page to the kva
2746 * note that in order for the mapping to take effect -- you
2747 * should do a invltlb after doing the pmap_kenter...
2749 static PMAP_INLINE void
2750 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2752 struct l2_bucket *l2b;
2755 struct pv_entry *pve;
2758 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2759 (uint32_t) va, (uint32_t) pa));
2762 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2764 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2765 KASSERT(l2b != NULL, ("No L2 Bucket"));
2766 pte = &l2b->l2b_kva[l2pte_index(va)];
2768 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2769 (uint32_t) pte, opte, *pte));
2770 if (l2pte_valid(opte)) {
2774 l2b->l2b_occupancy++;
2776 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2777 VM_PROT_READ | VM_PROT_WRITE);
2778 if (flags & KENTER_CACHE)
2779 *pte |= pte_l2_s_cache_mode;
2780 if (flags & KENTER_USER)
2781 *pte |= L2_S_PROT_U;
2785 * A kernel mapping may not be the page's only mapping, so create a PV
2786 * entry to ensure proper caching.
2788 * The existence test for the pvzone is used to delay the recording of
2789 * kernel mappings until the VM system is fully initialized.
2791 * This expects the physical memory to have a vm_page_array entry.
2793 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) != NULL) {
2794 rw_wlock(&pvh_global_lock);
2795 if (!TAILQ_EMPTY(&m->md.pv_list) || m->md.pv_kva != 0) {
2796 if ((pve = pmap_get_pv_entry()) == NULL)
2797 panic("pmap_kenter_internal: no pv entries");
2798 PMAP_LOCK(pmap_kernel());
2799 pmap_enter_pv(m, pve, pmap_kernel(), va,
2800 PVF_WRITE | PVF_UNMAN);
2801 pmap_fix_cache(m, pmap_kernel(), va);
2802 PMAP_UNLOCK(pmap_kernel());
2806 rw_wunlock(&pvh_global_lock);
2811 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2813 pmap_kenter_internal(va, pa, KENTER_CACHE);
2817 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2820 pmap_kenter_internal(va, pa, 0);
2824 pmap_kenter_device(vm_offset_t va, vm_paddr_t pa)
2828 * XXX - Need a way for kenter_internal to handle PTE_DEVICE mapping as
2829 * a potentially different thing than PTE_NOCACHE.
2831 pmap_kenter_internal(va, pa, 0);
2835 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2838 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2840 * Call pmap_fault_fixup now, to make sure we'll have no exception
2841 * at the first use of the new address, or bad things will happen,
2842 * as we use one of these addresses in the exception handlers.
2844 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2848 pmap_kextract(vm_offset_t va)
2851 return (pmap_extract_locked(kernel_pmap, va));
2855 * remove a page from the kernel pagetables
2858 pmap_kremove(vm_offset_t va)
2860 struct l2_bucket *l2b;
2861 pt_entry_t *pte, opte;
2862 struct pv_entry *pve;
2866 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2869 KASSERT(l2b != NULL, ("No L2 Bucket"));
2870 pte = &l2b->l2b_kva[l2pte_index(va)];
2872 if (l2pte_valid(opte)) {
2873 /* pa = vtophs(va) taken from pmap_extract() */
2874 switch (opte & L2_TYPE_MASK) {
2876 pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
2879 pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
2882 /* note: should never have to remove an allocation
2883 * before the pvzone is initialized.
2885 rw_wlock(&pvh_global_lock);
2886 PMAP_LOCK(pmap_kernel());
2887 if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
2888 (pve = pmap_remove_pv(m, pmap_kernel(), va)))
2889 pmap_free_pv_entry(pve);
2890 PMAP_UNLOCK(pmap_kernel());
2891 rw_wunlock(&pvh_global_lock);
2892 va = va & ~PAGE_MASK;
2893 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2894 cpu_l2cache_wbinv_range(va, PAGE_SIZE);
2895 cpu_tlb_flushD_SE(va);
2903 * Used to map a range of physical addresses into kernel
2904 * virtual address space.
2906 * The value passed in '*virt' is a suggested virtual address for
2907 * the mapping. Architectures which can support a direct-mapped
2908 * physical to virtual region can return the appropriate address
2909 * within that region, leaving '*virt' unchanged. Other
2910 * architectures should map the pages starting at '*virt' and
2911 * update '*virt' with the first usable address after the mapped
2915 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
2917 vm_offset_t sva = *virt;
2918 vm_offset_t va = sva;
2920 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
2921 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
2924 while (start < end) {
2925 pmap_kenter(va, start);
2934 pmap_wb_page(vm_page_t m)
2936 struct pv_entry *pv;
2938 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2939 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, FALSE,
2940 (pv->pv_flags & PVF_WRITE) == 0);
2944 pmap_inv_page(vm_page_t m)
2946 struct pv_entry *pv;
2948 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
2949 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, TRUE, TRUE);
2952 * Add a list of wired pages to the kva
2953 * this routine is only used for temporary
2954 * kernel mappings that do not need to have
2955 * page modification or references recorded.
2956 * Note that old mappings are simply written
2957 * over. The page *must* be wired.
2960 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
2964 for (i = 0; i < count; i++) {
2966 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
2974 * this routine jerks page mappings from the
2975 * kernel -- it is meant only for temporary mappings.
2978 pmap_qremove(vm_offset_t va, int count)
2983 for (i = 0; i < count; i++) {
2986 pmap_inv_page(PHYS_TO_VM_PAGE(pa));
2995 * pmap_object_init_pt preloads the ptes for a given object
2996 * into the specified pmap. This eliminates the blast of soft
2997 * faults on process startup and immediately after an mmap.
3000 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3001 vm_pindex_t pindex, vm_size_t size)
3004 VM_OBJECT_ASSERT_WLOCKED(object);
3005 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3006 ("pmap_object_init_pt: non-device object"));
3011 * pmap_is_prefaultable:
3013 * Return whether or not the specified virtual address is elgible
3017 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3022 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3024 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3031 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3032 * Returns TRUE if the mapping exists, else FALSE.
3034 * NOTE: This function is only used by a couple of arm-specific modules.
3035 * It is not safe to take any pmap locks here, since we could be right
3036 * in the middle of debugging the pmap anyway...
3038 * It is possible for this routine to return FALSE even though a valid
3039 * mapping does exist. This is because we don't lock, so the metadata
3040 * state may be inconsistent.
3042 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3043 * a "section" mapping.
3046 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3048 struct l2_dtable *l2;
3049 pd_entry_t *pl1pd, l1pd;
3053 if (pm->pm_l1 == NULL)
3057 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3060 if (l1pte_section_p(l1pd)) {
3065 if (pm->pm_l2 == NULL)
3068 l2 = pm->pm_l2[L2_IDX(l1idx)];
3071 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3075 *ptp = &ptep[l2pte_index(va)];
3080 * Routine: pmap_remove_all
3082 * Removes this physical page from
3083 * all physical maps in which it resides.
3084 * Reflects back modify bits to the pager.
3087 * Original versions of this routine were very
3088 * inefficient because they iteratively called
3089 * pmap_remove (slow...)
3092 pmap_remove_all(vm_page_t m)
3096 struct l2_bucket *l2b;
3097 boolean_t flush = FALSE;
3101 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3102 ("pmap_remove_all: page %p is not managed", m));
3103 if (TAILQ_EMPTY(&m->md.pv_list))
3105 rw_wlock(&pvh_global_lock);
3106 pmap_remove_write(m);
3107 curpm = vmspace_pmap(curproc->p_vmspace);
3108 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3109 if (flush == FALSE && (pv->pv_pmap == curpm ||
3110 pv->pv_pmap == pmap_kernel()))
3113 PMAP_LOCK(pv->pv_pmap);
3115 * Cached contents were written-back in pmap_remove_write(),
3116 * but we still have to invalidate the cache entry to make
3117 * sure stale data are not retrieved when another page will be
3118 * mapped under this virtual address.
3120 if (pmap_is_current(pv->pv_pmap)) {
3121 cpu_dcache_inv_range(pv->pv_va, PAGE_SIZE);
3122 if (pmap_has_valid_mapping(pv->pv_pmap, pv->pv_va))
3123 cpu_l2cache_inv_range(pv->pv_va, PAGE_SIZE);
3126 if (pv->pv_flags & PVF_UNMAN) {
3127 /* remove the pv entry, but do not remove the mapping
3128 * and remember this is a kernel mapped page
3130 m->md.pv_kva = pv->pv_va;
3132 /* remove the mapping and pv entry */
3133 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3134 KASSERT(l2b != NULL, ("No l2 bucket"));
3135 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3137 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3138 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3139 pv->pv_pmap->pm_stats.resident_count--;
3140 flags |= pv->pv_flags;
3142 pmap_nuke_pv(m, pv->pv_pmap, pv);
3143 PMAP_UNLOCK(pv->pv_pmap);
3144 pmap_free_pv_entry(pv);
3148 if (PV_BEEN_EXECD(flags))
3149 pmap_tlb_flushID(curpm);
3151 pmap_tlb_flushD(curpm);
3153 vm_page_aflag_clear(m, PGA_WRITEABLE);
3154 rw_wunlock(&pvh_global_lock);
3159 * Set the physical protection on the
3160 * specified range of this map as requested.
3163 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3165 struct l2_bucket *l2b;
3166 pt_entry_t *ptep, pte;
3167 vm_offset_t next_bucket;
3171 CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x",
3172 pm, sva, eva, prot);
3174 if ((prot & VM_PROT_READ) == 0) {
3175 pmap_remove(pm, sva, eva);
3179 if (prot & VM_PROT_WRITE) {
3181 * If this is a read->write transition, just ignore it and let
3182 * vm_fault() take care of it later.
3187 rw_wlock(&pvh_global_lock);
3191 * OK, at this point, we know we're doing write-protect operation.
3192 * If the pmap is active, write-back the range.
3194 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3196 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3200 next_bucket = L2_NEXT_BUCKET(sva);
3201 if (next_bucket > eva)
3204 l2b = pmap_get_l2_bucket(pm, sva);
3210 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3212 while (sva < next_bucket) {
3213 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3217 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3218 pte &= ~L2_S_PROT_W;
3222 if (!(pg->oflags & VPO_UNMANAGED)) {
3223 f = pmap_modify_pv(pg, pm, sva,
3234 if (PV_BEEN_EXECD(f))
3235 pmap_tlb_flushID_SE(pm, sva);
3237 if (PV_BEEN_REFD(f))
3238 pmap_tlb_flushD_SE(pm, sva);
3248 if (PV_BEEN_EXECD(flags))
3249 pmap_tlb_flushID(pm);
3251 if (PV_BEEN_REFD(flags))
3252 pmap_tlb_flushD(pm);
3254 rw_wunlock(&pvh_global_lock);
3261 * Insert the given physical page (p) at
3262 * the specified virtual address (v) in the
3263 * target physical map with the protection requested.
3265 * If specified, the page will be wired down, meaning
3266 * that the related pte can not be reclaimed.
3268 * NB: This is the only routine which MAY NOT lazy-evaluate
3269 * or lose information. That is, this routine must actually
3270 * insert this page into the given map NOW.
3274 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3275 vm_prot_t prot, boolean_t wired)
3278 rw_wlock(&pvh_global_lock);
3280 pmap_enter_locked(pmap, va, m, prot, wired, M_WAITOK);
3281 rw_wunlock(&pvh_global_lock);
3286 * The pvh global and pmap locks must be held.
3289 pmap_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3290 boolean_t wired, int flags)
3292 struct l2_bucket *l2b = NULL;
3293 struct vm_page *opg;
3294 struct pv_entry *pve = NULL;
3295 pt_entry_t *ptep, npte, opte;
3300 PMAP_ASSERT_LOCKED(pmap);
3301 rw_assert(&pvh_global_lock, RA_WLOCKED);
3302 if (va == vector_page) {
3303 pa = systempage.pv_pa;
3306 KASSERT((m->oflags & VPO_UNMANAGED) != 0 ||
3307 vm_page_xbusied(m) || (flags & M_NOWAIT) != 0,
3308 ("pmap_enter_locked: page %p is not busy", m));
3309 pa = VM_PAGE_TO_PHYS(m);
3312 if (prot & VM_PROT_WRITE)
3313 nflags |= PVF_WRITE;
3314 if (prot & VM_PROT_EXECUTE)
3317 nflags |= PVF_WIRED;
3318 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3319 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3321 if (pmap == pmap_kernel()) {
3322 l2b = pmap_get_l2_bucket(pmap, va);
3324 l2b = pmap_grow_l2_bucket(pmap, va);
3327 l2b = pmap_alloc_l2_bucket(pmap, va);
3329 if (flags & M_WAITOK) {
3331 rw_wunlock(&pvh_global_lock);
3333 rw_wlock(&pvh_global_lock);
3341 ptep = &l2b->l2b_kva[l2pte_index(va)];
3348 * There is already a mapping at this address.
3349 * If the physical address is different, lookup the
3352 if (l2pte_pa(opte) != pa)
3353 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3359 if ((prot & (VM_PROT_ALL)) ||
3360 (!m || m->md.pvh_attrs & PVF_REF)) {
3362 * - The access type indicates that we don't need
3363 * to do referenced emulation.
3365 * - The physical page has already been referenced
3366 * so no need to re-do referenced emulation here.
3372 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3373 (m->md.pvh_attrs & PVF_MOD))) {
3375 * This is a writable mapping, and the
3376 * page's mod state indicates it has
3377 * already been modified. Make it
3378 * writable from the outset.
3381 if (!(m->md.pvh_attrs & PVF_MOD))
3385 vm_page_aflag_set(m, PGA_REFERENCED);
3388 * Need to do page referenced emulation.
3390 npte |= L2_TYPE_INV;
3393 if (prot & VM_PROT_WRITE) {
3394 npte |= L2_S_PROT_W;
3396 (m->oflags & VPO_UNMANAGED) == 0)
3397 vm_page_aflag_set(m, PGA_WRITEABLE);
3399 if (m->md.pv_memattr != VM_MEMATTR_UNCACHEABLE)
3400 npte |= pte_l2_s_cache_mode;
3401 if (m && m == opg) {
3403 * We're changing the attrs of an existing mapping.
3405 oflags = pmap_modify_pv(m, pmap, va,
3406 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3407 PVF_MOD | PVF_REF, nflags);
3410 * We may need to flush the cache if we're
3413 if (pmap_is_current(pmap) &&
3414 (oflags & PVF_NC) == 0 &&
3415 (opte & L2_S_PROT_W) != 0 &&
3416 (prot & VM_PROT_WRITE) == 0 &&
3417 (opte & L2_TYPE_MASK) != L2_TYPE_INV) {
3418 cpu_dcache_wb_range(va, PAGE_SIZE);
3419 cpu_l2cache_wb_range(va, PAGE_SIZE);
3423 * New mapping, or changing the backing page
3424 * of an existing mapping.
3428 * Replacing an existing mapping with a new one.
3429 * It is part of our managed memory so we
3430 * must remove it from the PV list
3432 if ((pve = pmap_remove_pv(opg, pmap, va))) {
3434 /* note for patch: the oflags/invalidation was moved
3435 * because PG_FICTITIOUS pages could free the pve
3437 oflags = pve->pv_flags;
3439 * If the old mapping was valid (ref/mod
3440 * emulation creates 'invalid' mappings
3441 * initially) then make sure to frob
3444 if ((oflags & PVF_NC) == 0 && l2pte_valid(opte)) {
3445 if (PV_BEEN_EXECD(oflags)) {
3446 pmap_idcache_wbinv_range(pmap, va,
3449 if (PV_BEEN_REFD(oflags)) {
3450 pmap_dcache_wb_range(pmap, va,
3452 (oflags & PVF_WRITE) == 0);
3456 /* free/allocate a pv_entry for UNMANAGED pages if
3457 * this physical page is not/is already mapped.
3460 if (m && (m->oflags & VPO_UNMANAGED) &&
3462 TAILQ_EMPTY(&m->md.pv_list)) {
3463 pmap_free_pv_entry(pve);
3467 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3468 !TAILQ_EMPTY(&m->md.pv_list)))
3469 pve = pmap_get_pv_entry();
3471 (!(m->oflags & VPO_UNMANAGED) || m->md.pv_kva ||
3472 !TAILQ_EMPTY(&m->md.pv_list)))
3473 pve = pmap_get_pv_entry();
3476 if ((m->oflags & VPO_UNMANAGED)) {
3477 if (!TAILQ_EMPTY(&m->md.pv_list) ||
3479 KASSERT(pve != NULL, ("No pv"));
3480 nflags |= PVF_UNMAN;
3481 pmap_enter_pv(m, pve, pmap, va, nflags);
3485 KASSERT(va < kmi.clean_sva ||
3486 va >= kmi.clean_eva,
3487 ("pmap_enter: managed mapping within the clean submap"));
3488 KASSERT(pve != NULL, ("No pv"));
3489 pmap_enter_pv(m, pve, pmap, va, nflags);
3494 * Make sure userland mappings get the right permissions
3496 if (pmap != pmap_kernel() && va != vector_page) {
3497 npte |= L2_S_PROT_U;
3501 * Keep the stats up to date
3504 l2b->l2b_occupancy++;
3505 pmap->pm_stats.resident_count++;
3509 * If this is just a wiring change, the two PTEs will be
3510 * identical, so there's no need to update the page table.
3513 boolean_t is_cached = pmap_is_current(pmap);
3518 * We only need to frob the cache/tlb if this pmap
3522 if (L1_IDX(va) != L1_IDX(vector_page) &&
3523 l2pte_valid(npte)) {
3525 * This mapping is likely to be accessed as
3526 * soon as we return to userland. Fix up the
3527 * L1 entry to avoid taking another
3528 * page/domain fault.
3530 pd_entry_t *pl1pd, l1pd;
3532 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3533 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3535 if (*pl1pd != l1pd) {
3542 if (PV_BEEN_EXECD(oflags))
3543 pmap_tlb_flushID_SE(pmap, va);
3544 else if (PV_BEEN_REFD(oflags))
3545 pmap_tlb_flushD_SE(pmap, va);
3549 pmap_fix_cache(m, pmap, va);
3554 * Maps a sequence of resident pages belonging to the same object.
3555 * The sequence begins with the given page m_start. This page is
3556 * mapped at the given virtual address start. Each subsequent page is
3557 * mapped at a virtual address that is offset from start by the same
3558 * amount as the page is offset from m_start within the object. The
3559 * last page in the sequence is the page with the largest offset from
3560 * m_start that can be mapped at a virtual address less than the given
3561 * virtual address end. Not every virtual page between start and end
3562 * is mapped; only those for which a resident page exists with the
3563 * corresponding offset from m_start are mapped.
3566 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3567 vm_page_t m_start, vm_prot_t prot)
3570 vm_pindex_t diff, psize;
3572 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3574 psize = atop(end - start);
3576 rw_wlock(&pvh_global_lock);
3578 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3579 pmap_enter_locked(pmap, start + ptoa(diff), m, prot &
3580 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE, M_NOWAIT);
3581 m = TAILQ_NEXT(m, listq);
3583 rw_wunlock(&pvh_global_lock);
3588 * this code makes some *MAJOR* assumptions:
3589 * 1. Current pmap & pmap exists.
3592 * 4. No page table pages.
3593 * but is *MUCH* faster than pmap_enter...
3597 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3600 rw_wlock(&pvh_global_lock);
3602 pmap_enter_locked(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
3604 rw_wunlock(&pvh_global_lock);
3609 * Routine: pmap_change_wiring
3610 * Function: Change the wiring attribute for a map/virtual-address
3612 * In/out conditions:
3613 * The mapping must already exist in the pmap.
3616 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3618 struct l2_bucket *l2b;
3619 pt_entry_t *ptep, pte;
3622 rw_wlock(&pvh_global_lock);
3624 l2b = pmap_get_l2_bucket(pmap, va);
3625 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3626 ptep = &l2b->l2b_kva[l2pte_index(va)];
3628 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3630 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired ? PVF_WIRED : 0);
3631 rw_wunlock(&pvh_global_lock);
3637 * Copy the range specified by src_addr/len
3638 * from the source map to the range dst_addr/len
3639 * in the destination map.
3641 * This routine is only advisory and need not do anything.
3644 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3645 vm_size_t len, vm_offset_t src_addr)
3651 * Routine: pmap_extract
3653 * Extract the physical page address associated
3654 * with the given map/virtual_address pair.
3657 pmap_extract(pmap_t pmap, vm_offset_t va)
3662 pa = pmap_extract_locked(pmap, va);
3668 pmap_extract_locked(pmap_t pmap, vm_offset_t va)
3670 struct l2_dtable *l2;
3672 pt_entry_t *ptep, pte;
3676 if (pmap != kernel_pmap)
3677 PMAP_ASSERT_LOCKED(pmap);
3679 l1pd = pmap->pm_l1->l1_kva[l1idx];
3680 if (l1pte_section_p(l1pd)) {
3682 * These should only happen for the kernel pmap.
3684 KASSERT(pmap == kernel_pmap, ("unexpected section"));
3685 /* XXX: what to do about the bits > 32 ? */
3686 if (l1pd & L1_S_SUPERSEC)
3687 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3689 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3692 * Note that we can't rely on the validity of the L1
3693 * descriptor as an indication that a mapping exists.
3694 * We have to look it up in the L2 dtable.
3696 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3698 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL)
3700 pte = ptep[l2pte_index(va)];
3703 switch (pte & L2_TYPE_MASK) {
3705 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3708 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3716 * Atomically extract and hold the physical page with the given
3717 * pmap and virtual address pair if that mapping permits the given
3722 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3724 struct l2_dtable *l2;
3726 pt_entry_t *ptep, pte;
3727 vm_paddr_t pa, paddr;
3735 l1pd = pmap->pm_l1->l1_kva[l1idx];
3736 if (l1pte_section_p(l1pd)) {
3738 * These should only happen for pmap_kernel()
3740 KASSERT(pmap == pmap_kernel(), ("huh"));
3741 /* XXX: what to do about the bits > 32 ? */
3742 if (l1pd & L1_S_SUPERSEC)
3743 pa = (l1pd & L1_SUP_FRAME) | (va & L1_SUP_OFFSET);
3745 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3746 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3748 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3749 m = PHYS_TO_VM_PAGE(pa);
3755 * Note that we can't rely on the validity of the L1
3756 * descriptor as an indication that a mapping exists.
3757 * We have to look it up in the L2 dtable.
3759 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3762 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3767 ptep = &ptep[l2pte_index(va)];
3774 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3775 switch (pte & L2_TYPE_MASK) {
3777 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3781 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3784 if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
3786 m = PHYS_TO_VM_PAGE(pa);
3792 PA_UNLOCK_COND(paddr);
3797 * Initialize a preallocated and zeroed pmap structure,
3798 * such as one in a vmspace structure.
3802 pmap_pinit(pmap_t pmap)
3804 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3806 pmap_alloc_l1(pmap);
3807 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3809 CPU_ZERO(&pmap->pm_active);
3811 TAILQ_INIT(&pmap->pm_pvlist);
3812 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3813 pmap->pm_stats.resident_count = 1;
3814 if (vector_page < KERNBASE) {
3815 pmap_enter(pmap, vector_page,
3816 VM_PROT_READ, PHYS_TO_VM_PAGE(systempage.pv_pa),
3823 /***************************************************
3824 * page management routines.
3825 ***************************************************/
3829 pmap_free_pv_entry(pv_entry_t pv)
3832 uma_zfree(pvzone, pv);
3837 * get a new pv_entry, allocating a block from the system
3839 * the memory allocation is performed bypassing the malloc code
3840 * because of the possibility of allocations at interrupt time.
3843 pmap_get_pv_entry(void)
3845 pv_entry_t ret_value;
3848 if (pv_entry_count > pv_entry_high_water)
3849 pagedaemon_wakeup();
3850 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3855 * Remove the given range of addresses from the specified map.
3857 * It is assumed that the start and end are properly
3858 * rounded to the page size.
3860 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3862 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3864 struct l2_bucket *l2b;
3865 vm_offset_t next_bucket;
3868 u_int mappings, is_exec, is_refd;
3873 * we lock in the pmap => pv_head direction
3876 rw_wlock(&pvh_global_lock);
3881 * Do one L2 bucket's worth at a time.
3883 next_bucket = L2_NEXT_BUCKET(sva);
3884 if (next_bucket > eva)
3887 l2b = pmap_get_l2_bucket(pm, sva);
3893 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3896 while (sva < next_bucket) {
3905 * Nothing here, move along
3912 pm->pm_stats.resident_count--;
3918 * Update flags. In a number of circumstances,
3919 * we could cluster a lot of these and do a
3920 * number of sequential pages in one go.
3922 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3923 struct pv_entry *pve;
3925 pve = pmap_remove_pv(pg, pm, sva);
3927 is_exec = PV_BEEN_EXECD(pve->pv_flags);
3928 is_refd = PV_BEEN_REFD(pve->pv_flags);
3929 pmap_free_pv_entry(pve);
3933 if (l2pte_valid(pte) && pmap_is_current(pm)) {
3934 if (total < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3937 cpu_idcache_wbinv_range(sva,
3939 cpu_l2cache_wbinv_range(sva,
3941 cpu_tlb_flushID_SE(sva);
3942 } else if (is_refd) {
3943 cpu_dcache_wbinv_range(sva,
3945 cpu_l2cache_wbinv_range(sva,
3947 cpu_tlb_flushD_SE(sva);
3949 } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3950 /* flushall will also only get set for
3951 * for a current pmap
3953 cpu_idcache_wbinv_all();
3954 cpu_l2cache_wbinv_all();
3967 pmap_free_l2_bucket(pm, l2b, mappings);
3970 rw_wunlock(&pvh_global_lock);
3979 * Zero a given physical page by mapping it at a page hook point.
3980 * In doing the zero page op, the page we zero is mapped cachable, as with
3981 * StrongARM accesses to non-cached pages are non-burst making writing
3982 * _any_ bulk data very slow.
3984 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_CORE3)
3986 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
3989 if (_arm_bzero && size >= _min_bzero_size &&
3990 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
3995 * Hook in the page, zero it, invalidate the TLB as needed.
3997 * Note the temporary zero-page mapping must be a non-cached page in
3998 * order to work without corruption when write-allocate is enabled.
4000 *cdst_pte = L2_S_PROTO | phys | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE);
4002 cpu_tlb_flushD_SE(cdstp);
4004 if (off || size != PAGE_SIZE)
4005 bzero((void *)(cdstp + off), size);
4011 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4013 #if ARM_MMU_XSCALE == 1
4015 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4018 if (_arm_bzero && size >= _min_bzero_size &&
4019 _arm_bzero((void *)(phys + off), size, IS_PHYSICAL) == 0)
4024 * Hook in the page, zero it, and purge the cache for that
4025 * zeroed page. Invalidate the TLB as needed.
4027 *cdst_pte = L2_S_PROTO | phys |
4028 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4029 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4031 cpu_tlb_flushD_SE(cdstp);
4033 if (off || size != PAGE_SIZE)
4034 bzero((void *)(cdstp + off), size);
4038 xscale_cache_clean_minidata();
4042 * Change the PTEs for the specified kernel mappings such that they
4043 * will use the mini data cache instead of the main data cache.
4046 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4048 struct l2_bucket *l2b;
4049 pt_entry_t *ptep, *sptep, pte;
4050 vm_offset_t next_bucket, eva;
4052 #if (ARM_NMMUS > 1) || defined(CPU_XSCALE_CORE3)
4053 if (xscale_use_minidata == 0)
4060 next_bucket = L2_NEXT_BUCKET(va);
4061 if (next_bucket > eva)
4064 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4066 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4068 while (va < next_bucket) {
4070 if (!l2pte_minidata(pte)) {
4071 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4072 cpu_tlb_flushD_SE(va);
4073 *ptep = pte & ~L2_B;
4078 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4082 #endif /* ARM_MMU_XSCALE == 1 */
4085 * pmap_zero_page zeros the specified hardware page by mapping
4086 * the page into KVM and using bzero to clear its contents.
4089 pmap_zero_page(vm_page_t m)
4091 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4096 * pmap_zero_page_area zeros the specified hardware page by mapping
4097 * the page into KVM and using bzero to clear its contents.
4099 * off and size may not cover an area beyond a single hardware page.
4102 pmap_zero_page_area(vm_page_t m, int off, int size)
4105 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4110 * pmap_zero_page_idle zeros the specified hardware page by mapping
4111 * the page into KVM and using bzero to clear its contents. This
4112 * is intended to be called from the vm_pagezero process only and
4116 pmap_zero_page_idle(vm_page_t m)
4126 * This is a local function used to work out the best strategy to clean
4127 * a single page referenced by its entry in the PV table. It should be used by
4128 * pmap_copy_page, pmap_zero page and maybe some others later on.
4130 * Its policy is effectively:
4131 * o If there are no mappings, we don't bother doing anything with the cache.
4132 * o If there is one mapping, we clean just that page.
4133 * o If there are multiple mappings, we clean the entire cache.
4135 * So that some functions can be further optimised, it returns 0 if it didn't
4136 * clean the entire cache, or 1 if it did.
4138 * XXX One bug in this routine is that if the pv_entry has a single page
4139 * mapped at 0x00000000 a whole cache clean will be performed rather than
4140 * just the 1 page. Since this should not occur in everyday use and if it does
4141 * it will just result in not the most efficient clean for the page.
4143 * We don't yet use this function but may want to.
4146 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4148 pmap_t pm, pm_to_clean = NULL;
4149 struct pv_entry *npv;
4150 u_int cache_needs_cleaning = 0;
4152 vm_offset_t page_to_clean = 0;
4155 /* nothing mapped in so nothing to flush */
4160 * Since we flush the cache each time we change to a different
4161 * user vmspace, we only need to flush the page if it is in the
4165 pm = vmspace_pmap(curproc->p_vmspace);
4169 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4170 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4171 flags |= npv->pv_flags;
4173 * The page is mapped non-cacheable in
4174 * this map. No need to flush the cache.
4176 if (npv->pv_flags & PVF_NC) {
4178 if (cache_needs_cleaning)
4179 panic("pmap_clean_page: "
4180 "cache inconsistency");
4183 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4185 if (cache_needs_cleaning) {
4189 page_to_clean = npv->pv_va;
4190 pm_to_clean = npv->pv_pmap;
4192 cache_needs_cleaning = 1;
4195 if (page_to_clean) {
4196 if (PV_BEEN_EXECD(flags))
4197 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4200 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4201 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4202 } else if (cache_needs_cleaning) {
4203 if (PV_BEEN_EXECD(flags))
4204 pmap_idcache_wbinv_all(pm);
4206 pmap_dcache_wbinv_all(pm);
4214 * pmap_copy_page copies the specified (machine independent)
4215 * page by mapping the page into virtual memory and using
4216 * bcopy to copy the page, one machine dependent page at a
4223 * Copy one physical page into another, by mapping the pages into
4224 * hook points. The same comment regarding cachability as in
4225 * pmap_zero_page also applies here.
4227 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined (CPU_XSCALE_CORE3)
4229 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4232 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4236 * Clean the source page. Hold the source page's lock for
4237 * the duration of the copy so that no other mappings can
4238 * be created while we have a potentially aliased mapping.
4242 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4245 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4248 * Map the pages into the page hook points, copy them, and purge
4249 * the cache for the appropriate page. Invalidate the TLB
4253 *csrc_pte = L2_S_PROTO | src |
4254 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4256 *cdst_pte = L2_S_PROTO | dst |
4257 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4259 cpu_tlb_flushD_SE(csrcp);
4260 cpu_tlb_flushD_SE(cdstp);
4262 bcopy_page(csrcp, cdstp);
4264 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4265 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4266 cpu_l2cache_inv_range(csrcp, PAGE_SIZE);
4267 cpu_l2cache_wbinv_range(cdstp, PAGE_SIZE);
4271 pmap_copy_page_offs_generic(vm_paddr_t a_phys, vm_offset_t a_offs,
4272 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4276 *csrc_pte = L2_S_PROTO | a_phys |
4277 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4279 *cdst_pte = L2_S_PROTO | b_phys |
4280 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4282 cpu_tlb_flushD_SE(csrcp);
4283 cpu_tlb_flushD_SE(cdstp);
4285 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4287 cpu_dcache_inv_range(csrcp + a_offs, cnt);
4288 cpu_dcache_wbinv_range(cdstp + b_offs, cnt);
4289 cpu_l2cache_inv_range(csrcp + a_offs, cnt);
4290 cpu_l2cache_wbinv_range(cdstp + b_offs, cnt);
4292 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4294 #if ARM_MMU_XSCALE == 1
4296 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4299 /* XXX: Only needed for pmap_clean_page(), which is commented out. */
4300 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4304 * Clean the source page. Hold the source page's lock for
4305 * the duration of the copy so that no other mappings can
4306 * be created while we have a potentially aliased mapping.
4310 * XXX: Not needed while we call cpu_dcache_wbinv_all() in
4313 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4316 * Map the pages into the page hook points, copy them, and purge
4317 * the cache for the appropriate page. Invalidate the TLB
4321 *csrc_pte = L2_S_PROTO | src |
4322 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4323 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4325 *cdst_pte = L2_S_PROTO | dst |
4326 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4327 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4329 cpu_tlb_flushD_SE(csrcp);
4330 cpu_tlb_flushD_SE(cdstp);
4332 bcopy_page(csrcp, cdstp);
4334 xscale_cache_clean_minidata();
4338 pmap_copy_page_offs_xscale(vm_paddr_t a_phys, vm_offset_t a_offs,
4339 vm_paddr_t b_phys, vm_offset_t b_offs, int cnt)
4343 *csrc_pte = L2_S_PROTO | a_phys |
4344 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4345 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4347 *cdst_pte = L2_S_PROTO | b_phys |
4348 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4349 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
4351 cpu_tlb_flushD_SE(csrcp);
4352 cpu_tlb_flushD_SE(cdstp);
4354 bcopy((char *)csrcp + a_offs, (char *)cdstp + b_offs, cnt);
4356 xscale_cache_clean_minidata();
4358 #endif /* ARM_MMU_XSCALE == 1 */
4361 pmap_copy_page(vm_page_t src, vm_page_t dst)
4364 cpu_dcache_wbinv_all();
4365 cpu_l2cache_wbinv_all();
4366 if (_arm_memcpy && PAGE_SIZE >= _min_memcpy_size &&
4367 _arm_memcpy((void *)VM_PAGE_TO_PHYS(dst),
4368 (void *)VM_PAGE_TO_PHYS(src), PAGE_SIZE, IS_PHYSICAL) == 0)
4370 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4373 int unmapped_buf_allowed = 1;
4376 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4377 vm_offset_t b_offset, int xfersize)
4379 vm_page_t a_pg, b_pg;
4380 vm_offset_t a_pg_offset, b_pg_offset;
4383 cpu_dcache_wbinv_all();
4384 cpu_l2cache_wbinv_all();
4385 while (xfersize > 0) {
4386 a_pg = ma[a_offset >> PAGE_SHIFT];
4387 a_pg_offset = a_offset & PAGE_MASK;
4388 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4389 b_pg = mb[b_offset >> PAGE_SHIFT];
4390 b_pg_offset = b_offset & PAGE_MASK;
4391 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4392 pmap_copy_page_offs_func(VM_PAGE_TO_PHYS(a_pg), a_pg_offset,
4393 VM_PAGE_TO_PHYS(b_pg), b_pg_offset, cnt);
4401 * this routine returns true if a physical page resides
4402 * in the given pmap.
4405 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4411 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4412 ("pmap_page_exists_quick: page %p is not managed", m));
4414 rw_wlock(&pvh_global_lock);
4415 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4416 if (pv->pv_pmap == pmap) {
4424 rw_wunlock(&pvh_global_lock);
4429 * pmap_page_wired_mappings:
4431 * Return the number of managed mappings to the given physical page
4435 pmap_page_wired_mappings(vm_page_t m)
4441 if ((m->oflags & VPO_UNMANAGED) != 0)
4443 rw_wlock(&pvh_global_lock);
4444 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
4445 if ((pv->pv_flags & PVF_WIRED) != 0)
4447 rw_wunlock(&pvh_global_lock);
4452 * This function is advisory.
4455 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4460 * pmap_ts_referenced:
4462 * Return the count of reference bits for a page, clearing all of them.
4465 pmap_ts_referenced(vm_page_t m)
4468 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4469 ("pmap_ts_referenced: page %p is not managed", m));
4470 return (pmap_clearbit(m, PVF_REF));
4475 pmap_is_modified(vm_page_t m)
4478 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4479 ("pmap_is_modified: page %p is not managed", m));
4480 if (m->md.pvh_attrs & PVF_MOD)
4488 * Clear the modify bits on the specified physical page.
4491 pmap_clear_modify(vm_page_t m)
4494 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4495 ("pmap_clear_modify: page %p is not managed", m));
4496 VM_OBJECT_ASSERT_WLOCKED(m->object);
4497 KASSERT(!vm_page_xbusied(m),
4498 ("pmap_clear_modify: page %p is exclusive busied", m));
4501 * If the page is not PGA_WRITEABLE, then no mappings can be modified.
4502 * If the object containing the page is locked and the page is not
4503 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4505 if ((m->aflags & PGA_WRITEABLE) == 0)
4507 if (m->md.pvh_attrs & PVF_MOD)
4508 pmap_clearbit(m, PVF_MOD);
4513 * pmap_is_referenced:
4515 * Return whether or not the specified physical page was referenced
4516 * in any physical maps.
4519 pmap_is_referenced(vm_page_t m)
4522 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4523 ("pmap_is_referenced: page %p is not managed", m));
4524 return ((m->md.pvh_attrs & PVF_REF) != 0);
4529 * Clear the write and modified bits in each of the given page's mappings.
4532 pmap_remove_write(vm_page_t m)
4535 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4536 ("pmap_remove_write: page %p is not managed", m));
4539 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4540 * set by another thread while the object is locked. Thus,
4541 * if PGA_WRITEABLE is clear, no page table entries need updating.
4543 VM_OBJECT_ASSERT_WLOCKED(m->object);
4544 if (vm_page_xbusied(m) || (m->aflags & PGA_WRITEABLE) != 0)
4545 pmap_clearbit(m, PVF_WRITE);
4550 * perform the pmap work for mincore
4553 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4555 struct l2_bucket *l2b;
4556 pt_entry_t *ptep, pte;
4564 l2b = pmap_get_l2_bucket(pmap, addr);
4569 ptep = &l2b->l2b_kva[l2pte_index(addr)];
4571 if (!l2pte_valid(pte)) {
4575 val = MINCORE_INCORE;
4576 if (pte & L2_S_PROT_W)
4577 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4580 m = PHYS_TO_VM_PAGE(pa);
4581 if (m != NULL && !(m->oflags & VPO_UNMANAGED))
4585 * The ARM pmap tries to maintain a per-mapping
4586 * reference bit. The trouble is that it's kept in
4587 * the PV entry, not the PTE, so it's costly to access
4588 * here. You would need to acquire the pvh global
4589 * lock, call pmap_find_pv(), and introduce a custom
4590 * version of vm_page_pa_tryrelock() that releases and
4591 * reacquires the pvh global lock. In the end, I
4592 * doubt it's worthwhile. This may falsely report
4593 * the given address as referenced.
4595 if ((m->md.pvh_attrs & PVF_REF) != 0)
4596 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4598 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4599 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4600 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4601 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4605 PA_UNLOCK_COND(*locked_pa);
4612 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
4618 * Increase the starting virtual address of the given mapping if a
4619 * different alignment might result in more superpage mappings.
4622 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4623 vm_offset_t *addr, vm_size_t size)
4627 #define BOOTSTRAP_DEBUG
4632 * Create a single section mapping.
4635 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4636 int prot, int cache)
4638 pd_entry_t *pde = (pd_entry_t *) l1pt;
4641 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4650 fl = pte_l1_s_cache_mode;
4654 fl = pte_l1_s_cache_mode_pt;
4658 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4659 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4660 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4667 * Link the L2 page table specified by l2pv.pv_pa into the L1
4668 * page table at the slot for "va".
4671 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4673 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4674 u_int slot = va >> L1_S_SHIFT;
4676 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4678 #ifdef VERBOSE_INIT_ARM
4679 printf("pmap_link_l2pt: pa=0x%x va=0x%x\n", l2pv->pv_pa, l2pv->pv_va);
4682 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4684 PTE_SYNC(&pde[slot]);
4686 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4694 * Create a single page mapping.
4697 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4700 pd_entry_t *pde = (pd_entry_t *) l1pt;
4704 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4713 fl = pte_l2_s_cache_mode;
4717 fl = pte_l2_s_cache_mode_pt;
4721 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4722 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4724 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4727 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4729 pte[l2pte_index(va)] =
4730 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4731 PTE_SYNC(&pte[l2pte_index(va)]);
4737 * Map a chunk of memory using the most efficient mappings
4738 * possible (section. large page, small page) into the
4739 * provided L1 and L2 tables at the specified virtual address.
4742 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4743 vm_size_t size, int prot, int cache)
4745 pd_entry_t *pde = (pd_entry_t *) l1pt;
4746 pt_entry_t *pte, f1, f2s, f2l;
4750 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4753 panic("pmap_map_chunk: no L1 table provided");
4755 #ifdef VERBOSE_INIT_ARM
4756 printf("pmap_map_chunk: pa=0x%x va=0x%x size=0x%x resid=0x%x "
4757 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4769 f1 = pte_l1_s_cache_mode;
4770 f2l = pte_l2_l_cache_mode;
4771 f2s = pte_l2_s_cache_mode;
4775 f1 = pte_l1_s_cache_mode_pt;
4776 f2l = pte_l2_l_cache_mode_pt;
4777 f2s = pte_l2_s_cache_mode_pt;
4784 /* See if we can use a section mapping. */
4785 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4786 #ifdef VERBOSE_INIT_ARM
4789 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4790 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4791 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4792 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4800 * Ok, we're going to use an L2 table. Make sure
4801 * one is actually in the corresponding L1 slot
4802 * for the current VA.
4804 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4805 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4807 pte = (pt_entry_t *) kernel_pt_lookup(
4808 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4810 panic("pmap_map_chunk: can't find L2 table for VA"
4812 /* See if we can use a L2 large page mapping. */
4813 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4814 #ifdef VERBOSE_INIT_ARM
4817 for (i = 0; i < 16; i++) {
4818 pte[l2pte_index(va) + i] =
4820 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4821 PTE_SYNC(&pte[l2pte_index(va) + i]);
4829 /* Use a small page mapping. */
4830 #ifdef VERBOSE_INIT_ARM
4833 pte[l2pte_index(va)] =
4834 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4835 PTE_SYNC(&pte[l2pte_index(va)]);
4840 #ifdef VERBOSE_INIT_ARM
4848 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4851 * Remember the memattr in a field that gets used to set the appropriate
4852 * bits in the PTEs as mappings are established.
4854 m->md.pv_memattr = ma;
4857 * It appears that this function can only be called before any mappings
4858 * for the page are established on ARM. If this ever changes, this code
4859 * will need to walk the pv_list and make each of the existing mappings
4860 * uncacheable, being careful to sync caches and PTEs (and maybe
4861 * invalidate TLB?) for any current mapping it modifies.
4863 if (m->md.pv_kva != 0 || TAILQ_FIRST(&m->md.pv_list) != NULL)
4864 panic("Can't change memattr on page with existing mappings");