2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Copyright (c) 2010 Greg Ansley. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/kthread.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/queue.h>
44 #include <sys/resource.h>
46 #include <sys/sysctl.h>
48 #include <sys/timetc.h>
49 #include <sys/watchdog.h>
51 #include <machine/bus.h>
52 #include <machine/cpu.h>
53 #include <machine/cpufunc.h>
54 #include <machine/resource.h>
55 #include <machine/frame.h>
56 #include <machine/intr.h>
58 #include <arm/at91/at91var.h>
59 #include <arm/at91/at91_mcireg.h>
60 #include <arm/at91/at91_pdcreg.h>
62 #include <dev/mmc/bridge.h>
63 #include <dev/mmc/mmcreg.h>
64 #include <dev/mmc/mmcbrvar.h>
72 struct at91_mci_softc {
73 void *intrhand; /* Interrupt handle */
76 #define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
77 #define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
81 #define STOP_STARTED 2
82 struct resource *irq_res; /* IRQ resource */
83 struct resource *mem_res; /* Memory resource */
90 struct mmc_request *req;
91 struct mmc_command *curcmd;
92 char bounce_buffer[BBSZ];
95 static inline uint32_t
96 RD4(struct at91_mci_softc *sc, bus_size_t off)
98 return (bus_read_4(sc->mem_res, off));
102 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
104 bus_write_4(sc->mem_res, off, val);
107 /* bus entry points */
108 static int at91_mci_probe(device_t dev);
109 static int at91_mci_attach(device_t dev);
110 static int at91_mci_detach(device_t dev);
111 static void at91_mci_intr(void *);
113 /* helper routines */
114 static int at91_mci_activate(device_t dev);
115 static void at91_mci_deactivate(device_t dev);
116 static int at91_mci_is_mci1rev2xx(void);
118 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
119 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
120 #define AT91_MCI_LOCK_INIT(_sc) \
121 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
123 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
124 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
125 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
128 at91_mci_pdc_disable(struct at91_mci_softc *sc)
130 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
133 WR4(sc, PDC_RNPR, 0);
134 WR4(sc, PDC_RNCR, 0);
137 WR4(sc, PDC_TNPR, 0);
138 WR4(sc, PDC_TNCR, 0);
142 at91_mci_init(device_t dev)
144 struct at91_mci_softc *sc = device_get_softc(dev);
147 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */
148 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
149 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
150 val = MCI_MR_PDCMODE;
151 val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
152 if (at91_mci_is_mci1rev2xx())
153 val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
154 WR4(sc, MCI_MR, val);
155 #ifndef AT91_MCI_SLOT_B
156 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
158 /* XXX Really should add second "unit" but nobody using using
159 * a two slot card that we know of. XXX */
160 WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
165 at91_mci_fini(device_t dev)
167 struct at91_mci_softc *sc = device_get_softc(dev);
169 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
170 at91_mci_pdc_disable(sc);
171 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* Put the device into reset */
175 at91_mci_probe(device_t dev)
178 device_set_desc(dev, "MCI mmc/sd host bridge");
183 at91_mci_attach(device_t dev)
185 struct at91_mci_softc *sc = device_get_softc(dev);
186 struct sysctl_ctx_list *sctx;
187 struct sysctl_oid *soid;
195 sc->sc_cap |= CAP_NEEDS_BYTESWAP;
196 err = at91_mci_activate(dev);
200 AT91_MCI_LOCK_INIT(sc);
203 * Allocate DMA tags and maps
205 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
206 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, 1,
207 MAXPHYS, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag);
211 err = bus_dmamap_create(sc->dmatag, 0, &sc->map);
219 * Activate the interrupt
221 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
222 NULL, at91_mci_intr, sc, &sc->intrhand);
224 AT91_MCI_LOCK_DESTROY(sc);
228 sctx = device_get_sysctl_ctx(dev);
229 soid = device_get_sysctl_tree(dev);
230 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
231 CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
233 #ifdef AT91_MCI_HAS_4WIRE
237 sc->sc_cap |= CAP_HAS_4WIRE;
239 sc->host.f_min = at91_master_clock / 512;
240 sc->host.f_min = 375000;
241 sc->host.f_max = at91_master_clock / 2;
242 if (sc->host.f_max > 50000000)
243 sc->host.f_max = 50000000; /* Limit to 50MHz */
245 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
247 if (sc->sc_cap & CAP_HAS_4WIRE)
248 sc->host.caps |= MMC_CAP_4_BIT_DATA;
249 child = device_add_child(dev, "mmc", 0);
250 device_set_ivars(dev, &sc->host);
251 err = bus_generic_attach(dev);
254 at91_mci_deactivate(dev);
259 at91_mci_detach(device_t dev)
262 at91_mci_deactivate(dev);
263 return (EBUSY); /* XXX */
267 at91_mci_activate(device_t dev)
269 struct at91_mci_softc *sc;
272 sc = device_get_softc(dev);
274 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
276 if (sc->mem_res == NULL)
280 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
282 if (sc->irq_res == NULL)
287 at91_mci_deactivate(dev);
292 at91_mci_deactivate(device_t dev)
294 struct at91_mci_softc *sc;
296 sc = device_get_softc(dev);
298 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
300 bus_generic_detach(sc->dev);
302 bus_release_resource(dev, SYS_RES_IOPORT,
303 rman_get_rid(sc->mem_res), sc->mem_res);
306 bus_release_resource(dev, SYS_RES_IRQ,
307 rman_get_rid(sc->irq_res), sc->irq_res);
313 at91_mci_is_mci1rev2xx(void)
316 switch (AT91_CPU(at91_chip_id)) {
317 case AT91_CPU_SAM9260:
318 case AT91_CPU_SAM9263:
322 case AT91_CPU_SAM9G10:
323 case AT91_CPU_SAM9G20:
325 case AT91_CPU_SAM9RL:
327 case AT91_CPU_SAM9XE128:
328 case AT91_CPU_SAM9XE256:
329 case AT91_CPU_SAM9XE512:
336 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
340 *(bus_addr_t *)arg = segs[0].ds_addr;
344 at91_mci_update_ios(device_t brdev, device_t reqdev)
346 struct at91_mci_softc *sc;
347 struct mmc_host *host;
351 sc = device_get_softc(brdev);
355 if (ios->clock == 0) {
356 WR4(sc, MCI_CR, MCI_CR_MCIDIS);
359 WR4(sc, MCI_CR, MCI_CR_MCIEN);
360 if ((at91_master_clock % (ios->clock * 2)) == 0)
361 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
363 clkdiv = (at91_master_clock / ios->clock) / 2;
365 if (ios->bus_width == bus_width_4)
366 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
368 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
369 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
370 /* Do we need a settle time here? */
371 /* XXX We need to turn the device on/off here with a GPIO pin */
376 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
379 uint32_t cmdr, ier = 0, mr;
382 struct mmc_data *data;
390 /* XXX Upper layers don't always set this */
393 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
394 cmdr |= MCI_CMDR_RSPTYP_NO;
396 /* Allow big timeout for responses */
397 cmdr |= MCI_CMDR_MAXLAT;
398 if (cmd->flags & MMC_RSP_136)
399 cmdr |= MCI_CMDR_RSPTYP_136;
401 cmdr |= MCI_CMDR_RSPTYP_48;
403 if (cmd->opcode == MMC_STOP_TRANSMISSION)
404 cmdr |= MCI_CMDR_TRCMD_STOP;
405 if (sc->host.ios.bus_mode == opendrain)
406 cmdr |= MCI_CMDR_OPDCMD;
408 // The no data case is fairly simple
409 at91_mci_pdc_disable(sc);
410 // printf("CMDR %x ARGR %x\n", cmdr, cmd->arg);
411 WR4(sc, MCI_ARGR, cmd->arg);
412 WR4(sc, MCI_CMDR, cmdr);
413 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
416 if (data->flags & MMC_DATA_READ)
417 cmdr |= MCI_CMDR_TRDIR;
418 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
419 cmdr |= MCI_CMDR_TRCMD_START;
420 if (data->flags & MMC_DATA_STREAM)
421 cmdr |= MCI_CMDR_TRTYP_STREAM;
422 if (data->flags & MMC_DATA_MULTI)
423 cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
424 // Set block size and turn on PDC mode for dma xfer and disable
425 // PDC until we're ready.
426 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
427 WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
428 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
429 if (cmdr & MCI_CMDR_TRCMD_START) {
431 if (cmdr & MCI_CMDR_TRDIR)
432 vaddr = cmd->data->data;
434 /* Use bounce buffer even if we don't need
435 * byteswap, since buffer may straddle a page
436 * boundry, and we don't handle multi-segment
437 * transfers in hardware.
438 * (page issues seen from 'bsdlabel -w' which
439 * uses raw geom access to the volume).
440 * Greg Ansley (gja (at) ansley.com)
442 vaddr = sc->bounce_buffer;
443 src = (uint32_t *)cmd->data->data;
444 dst = (uint32_t *)vaddr;
446 * If this is MCI1 revision 2xx controller, apply
447 * a work-around for the "Data Write Operation and
448 * number of bytes" erratum.
450 if (at91_mci_is_mci1rev2xx() && data->len < 12) {
454 if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
455 for (i = 0; i < data->len / 4; i++)
456 dst[i] = bswap32(src[i]);
458 memcpy(dst, src, data->len);
461 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, len,
462 at91_mci_getaddr, &paddr, 0) != 0) {
463 cmd->error = MMC_ERR_NO_MEMORY;
466 cmd->mrq->done(cmd->mrq);
470 if (cmdr & MCI_CMDR_TRDIR) {
471 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
472 WR4(sc, PDC_RPR, paddr);
473 WR4(sc, PDC_RCR, len / 4);
476 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE);
477 WR4(sc, PDC_TPR, paddr);
478 WR4(sc, PDC_TCR, len / 4);
482 // printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg);
483 WR4(sc, MCI_ARGR, cmd->arg);
484 if (cmdr & MCI_CMDR_TRCMD_START) {
485 if (cmdr & MCI_CMDR_TRDIR) {
486 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
487 WR4(sc, MCI_CMDR, cmdr);
489 WR4(sc, MCI_CMDR, cmdr);
490 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
493 WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
497 at91_mci_start(struct at91_mci_softc *sc)
499 struct mmc_request *req;
505 if (!(sc->flags & CMD_STARTED)) {
506 sc->flags |= CMD_STARTED;
507 // printf("Starting CMD\n");
508 at91_mci_start_cmd(sc, req->cmd);
511 if (!(sc->flags & STOP_STARTED) && req->stop) {
512 // printf("Starting Stop\n");
513 sc->flags |= STOP_STARTED;
514 at91_mci_start_cmd(sc, req->stop);
517 /* We must be done -- bad idea to do this while locked? */
524 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
526 struct at91_mci_softc *sc = device_get_softc(brdev);
529 // XXX do we want to be able to queue up multiple commands?
530 // XXX sounds like a good idea, but all protocols are sync, so
531 // XXX maybe the idea is naive...
532 if (sc->req != NULL) {
544 at91_mci_get_ro(device_t brdev, device_t reqdev)
550 at91_mci_acquire_host(device_t brdev, device_t reqdev)
552 struct at91_mci_softc *sc = device_get_softc(brdev);
557 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
564 at91_mci_release_host(device_t brdev, device_t reqdev)
566 struct at91_mci_softc *sc = device_get_softc(brdev);
576 at91_mci_read_done(struct at91_mci_softc *sc)
579 struct mmc_command *cmd;
583 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
584 bus_dmamap_unload(sc->dmatag, sc->map);
586 if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
587 walker = (uint32_t *)cmd->data->data;
588 len = cmd->data->len / 4;
589 for (i = 0; i < len; i++)
590 walker[i] = bswap32(walker[i]);
592 // Finish up the sequence...
593 WR4(sc, MCI_IDR, MCI_SR_ENDRX);
594 WR4(sc, MCI_IER, MCI_SR_RXBUFF);
595 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
599 at91_mci_xmit_done(struct at91_mci_softc *sc)
601 // Finish up the sequence...
602 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
603 WR4(sc, MCI_IDR, MCI_SR_TXBUFE);
604 WR4(sc, MCI_IER, MCI_SR_NOTBUSY);
605 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTWRITE);
606 bus_dmamap_unload(sc->dmatag, sc->map);
611 at91_mci_intr(void *arg)
613 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
616 struct mmc_command *cmd;
619 sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR);
620 // printf("i 0x%x\n", sr);
622 if (sr & MCI_SR_ERROR) {
623 // Ignore CRC errors on CMD2 and ACMD47, per relevant standards
624 if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND ||
625 cmd->opcode == ACMD_SD_SEND_OP_COND))
626 cmd->error = MMC_ERR_NONE;
627 else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE))
628 cmd->error = MMC_ERR_TIMEOUT;
629 else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
630 cmd->error = MMC_ERR_BADCRC;
631 else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE))
632 cmd->error = MMC_ERR_FIFO;
634 cmd->error = MMC_ERR_FAILED;
636 if (sc->mapped && cmd->error) {
637 bus_dmamap_unload(sc->dmatag, sc->map);
641 if (sr & MCI_SR_TXBUFE) {
642 // printf("TXBUFE\n");
643 at91_mci_xmit_done(sc);
645 if (sr & MCI_SR_RXBUFF) {
646 // printf("RXBUFF\n");
647 WR4(sc, MCI_IDR, MCI_SR_RXBUFF);
648 WR4(sc, MCI_IER, MCI_SR_CMDRDY);
650 if (sr & MCI_SR_ENDTX) {
651 // printf("ENDTX\n");
653 if (sr & MCI_SR_ENDRX) {
654 // printf("ENDRX\n");
655 at91_mci_read_done(sc);
657 if (sr & MCI_SR_NOTBUSY) {
658 // printf("NOTBUSY\n");
659 WR4(sc, MCI_IDR, MCI_SR_NOTBUSY);
660 WR4(sc, MCI_IER, MCI_SR_CMDRDY);
662 if (sr & MCI_SR_DTIP) {
663 // printf("Data transfer in progress\n");
665 if (sr & MCI_SR_BLKE) {
666 // printf("Block transfer end\n");
668 if (sr & MCI_SR_TXRDY) {
669 // printf("Ready to transmit\n");
671 if (sr & MCI_SR_RXRDY) {
672 // printf("Ready to receive\n");
674 if (sr & MCI_SR_CMDRDY) {
675 // printf("Command ready\n");
677 cmd->error = MMC_ERR_NONE;
681 WR4(sc, MCI_IDR, 0xffffffff);
682 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) {
683 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1);
685 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
686 // printf("RSPR[%d] = %x\n", i, cmd->resp[i]);
695 at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
697 struct at91_mci_softc *sc = device_get_softc(bus);
702 case MMCBR_IVAR_BUS_MODE:
703 *(int *)result = sc->host.ios.bus_mode;
705 case MMCBR_IVAR_BUS_WIDTH:
706 *(int *)result = sc->host.ios.bus_width;
708 case MMCBR_IVAR_CHIP_SELECT:
709 *(int *)result = sc->host.ios.chip_select;
711 case MMCBR_IVAR_CLOCK:
712 *(int *)result = sc->host.ios.clock;
714 case MMCBR_IVAR_F_MIN:
715 *(int *)result = sc->host.f_min;
717 case MMCBR_IVAR_F_MAX:
718 *(int *)result = sc->host.f_max;
720 case MMCBR_IVAR_HOST_OCR:
721 *(int *)result = sc->host.host_ocr;
723 case MMCBR_IVAR_MODE:
724 *(int *)result = sc->host.mode;
727 *(int *)result = sc->host.ocr;
729 case MMCBR_IVAR_POWER_MODE:
730 *(int *)result = sc->host.ios.power_mode;
733 *(int *)result = sc->host.ios.vdd;
735 case MMCBR_IVAR_CAPS:
737 sc->sc_cap |= CAP_HAS_4WIRE;
738 sc->host.caps |= MMC_CAP_4_BIT_DATA;
740 sc->sc_cap &= ~CAP_HAS_4WIRE;
741 sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
743 *(int *)result = sc->host.caps;
745 case MMCBR_IVAR_MAX_DATA:
753 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
755 struct at91_mci_softc *sc = device_get_softc(bus);
760 case MMCBR_IVAR_BUS_MODE:
761 sc->host.ios.bus_mode = value;
763 case MMCBR_IVAR_BUS_WIDTH:
764 sc->host.ios.bus_width = value;
766 case MMCBR_IVAR_CHIP_SELECT:
767 sc->host.ios.chip_select = value;
769 case MMCBR_IVAR_CLOCK:
770 sc->host.ios.clock = value;
772 case MMCBR_IVAR_MODE:
773 sc->host.mode = value;
776 sc->host.ocr = value;
778 case MMCBR_IVAR_POWER_MODE:
779 sc->host.ios.power_mode = value;
782 sc->host.ios.vdd = value;
784 /* These are read-only */
785 case MMCBR_IVAR_CAPS:
786 case MMCBR_IVAR_HOST_OCR:
787 case MMCBR_IVAR_F_MIN:
788 case MMCBR_IVAR_F_MAX:
789 case MMCBR_IVAR_MAX_DATA:
795 static device_method_t at91_mci_methods[] = {
797 DEVMETHOD(device_probe, at91_mci_probe),
798 DEVMETHOD(device_attach, at91_mci_attach),
799 DEVMETHOD(device_detach, at91_mci_detach),
802 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar),
803 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar),
806 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
807 DEVMETHOD(mmcbr_request, at91_mci_request),
808 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
809 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
810 DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
815 static driver_t at91_mci_driver = {
818 sizeof(struct at91_mci_softc),
821 static devclass_t at91_mci_devclass;
823 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,