2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #ifndef AT91RM92REG_H_
29 #define AT91RM92REG_H_
31 /* Chip Specific limits */
32 #define RM9200_PLL_A_MIN_IN_FREQ 1000000 /* 1 MHz */
33 #define RM9200_PLL_A_MAX_IN_FREQ 32000000 /* 32 MHz */
34 #define RM9200_PLL_A_MIN_OUT_FREQ 80000000 /* 80 MHz */
35 #define RM9200_PLL_A_MAX_OUT_FREQ 180000000 /* 180 MHz */
36 #define RM9200_PLL_A_MUL_SHIFT 16
37 #define RM9200_PLL_A_MUL_MASK 0x7FF
38 #define RM9200_PLL_A_DIV_SHIFT 0
39 #define RM9200_PLL_A_DIV_MASK 0xFF
42 * PLL B input frequency spec sheet says it must be between 1MHz and 32MHz,
43 * but it works down as low as 100kHz, a frequency necessary for some
44 * output frequencies to work.
46 * PLL Max output frequency is 240MHz. The errata says 180MHz is the max
47 * for some revisions of this part. Be more permissive and optimistic.
49 #define RM9200_PLL_B_MIN_IN_FREQ 100000 /* 100 KHz */
50 #define RM9200_PLL_B_MAX_IN_FREQ 32000000 /* 32 MHz */
51 #define RM9200_PLL_B_MIN_OUT_FREQ 30000000 /* 30 MHz */
52 #define RM9200_PLL_B_MAX_OUT_FREQ 240000000 /* 240 MHz */
53 #define RM9200_PLL_B_MUL_SHIFT 16
54 #define RM9200_PLL_B_MUL_MASK 0x7FF
55 #define RM9200_PLL_B_DIV_SHIFT 0
56 #define RM9200_PLL_B_DIV_MASK 0xFF
58 * Memory map, from datasheet :
59 * 0x00000000 - 0x0ffffffff : Internal Memories
60 * 0x10000000 - 0x1ffffffff : Chip Select 0
61 * 0x20000000 - 0x2ffffffff : Chip Select 1
62 * 0x30000000 - 0x3ffffffff : Chip Select 2
63 * 0x40000000 - 0x4ffffffff : Chip Select 3
64 * 0x50000000 - 0x5ffffffff : Chip Select 4
65 * 0x60000000 - 0x6ffffffff : Chip Select 5
66 * 0x70000000 - 0x7ffffffff : Chip Select 6
67 * 0x80000000 - 0x8ffffffff : Chip Select 7
68 * 0x90000000 - 0xeffffffff : Undefined (Abort)
69 * 0xf0000000 - 0xfffffffff : Peripherals
72 #define AT91RM92_BASE 0xd0000000
75 #define AT91RM92_USART_SIZE 0x4000
76 #define AT91RM92_USART0_BASE 0xffc0000
77 #define AT91RM92_USART0_PDC 0xffc0100
78 #define AT91RM92_USART0_SIZE AT91RM92_USART_SIZE
79 #define AT91RM92_USART1_BASE 0xffc4000
80 #define AT91RM92_USART1_PDC 0xffc4100
81 #define AT91RM92_USART1_SIZE AT91RM92_USART_SIZE
82 #define AT91RM92_USART2_BASE 0xffc8000
83 #define AT91RM92_USART2_PDC 0xffc8100
84 #define AT91RM92_USART2_SIZE AT91RM92_USART_SIZE
85 #define AT91RM92_USART3_BASE 0xffcc000
86 #define AT91RM92_USART3_PDC 0xffcc100
87 #define AT91RM92_USART3_SIZE AT91RM92_USART_SIZE
89 /* System Registers */
91 #define AT91RM92_SYS_BASE 0xffff000
92 #define AT91RM92_SYS_SIZE 0x1000
95 /* Interrupt Controller */
96 #define IC_SMR (0) /* Source mode register */
97 #define IC_SVR (128) /* Source vector register */
98 #define IC_IVR (256) /* IRQ vector register */
99 #define IC_FVR (260) /* FIQ vector register */
100 #define IC_ISR (264) /* Interrupt status register */
101 #define IC_IPR (268) /* Interrupt pending register */
102 #define IC_IMR (272) /* Interrupt status register */
103 #define IC_CISR (276) /* Core interrupt status register */
104 #define IC_IECR (288) /* Interrupt enable command register */
105 #define IC_IDCR (292) /* Interrupt disable command register */
106 #define IC_ICCR (296) /* Interrupt clear command register */
107 #define IC_ISCR (300) /* Interrupt set command register */
108 #define IC_EOICR (304) /* End of interrupt command register */
109 #define IC_SPU (308) /* Spurious vector register */
110 #define IC_DCR (312) /* Debug control register */
111 #define IC_FFER (320) /* Fast forcing enable register */
112 #define IC_FFDR (324) /* Fast forcing disable register */
113 #define IC_FFSR (328) /* Fast forcing status register */
116 #define PIOA_PER (0x400) /* PIO Enable Register */
117 #define PIOA_PDR (0x400 + 4) /* PIO Disable Register */
118 #define PIOA_PSR (0x400 + 8) /* PIO status register */
119 #define PIOA_OER (0x400 + 16) /* Output enable register */
120 #define PIOA_ODR (0x400 + 20) /* Output disable register */
121 #define PIOA_OSR (0x400 + 24) /* Output status register */
122 #define PIOA_IFER (0x400 + 32) /* Input filter enable register */
123 #define PIOA_IFDR (0x400 + 36) /* Input filter disable register */
124 #define PIOA_IFSR (0x400 + 40) /* Input filter status register */
125 #define PIOA_SODR (0x400 + 48) /* Set output data register */
126 #define PIOA_CODR (0x400 + 52) /* Clear output data register */
127 #define PIOA_ODSR (0x400 + 56) /* Output data status register */
128 #define PIOA_PDSR (0x400 + 60) /* Pin data status register */
129 #define PIOA_IER (0x400 + 64) /* Interrupt enable register */
130 #define PIOA_IDR (0x400 + 68) /* Interrupt disable register */
131 #define PIOA_IMR (0x400 + 72) /* Interrupt mask register */
132 #define PIOA_ISR (0x400 + 76) /* Interrupt status register */
133 #define PIOA_MDER (0x400 + 80) /* Multi driver enable register */
134 #define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */
135 #define PIOA_MDSR (0x400 + 88) /* Multi driver status register */
136 #define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */
137 #define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */
138 #define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */
139 #define PIOA_ASR (0x400 + 112) /* Select A register */
140 #define PIOA_BSR (0x400 + 116) /* Select B register */
141 #define PIOA_ABSR (0x400 + 120) /* AB Select status register */
142 #define PIOA_OWER (0x400 + 160) /* Output Write enable register */
143 #define PIOA_OWDR (0x400 + 164) /* Output write disable register */
144 #define PIOA_OWSR (0x400 + 168) /* Output write status register */
145 #define PIOB_PER (0x400) /* PIO Enable Register */
146 #define PIOB_PDR (0x600 + 4) /* PIO Disable Register */
147 #define PIOB_PSR (0x600 + 8) /* PIO status register */
148 #define PIOB_OER (0x600 + 16) /* Output enable register */
149 #define PIOB_ODR (0x600 + 20) /* Output disable register */
150 #define PIOB_OSR (0x600 + 24) /* Output status register */
151 #define PIOB_IFER (0x600 + 32) /* Input filter enable register */
152 #define PIOB_IFDR (0x600 + 36) /* Input filter disable register */
153 #define PIOB_IFSR (0x600 + 40) /* Input filter status register */
154 #define PIOB_SODR (0x600 + 48) /* Set output data register */
155 #define PIOB_CODR (0x600 + 52) /* Clear output data register */
156 #define PIOB_ODSR (0x600 + 56) /* Output data status register */
157 #define PIOB_PDSR (0x600 + 60) /* Pin data status register */
158 #define PIOB_IER (0x600 + 64) /* Interrupt enable register */
159 #define PIOB_IDR (0x600 + 68) /* Interrupt disable register */
160 #define PIOB_IMR (0x600 + 72) /* Interrupt mask register */
161 #define PIOB_ISR (0x600 + 76) /* Interrupt status register */
162 #define PIOB_MDER (0x600 + 80) /* Multi driver enable register */
163 #define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */
164 #define PIOB_MDSR (0x600 + 88) /* Multi driver status register */
165 #define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */
166 #define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */
167 #define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */
168 #define PIOB_ASR (0x600 + 112) /* Select A register */
169 #define PIOB_BSR (0x600 + 116) /* Select B register */
170 #define PIOB_ABSR (0x600 + 120) /* AB Select status register */
171 #define PIOB_OWER (0x600 + 160) /* Output Write enable register */
172 #define PIOB_OWDR (0x600 + 164) /* Output write disable register */
173 #define PIOB_OWSR (0x600 + 168) /* Output write status register */
174 #define PIOC_PER (0x800) /* PIO Enable Register */
175 #define PIOC_PDR (0x800 + 4) /* PIO Disable Register */
176 #define PIOC_PSR (0x800 + 8) /* PIO status register */
177 #define PIOC_OER (0x800 + 16) /* Output enable register */
178 #define PIOC_ODR (0x800 + 20) /* Output disable register */
179 #define PIOC_OSR (0x800 + 24) /* Output status register */
180 #define PIOC_IFER (0x800 + 32) /* Input filter enable register */
181 #define PIOC_IFDR (0x800 + 36) /* Input filter disable register */
182 #define PIOC_IFSR (0x800 + 40) /* Input filter status register */
183 #define PIOC_SODR (0x800 + 48) /* Set output data register */
184 #define PIOC_CODR (0x800 + 52) /* Clear output data register */
185 #define PIOC_ODSR (0x800 + 56) /* Output data status register */
186 #define PIOC_PDSR (0x800 + 60) /* Pin data status register */
187 #define PIOC_IER (0x800 + 64) /* Interrupt enable register */
188 #define PIOC_IDR (0x800 + 68) /* Interrupt disable register */
189 #define PIOC_IMR (0x800 + 72) /* Interrupt mask register */
190 #define PIOC_ISR (0x800 + 76) /* Interrupt status register */
191 #define PIOC_MDER (0x800 + 80) /* Multi driver enable register */
192 #define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */
193 #define PIOC_MDSR (0x800 + 88) /* Multi driver status register */
194 #define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */
195 #define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */
196 #define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */
197 #define PIOC_ASR (0x800 + 112) /* Select A register */
198 #define PIOC_BSR (0x800 + 116) /* Select B register */
199 #define PIOC_ABSR (0x800 + 120) /* AB Select status register */
200 #define PIOC_OWER (0x800 + 160) /* Output Write enable register */
201 #define PIOC_OWDR (0x800 + 164) /* Output write disable register */
202 #define PIOC_OWSR (0x800 + 168) /* Output write status register */
203 #define PIOD_PER (0xa00) /* PIO Enable Register */
204 #define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */
205 #define PIOD_PSR (0xa00 + 8) /* PIO status register */
206 #define PIOD_OER (0xa00 + 16) /* Output enable register */
207 #define PIOD_ODR (0xa00 + 20) /* Output disable register */
208 #define PIOD_OSR (0xa00 + 24) /* Output status register */
209 #define PIOD_IFER (0xa00 + 32) /* Input filter enable register */
210 #define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */
211 #define PIOD_IFSR (0xa00 + 40) /* Input filter status register */
212 #define PIOD_SODR (0xa00 + 48) /* Set output data register */
213 #define PIOD_CODR (0xa00 + 52) /* Clear output data register */
214 #define PIOD_ODSR (0xa00 + 56) /* Output data status register */
215 #define PIOD_PDSR (0xa00 + 60) /* Pin data status register */
216 #define PIOD_IER (0xa00 + 64) /* Interrupt enable register */
217 #define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */
218 #define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */
219 #define PIOD_ISR (0xa00 + 76) /* Interrupt status register */
220 #define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */
221 #define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */
222 #define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */
223 #define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */
224 #define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */
225 #define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */
226 #define PIOD_ASR (0xa00 + 112) /* Select A register */
227 #define PIOD_BSR (0xa00 + 116) /* Select B register */
228 #define PIOD_ABSR (0xa00 + 120) /* AB Select status register */
229 #define PIOD_OWER (0xa00 + 160) /* Output Write enable register */
230 #define PIOD_OWDR (0xa00 + 164) /* Output write disable register */
231 #define PIOD_OWSR (0xa00 + 168) /* Output write status register */
237 #define AT91RM92_PIO_SIZE 0x200
238 #define AT91RM92_PIOA_BASE 0xffff400
239 #define AT91RM92_PIOA_SIZE AT91RM92_PIO_SIZE
240 #define AT91RM92_PIOB_BASE 0xffff600
241 #define AT91RM92_PIOB_SIZE AT91RM92_PIO_SIZE
242 #define AT91RM92_PIOC_BASE 0xffff800
243 #define AT91RM92_PIOC_SIZE AT91RM92_PIO_SIZE
244 #define AT91RM92_PIOD_BASE 0xffffa00
245 #define AT91RM92_PIOD_SIZE AT91RM92_PIO_SIZE
250 #define AT91RM92_PMC_BASE 0xffffc00
251 #define AT91RM92_PMC_SIZE 0x100
256 * 1: System peripheral (System timer, RTC, DBGU)
257 * 2: PIO Controller A
258 * 3: PIO Controller B
259 * 4: PIO Controller C
260 * 5: PIO Controller D
266 * 11: USB device port
267 * 12: Two-wirte interface
272 * 17: Timer Counter 0
273 * 18: Timer Counter 1
274 * 19: Timer Counter 2
275 * 20: Timer Counter 3
276 * 21: Timer Counter 4
277 * 22: Timer Counter 6
289 #define AT91RM92_IRQ_SYSTEM 1
290 #define AT91RM92_IRQ_PIOA 2
291 #define AT91RM92_IRQ_PIOB 3
292 #define AT91RM92_IRQ_PIOC 4
293 #define AT91RM92_IRQ_PIOD 5
294 #define AT91RM92_IRQ_USART0 6
295 #define AT91RM92_IRQ_USART1 7
296 #define AT91RM92_IRQ_USART2 8
297 #define AT91RM92_IRQ_USART3 9
298 #define AT91RM92_IRQ_MCI 10
299 #define AT91RM92_IRQ_UDP 11
300 #define AT91RM92_IRQ_TWI 12
301 #define AT91RM92_IRQ_SPI 13
302 #define AT91RM92_IRQ_SSC0 14
303 #define AT91RM92_IRQ_SSC1 15
304 #define AT91RM92_IRQ_SSC2 16
305 #define AT91RM92_IRQ_TC0 17,18,19
306 #define AT91RM92_IRQ_TC0C0 17
307 #define AT91RM92_IRQ_TC0C1 18
308 #define AT91RM92_IRQ_TC0C2 19
309 #define AT91RM92_IRQ_TC1 20,21,22
310 #define AT91RM92_IRQ_TC1C1 20
311 #define AT91RM92_IRQ_TC1C2 21
312 #define AT91RM92_IRQ_TC1C3 22
313 #define AT91RM92_IRQ_UHP 23
314 #define AT91RM92_IRQ_EMAC 24
315 #define AT91RM92_IRQ_AIC_IRQ0 25
316 #define AT91RM92_IRQ_AIC_IRQ1 26
317 #define AT91RM92_IRQ_AIC_IRQ2 27
318 #define AT91RM92_IRQ_AIC_IRQ3 28
319 #define AT91RM92_IRQ_AIC_IRQ4 29
320 #define AT91RM92_IRQ_AIC_IRQ5 30
321 #define AT91RM92_IRQ_AIC_IRQ6 31
324 #define AT91RM92_IRQ_DBGU AT91RM92_IRQ_SYSTEM
325 #define AT91RM92_IRQ_PMC AT91RM92_IRQ_SYSTEM
326 #define AT91RM92_IRQ_ST AT91RM92_IRQ_SYSTEM
327 #define AT91RM92_IRQ_RTC AT91RM92_IRQ_SYSTEM
328 #define AT91RM92_IRQ_MC AT91RM92_IRQ_SYSTEM
329 #define AT91RM92_IRQ_OHCI AT91RM92_IRQ_UHP
330 #define AT91RM92_IRQ_AIC -1
331 #define AT91RM92_IRQ_CF -1
335 #define AT91RM92_AIC_BASE 0xffff000
336 #define AT91RM92_AIC_SIZE 0x200
339 #define AT91RM92_DBGU_BASE 0xffff200
340 #define AT91RM92_DBGU_SIZE 0x200
342 #define AT91RM92_RTC_BASE 0xffffe00
343 #define AT91RM92_RTC_SIZE 0x100
345 #define AT91RM92_MC_BASE 0xfffff00
346 #define AT91RM92_MC_SIZE 0x100
348 #define AT91RM92_ST_BASE 0xffffd00
349 #define AT91RM92_ST_SIZE 0x100
351 #define AT91RM92_SPI_BASE 0xffe0000
352 #define AT91RM92_SPI_SIZE 0x4000
353 #define AT91RM92_SPI_PDC 0xffe0100
355 #define AT91RM92_SSC_SIZE 0x4000
356 #define AT91RM92_SSC0_BASE 0xffd0000
357 #define AT91RM92_SSC0_PDC 0xffd0100
358 #define AT91RM92_SSC0_SIZE AT91RM92_SSC_SIZE
360 #define AT91RM92_SSC1_BASE 0xffd4000
361 #define AT91RM92_SSC1_PDC 0xffd4100
362 #define AT91RM92_SSC1_SIZE AT91RM92_SSC_SIZE
364 #define AT91RM92_SSC2_BASE 0xffd8000
365 #define AT91RM92_SSC2_PDC 0xffd8100
366 #define AT91RM92_SSC2_SIZE AT91RM92_SSC_SIZE
368 #define AT91RM92_EMAC_BASE 0xffbc000
369 #define AT91RM92_EMAC_SIZE 0x4000
371 #define AT91RM92_TWI_BASE 0xffb8000
372 #define AT91RM92_TWI_SIZE 0x4000
374 #define AT91RM92_MCI_BASE 0xffb4000
375 #define AT91RM92_MCI_PDC 0xffb4100
376 #define AT91RM92_MCI_SIZE 0x4000
378 #define AT91RM92_UDP_BASE 0xffb0000
379 #define AT91RM92_UDP_SIZE 0x4000
381 #define AT91RM92_TC_SIZE 0x4000
382 #define AT91RM92_TC0_BASE 0xffa0000
383 #define AT91RM92_TC0_SIZE AT91RM92_TC_SIZE
384 #define AT91RM92_TC0C0_BASE 0xffa0000
385 #define AT91RM92_TC0C1_BASE 0xffa0040
386 #define AT91RM92_TC0C2_BASE 0xffa0080
388 #define AT91RM92_TC1_BASE 0xffa4000
389 #define AT91RM92_TC1_SIZE AT91RM92_TC_SIZE
390 #define AT91RM92_TC1C0_BASE 0xffa4000
391 #define AT91RM92_TC1C1_BASE 0xffa4040
392 #define AT91RM92_TC1C2_BASE 0xffa4080
394 /* XXX Needs to be carfully coordinated with
395 * other * soc's so phyical and vm address
396 * mapping are unique. XXX
398 #define AT91RM92_OHCI_BASE 0xdfe00000
399 #define AT91RM92_OHCI_PA_BASE 0x00300000
400 #define AT91RM92_OHCI_SIZE 0x00100000
402 #define AT91RM92_CF_BASE 0xdfd00000
403 #define AT91RM92_CF_PA_BASE 0x51400000
404 #define AT91RM92_CF_SIZE 0x00100000
406 #ifndef AT91C_MASTER_CLOCK
407 #define AT91C_MASTER_CLOCK 60000000
412 #define AT91RM92_SDRAMC_BASE 0xfffff90
413 #define AT91RM92_SDRAMC_MR 0x00
414 #define AT91RM92_SDRAMC_MR_MODE_NORMAL 0
415 #define AT91RM92_SDRAMC_MR_MODE_NOP 1
416 #define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2
417 #define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
418 #define AT91RM92_SDRAMC_MR_MODE_REFRESH 4
419 #define AT91RM92_SDRAMC_MR_DBW_16 0x10
420 #define AT91RM92_SDRAMC_TR 0x04
421 #define AT91RM92_SDRAMC_CR 0x08
422 #define AT91RM92_SDRAMC_CR_NC_8 0x0
423 #define AT91RM92_SDRAMC_CR_NC_9 0x1
424 #define AT91RM92_SDRAMC_CR_NC_10 0x2
425 #define AT91RM92_SDRAMC_CR_NC_11 0x3
426 #define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003
427 #define AT91RM92_SDRAMC_CR_NR_11 0x0
428 #define AT91RM92_SDRAMC_CR_NR_12 0x4
429 #define AT91RM92_SDRAMC_CR_NR_13 0x8
430 #define AT91RM92_SDRAMC_CR_NR_RES 0xc
431 #define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c
432 #define AT91RM92_SDRAMC_CR_NB_2 0x00
433 #define AT91RM92_SDRAMC_CR_NB_4 0x10
434 #define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010
435 #define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060
436 #define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780
437 #define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800
438 #define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000
439 #define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000
440 #define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000
441 #define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000
442 #define AT91RM92_SDRAMC_SRR 0x0c
443 #define AT91RM92_SDRAMC_LPR 0x10
444 #define AT91RM92_SDRAMC_IER 0x14
445 #define AT91RM92_SDRAMC_IDR 0x18
446 #define AT91RM92_SDRAMC_IMR 0x1c
447 #define AT91RM92_SDRAMC_ISR 0x20
448 #define AT91RM92_SDRAMC_IER_RES 0x1
450 #endif /* AT91RM92REG_H_ */