2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
3 * Copyright (c) 2010 Greg Ansley. All rights reserved.
4 * Copyright (c) 2012 M. Warener Losh. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef AT91SAM9X5REG_H_
31 #define AT91SAM9X5REG_H_
33 #ifndef AT91SAM9X25_MASTER_CLOCK
34 #define AT91SAM9X25_MASTER_CLOCK ((18432000 * 43)/6)
37 /* Chip Specific limits */
38 #define SAM9X25_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
39 #define SAM9X25_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
40 #define SAM9X25_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
41 #define SAM9X25_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
42 #define SAM9X25_PLL_A_MUL_SHIFT 16
43 #define SAM9X25_PLL_A_MUL_MASK 0xFF
44 #define SAM9X25_PLL_A_DIV_SHIFT 0
45 #define SAM9X25_PLL_A_DIV_MASK 0xFF
47 #define SAM9X25_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */
48 #define SAM9X25_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */
49 #define SAM9X25_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */
50 #define SAM9X25_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */
51 #define SAM9X25_PLL_B_MUL_SHIFT 16
52 #define SAM9X25_PLL_B_MUL_MASK 0x3F
53 #define SAM9X25_PLL_B_DIV_SHIFT 0
54 #define SAM9X25_PLL_B_DIV_MASK 0xFF
57 * Memory map, from datasheet :
58 * 0x00000000 - 0x0ffffffff : Internal Memories
59 * 0x10000000 - 0x1ffffffff : Chip Select 0
60 * 0x20000000 - 0x2ffffffff : Chip Select 1 DDR2/LPDDR/SDR/LPSDR
61 * 0x30000000 - 0x3ffffffff : Chip Select 2
62 * 0x40000000 - 0x4ffffffff : Chip Select 3 NAND Flash
63 * 0x50000000 - 0x5ffffffff : Chip Select 4
64 * 0x60000000 - 0x6ffffffff : Chip Select 5
65 * 0x70000000 - 0xeffffffff : Undefined (Abort)
66 * 0xf0000000 - 0xfffffffff : Peripherals
69 #define AT91_CHIPSELECT_0 0x10000000
70 #define AT91_CHIPSELECT_1 0x20000000
71 #define AT91_CHIPSELECT_2 0x30000000
72 #define AT91_CHIPSELECT_3 0x40000000
73 #define AT91_CHIPSELECT_4 0x50000000
74 #define AT91_CHIPSELECT_5 0x60000000
76 #define AT91SAM9X25_EMAC_SIZE 0x4000
77 #define AT91SAM9X25_EMAC0_BASE 0x802c000
78 #define AT91SAM9X25_EMAC0_SIZE AT91SAM9X25_EMAC_SIZE
79 #define AT91SAM9X25_EMAC1_BASE 0x8030000
80 #define AT91SAM9X25_EMAC1_SIZE AT91SAM9X25_EMAC_SIZE
82 #define AT91SAM9X25_RSTC_BASE 0xffffe00
83 #define AT91SAM9X25_RSTC_SIZE 0x10
87 #define AT91SAM9X25_USART_SIZE 0x4000
88 #define AT91SAM9X25_USART0_BASE 0x801c000
89 #define AT91SAM9X25_USART0_PDC 0x801c100
90 #define AT91SAM9X25_USART0_SIZE AT91SAM9X25_USART_SIZE
91 #define AT91SAM9X25_USART1_BASE 0x8020000
92 #define AT91SAM9X25_USART1_PDC 0x8020100
93 #define AT91SAM9X25_USART1_SIZE AT91SAM9X25_USART_SIZE
94 #define AT91SAM9X25_USART2_BASE 0x8024000
95 #define AT91SAM9X25_USART2_PDC 0x8024100
96 #define AT91SAM9X25_USART2_SIZE AT91SAM9X25_USART_SIZE
97 #define AT91SAM9X25_USART3_BASE 0x8028000
98 #define AT91SAM9X25_USART3_PDC 0x8028100
99 #define AT91SAM9X25_USART3_SIZE AT91SAM9X25_USART_SIZE
102 #define AT91SAM9X25_TC0_BASE 0x8008000
103 #define AT91SAM9X25_TC0_SIZE 0x4000
104 #define AT91SAM9X25_TC0C0_BASE 0x8008000
105 #define AT91SAM9X25_TC0C1_BASE 0x8008040
106 #define AT91SAM9X25_TC0C2_BASE 0x8008080
108 #define AT91SAM9X25_TC1_BASE 0x800c000
109 #define AT91SAM9X25_TC1_SIZE 0x4000
113 #define AT91SAM9X25_SPI0_BASE 0x0000000
115 #define AT91SAM9X25_SPI0_SIZE 0x4000
117 #define AT91SAM9X25_SPI1_BASE 0x0004000
118 #define AT91SAM9X25_SPI1_SIZE 0x4000
120 /* System Registers */
121 #define AT91SAM9X25_SYS_BASE 0xffff000
122 #define AT91SAM9X25_SYS_SIZE 0x1000
124 #define AT91SAM9X25_MATRIX_BASE 0xfffde00
125 #define AT91SAM9X25_MATRIX_SIZE 0x200
127 #define AT91SAM9X25_DBGU_BASE 0xffff200
128 #define AT91SAM9X25_DBGU_SIZE 0x200
133 #define AT91SAM9X25_PIOA_BASE 0xffff400
134 #define AT91SAM9X25_PIOA_SIZE 0x200
135 #define AT91SAM9X25_PIOB_BASE 0xffff600
136 #define AT91SAM9X25_PIOB_SIZE 0x200
137 #define AT91SAM9X25_PIOC_BASE 0xffff800
138 #define AT91SAM9X25_PIOC_SIZE 0x200
139 #define AT91SAM9X25_PIOD_BASE 0xffffa00
140 #define AT91SAM9X25_PIOD_SIZE 0x200
142 #define AT91RM92_PMC_BASE 0xffffc00
143 #define AT91RM92_PMC_SIZE 0x100
146 * 1: System peripheral (System timer, RTC, DBGU)
147 * 2: PIO Controller A,B
148 * 3: PIO Controller C,D
154 * 9: Two-wirte interface
155 * 10: Two-wirte interface
156 * 11: Two-wirte interface
157 * 12: HSMCI Interface
162 * 17: Timer Counter 0,1
167 * 22: UHPHS - USB Host controller
168 * 23: UDPHS - USB Device Controller
170 * 25: LCD controller or Image Sensor Interface
179 #define AT91SAM9X25_IRQ_AIC 0
180 #define AT91SAM9X25_IRQ_SYSTEM 1
181 #define AT91SAM9X25_IRQ_PIOAB 2
182 #define AT91SAM9X25_IRQ_PIOCD 3
183 #define AT91SAM9X25_IRQ_SMD 4
184 #define AT91SAM9X25_IRQ_USART0 5
185 #define AT91SAM9X25_IRQ_USART1 6
186 #define AT91SAM9X25_IRQ_USART2 7
187 #define AT91SAM9X25_IRQ_USART3 8
188 #define AT91SAM9X25_IRQ_TWI0 9
189 #define AT91SAM9X25_IRQ_TWI1 10
190 #define AT91SAM9X25_IRQ_TWI2 11
191 #define AT91SAM9X25_IRQ_HSMCI0 12
192 #define AT91SAM9X25_IRQ_SPI0 13
193 #define AT91SAM9X25_IRQ_SPI1 14
194 #define AT91SAM9X25_IRQ_UART0 15
195 #define AT91SAM9X25_IRQ_UART1 16
196 #define AT91SAM9X25_IRQ_TC01 17
197 #define AT91SAM9X25_IRQ_PWM 18
198 #define AT91SAM9X25_IRQ_ADC 19
199 #define AT91SAM9X25_IRQ_DMAC0 20
200 #define AT91SAM9X25_IRQ_DMAC1 21
201 #define AT91SAM9X25_IRQ_UHPHS 22
202 #define AT91SAM9X25_IRQ_UDPHS 23
203 #define AT91SAM9X25_IRQ_EMAC0 24
204 #define AT91SAM9X25_IRQ_HSMCI1 26
205 #define AT91SAM9X25_IRQ_EMAC1 27
206 #define AT91SAM9X25_IRQ_SSC 28
207 #define AT91SAM9X25_IRQ_CAN0 29
208 #define AT91SAM9X25_IRQ_CAN1 30
209 #define AT91SAM9X25_IRQ_AICBASE 31
212 #define AT91SAM9X25_IRQ_DBGU AT91SAM9X25_IRQ_SYSTEM
213 #define AT91SAM9X25_IRQ_PMC AT91SAM9X25_IRQ_SYSTEM
214 #define AT91SAM9X25_IRQ_WDT AT91SAM9X25_IRQ_SYSTEM
215 #define AT91SAM9X25_IRQ_PIT AT91SAM9X25_IRQ_SYSTEM
216 #define AT91SAM9X25_IRQ_RSTC AT91SAM9X25_IRQ_SYSTEM
217 #define AT91SAM9X25_IRQ_OHCI AT91SAM9X25_IRQ_UHPHS
218 #define AT91SAM9X25_IRQ_EHCI AT91SAM9X25_IRQ_UHPHS
219 #define AT91SAM9X25_IRQ_PIOA AT91SAM9X25_IRQ_PIOAB
220 #define AT91SAM9X25_IRQ_PIOB AT91SAM9X25_IRQ_PIOAB
221 #define AT91SAM9X25_IRQ_PIOC AT91SAM9X25_IRQ_PIOCD
222 #define AT91SAM9X25_IRQ_PIOD AT91SAM9X25_IRQ_PIOCD
223 #define AT91SAM9X25_IRQ_NAND (-1)
225 #define AT91SAM9X25_AIC_BASE 0xffff000
226 #define AT91SAM9X25_AIC_SIZE 0x200
230 #define AT91SAM9X25_WDT_BASE 0xffffd40
231 #define AT91SAM9X25_WDT_SIZE 0x10
233 #define AT91SAM9X25_PIT_BASE 0xffffd30
234 #define AT91SAM9X25_PIT_SIZE 0x10
236 #define AT91SAM9X25_SMC_BASE 0xfffea00
237 #define AT91SAM9X25_SMC_SIZE 0x200
239 #define AT91SAM9X25_PMC_BASE 0xffffc00
240 #define AT91SAM9X25_PMC_SIZE 0x100
242 #define AT91SAM9X25_UDPHS_BASE 0x803c000
243 #define AT91SAM9X25_UDPHS_SIZE 0x4000
245 #define AT91SAM9X25_HSMCI_SIZE 0x4000
246 #define AT91SAM9X25_HSMCI0_BASE 0x0008000
247 #define AT91SAM9X25_HSMCI0_SIZE AT91SAM9X25_HSMCI_SIZE
248 #define AT91SAM9X25_HSMCI1_BASE 0x000c000
249 #define AT91SAM9X25_HSMCI1_SIZE AT91SAM9X25_HSMCI_SIZE
251 #define AT91SAM9X25_TWI_SIZE 0x4000
252 #define AT91SAM9X25_TWI0_BASE 0xffaC000
253 #define AT91SAM9X25_TWI0_SIZE AT91SAM9X25_TWI_SIZE
254 #define AT91SAM9X25_TWI1_BASE 0xffaC000
255 #define AT91SAM9X25_TWI1_SIZE AT91SAM9X25_TWI_SIZE
256 #define AT91SAM9X25_TWI2_BASE 0xffaC000
257 #define AT91SAM9X25_TWI2_SIZE AT91SAM9X25_TWI_SIZE
259 /* XXX Needs to be carfully coordinated with
260 * other * soc's so phyical and vm address
261 * mapping are unique. XXX
263 #define AT91SAM9X25_OHCI_BASE 0xdfc00000 /* SAME as 9c40 */
264 #define AT91SAM9X25_OHCI_PA_BASE 0x00600000
265 #define AT91SAM9X25_OHCI_SIZE 0x00100000
267 #define AT91SAM9X25_EHCI_BASE 0xdfd00000
268 #define AT91SAM9X25_EHCI_PA_BASE 0x00700000
269 #define AT91SAM9X25_EHCI_SIZE 0x00100000
271 #define AT91SAM9X25_NAND_BASE 0xe0000000
272 #define AT91SAM9X25_NAND_PA_BASE 0x40000000
273 #define AT91SAM9X25_NAND_SIZE 0x10000000
277 #define AT91SAM9X25_SDRAMC_BASE 0xfffea00 /* SAME as SMC? */
278 #define AT91SAM9X25_SDRAMC_MR 0x00
279 #define AT91SAM9X25_SDRAMC_MR_MODE_NORMAL 0
280 #define AT91SAM9X25_SDRAMC_MR_MODE_NOP 1
281 #define AT91SAM9X25_SDRAMC_MR_MODE_PRECHARGE 2
282 #define AT91SAM9X25_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
283 #define AT91SAM9X25_SDRAMC_MR_MODE_REFRESH 4
284 #define AT91SAM9X25_SDRAMC_TR 0x04
285 #define AT91SAM9X25_SDRAMC_CR 0x08
286 #define AT91SAM9X25_SDRAMC_CR_NC_8 0x0
287 #define AT91SAM9X25_SDRAMC_CR_NC_9 0x1
288 #define AT91SAM9X25_SDRAMC_CR_NC_10 0x2
289 #define AT91SAM9X25_SDRAMC_CR_NC_11 0x3
290 #define AT91SAM9X25_SDRAMC_CR_NC_MASK 0x00000003
291 #define AT91SAM9X25_SDRAMC_CR_NR_11 0x0
292 #define AT91SAM9X25_SDRAMC_CR_NR_12 0x4
293 #define AT91SAM9X25_SDRAMC_CR_NR_13 0x8
294 #define AT91SAM9X25_SDRAMC_CR_NR_RES 0xc
295 #define AT91SAM9X25_SDRAMC_CR_NR_MASK 0x0000000c
296 #define AT91SAM9X25_SDRAMC_CR_NB_2 0x00
297 #define AT91SAM9X25_SDRAMC_CR_NB_4 0x10
298 #define AT91SAM9X25_SDRAMC_CR_DBW_16 0x80
299 #define AT91SAM9X25_SDRAMC_CR_NB_MASK 0x00000010
300 #define AT91SAM9X25_SDRAMC_CR_NCAS_MASK 0x00000060
301 #define AT91SAM9X25_SDRAMC_CR_TWR_MASK 0x00000780
302 #define AT91SAM9X25_SDRAMC_CR_TRC_MASK 0x00007800
303 #define AT91SAM9X25_SDRAMC_CR_TRP_MASK 0x00078000
304 #define AT91SAM9X25_SDRAMC_CR_TRCD_MASK 0x00780000
305 #define AT91SAM9X25_SDRAMC_CR_TRAS_MASK 0x07800000
306 #define AT91SAM9X25_SDRAMC_CR_TXSR_MASK 0x78000000
307 #define AT91SAM9X25_SDRAMC_HSR 0x0c
308 #define AT91SAM9X25_SDRAMC_LPR 0x10
309 #define AT91SAM9X25_SDRAMC_IER 0x14
310 #define AT91SAM9X25_SDRAMC_IDR 0x18
311 #define AT91SAM9X25_SDRAMC_IMR 0x1c
312 #define AT91SAM9X25_SDRAMC_ISR 0x20
313 #define AT91SAM9X25_SDRAMC_MDR 0x24
315 #endif /* AT91SAM9X5REG_H_*/