1 /* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */
3 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved.
4 * Written by Hashimoto Kenichi for Genetec Corporation.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
29 * Copyright (c) 2012, 2013 The FreeBSD Foundation
30 * All rights reserved.
32 * Portions of this software were developed by Oleksandr Rybalko
33 * under sponsorship from the FreeBSD Foundation.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 #ifndef _ARM_IMX_IMX51_IPUV3REG_H
60 #define _ARM_IMX_IMX51_IPUV3REG_H
62 /* register offset address */
68 #define IPU_CM_CONF 0x00000000
69 #define CM_CONF_CSI_SEL 0x80000000
70 #define CM_CONF_IC_INPUT 0x40000000
71 #define CM_CONF_CSI1_DATA_SOURCE 0x20000000
72 #define CM_CONF_CSI0_DATA_SOURCE 0x10000000
73 #define CM_CONF_VDI_DMFC_SYNC 0x08000000
74 #define CM_CONF_IC_DMFC_SYNC 0x04000000
75 #define CM_CONF_IC_DMFC_SEL 0x02000000
76 #define CM_CONF_ISP_DOUBLE_FLOW 0x01000000
77 #define CM_CONF_IDMAC_DISABLE 0x00400000
78 #define CM_CONF_IPU_DIAGBUS_ON 0x00200000
79 #define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000
80 #define CM_CONF_VDI_EN 0x00001000
81 #define CM_CONF_SISG_EN 0x00000800
82 #define CM_CONF_DMFC_EN 0x00000400
83 #define CM_CONF_DC_EN 0x00000200
84 #define CM_CONF_SMFC_EN 0x00000100
85 #define CM_CONF_DI1_EN 0x00000080
86 #define CM_CONF_DI0_EN 0x00000040
87 #define CM_CONF_DP_EN 0x00000020
88 #define CM_CONF_ISP_EN 0x00000010
89 #define CM_CONF_IRT_EN 0x00000008
90 #define CM_CONF_IC_EN 0x00000004
91 #define CM_CONF_CSI1_EN 0x00000002
92 #define CM_CONF_CSI0_EN 0x00000001
93 #define IPU_SISG_CTRL0 0x00000004
94 #define IPU_SISG_CTRL1 0x00000008
95 #define IPU_CM_INT_CTRL_1 0x0000003c
96 #define IPU_CM_INT_CTRL_2 0x00000040
97 #define IPU_CM_INT_CTRL_3 0x00000044
98 #define IPU_CM_INT_CTRL_4 0x00000048
99 #define IPU_CM_INT_CTRL_5 0x0000004c
100 #define IPU_CM_INT_CTRL_6 0x00000050
101 #define IPU_CM_INT_CTRL_7 0x00000054
102 #define IPU_CM_INT_CTRL_8 0x00000058
103 #define IPU_CM_INT_CTRL_9 0x0000005c
104 #define IPU_CM_INT_CTRL_10 0x00000060
105 #define IPU_CM_INT_CTRL_11 0x00000064
106 #define IPU_CM_INT_CTRL_12 0x00000068
107 #define IPU_CM_INT_CTRL_13 0x0000006c
108 #define IPU_CM_INT_CTRL_14 0x00000070
109 #define IPU_CM_INT_CTRL_15 0x00000074
110 #define IPU_CM_SDMA_EVENT_1 0x00000078
111 #define IPU_CM_SDMA_EVENT_2 0x0000007c
112 #define IPU_CM_SDMA_EVENT_3 0x00000080
113 #define IPU_CM_SDMA_EVENT_4 0x00000084
114 #define IPU_CM_SDMA_EVENT_7 0x00000088
115 #define IPU_CM_SDMA_EVENT_8 0x0000008c
116 #define IPU_CM_SDMA_EVENT_11 0x00000090
117 #define IPU_CM_SDMA_EVENT_12 0x00000094
118 #define IPU_CM_SDMA_EVENT_13 0x00000098
119 #define IPU_CM_SDMA_EVENT_14 0x0000009c
120 #define IPU_CM_SRM_PRI1 0x000000a0
121 #define IPU_CM_SRM_PRI2 0x000000a4
122 #define IPU_CM_FS_PROC_FLOW1 0x000000a8
123 #define IPU_CM_FS_PROC_FLOW2 0x000000ac
124 #define IPU_CM_FS_PROC_FLOW3 0x000000b0
125 #define IPU_CM_FS_DISP_FLOW1 0x000000b4
126 #define IPU_CM_FS_DISP_FLOW2 0x000000b8
127 #define IPU_CM_SKIP 0x000000bc
128 #define IPU_CM_DISP_ALT_CONF 0x000000c0
129 #define IPU_CM_DISP_GEN 0x000000c4
130 #define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000
131 #define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000
132 #define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000
133 #define CM_DISP_GEN_MCU_T_SHIFT 18
134 #define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT)
135 #define IPU_CM_DISP_ALT1 0x000000c8
136 #define IPU_CM_DISP_ALT2 0x000000cc
137 #define IPU_CM_DISP_ALT3 0x000000d0
138 #define IPU_CM_DISP_ALT4 0x000000d4
139 #define IPU_CM_SNOOP 0x000000d8
140 #define IPU_CM_MEM_RST 0x000000dc
141 #define CM_MEM_START 0x80000000
142 #define CM_MEM_EN 0x007fffff
143 #define IPU_CM_PM 0x000000e0
144 #define IPU_CM_GPR 0x000000e4
145 #define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000
146 #define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000
147 #define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000
148 #define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000
149 #define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000
150 #define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000
151 #define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000
152 #define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000
153 #define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000
154 #define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000
155 #define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000
156 #define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000
157 #define CM_GPR_IPU_GP(n) __BIT((n))
158 #define IPU_CM_CH_DB_MODE_SEL_0 0x00000150
159 #define IPU_CM_CH_DB_MODE_SEL_1 0x00000154
160 #define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168
161 #define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c
162 #define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178
163 #define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c
164 #define IPU_CM_INT_STAT_1 0x00000200
165 #define IPU_CM_INT_STAT_2 0x00000204
166 #define IPU_CM_INT_STAT_3 0x00000208
167 #define IPU_CM_INT_STAT_4 0x0000020c
168 #define IPU_CM_INT_STAT_5 0x00000210
169 #define IPU_CM_INT_STAT_6 0x00000214
170 #define IPU_CM_INT_STAT_7 0x00000218
171 #define IPU_CM_INT_STAT_8 0x0000021c
172 #define IPU_CM_INT_STAT_9 0x00000220
173 #define IPU_CM_INT_STAT_10 0x00000224
174 #define IPU_CM_INT_STAT_11 0x00000228
175 #define IPU_CM_INT_STAT_12 0x0000022c
176 #define IPU_CM_INT_STAT_13 0x00000230
177 #define IPU_CM_INT_STAT_14 0x00000234
178 #define IPU_CM_INT_STAT_15 0x00000238
179 #define IPU_CM_CUR_BUF_0 0x0000023c
180 #define IPU_CM_CUR_BUF_1 0x00000240
181 #define IPU_CM_ALT_CUR_BUF_0 0x00000244
182 #define IPU_CM_ALT_CUR_BUF_1 0x00000248
183 #define IPU_CM_SRM_STAT 0x0000024c
184 #define IPU_CM_PROC_TASKS_STAT 0x00000250
185 #define IPU_CM_DISP_TASKS_STAT 0x00000254
186 #define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258
187 #define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c
188 #define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260
189 #define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264
190 #define IPU_CM_CH_BUF0_RDY0 0x00000268
191 #define IPU_CM_CH_BUF0_RDY1 0x0000026c
192 #define IPU_CM_CH_BUF1_RDY0 0x00000270
193 #define IPU_CM_CH_BUF1_RDY1 0x00000274
194 #define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278
195 #define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c
196 #define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280
197 #define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284
198 #define IPU_CM_CH_BUF2_RDY0 0x00000288
199 #define IPU_CM_CH_BUF2_RDY1 0x0000028c
203 * Image DMA Controller
205 #define IPU_IDMAC_CONF 0x00000000
206 #define IPU_IDMAC_CH_EN_1 0x00000004
207 #define IPU_IDMAC_CH_EN_2 0x00000008
208 #define IPU_IDMAC_SEP_ALPHA 0x0000000c
209 #define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010
210 #define IPU_IDMAC_CH_PRI_1 0x00000014
211 #define IPU_IDMAC_CH_PRI_2 0x00000018
212 #define IPU_IDMAC_WM_EN_1 0x0000001c
213 #define IPU_IDMAC_WM_EN_2 0x00000020
214 #define IPU_IDMAC_LOCK_EN_1 0x00000024
215 #define IPU_IDMAC_LOCK_EN_2 0x00000028
216 #define IPU_IDMAC_SUB_ADDR_0 0x0000002c
217 #define IPU_IDMAC_SUB_ADDR_1 0x00000030
218 #define IPU_IDMAC_SUB_ADDR_2 0x00000034
219 #define IPU_IDMAC_SUB_ADDR_3 0x00000038
220 #define IPU_IDMAC_SUB_ADDR_4 0x0000003c
221 #define IPU_IDMAC_BNDM_EN_1 0x00000040
222 #define IPU_IDMAC_BNDM_EN_2 0x00000044
223 #define IPU_IDMAC_SC_CORD 0x00000048
224 #define IPU_IDMAC_SC_CORD1 0x0000004c
225 #define IPU_IDMAC_CH_BUSY_1 0x00000100
226 #define IPU_IDMAC_CH_BUSY_2 0x00000104
228 #define CH_PANNEL_BG 23
229 #define CH_PANNEL_FG 27
235 #define IPU_DP_DEBUG_CNT 0x000000bc
236 #define IPU_DP_DEBUG_STAT 0x000000c0
242 #define IPU_IC_CONF 0x00000000
243 #define IPU_IC_PRP_ENC_RSC 0x00000004
244 #define IPU_IC_PRP_VF_RSC 0x00000008
245 #define IPU_IC_PP_RSC 0x0000000c
246 #define IPU_IC_CMBP_1 0x00000010
247 #define IPU_IC_CMBP_2 0x00000014
248 #define IPU_IC_IDMAC_1 0x00000018
249 #define IPU_IC_IDMAC_2 0x0000001c
250 #define IPU_IC_IDMAC_3 0x00000020
251 #define IPU_IC_IDMAC_4 0x00000024
255 * Camera Sensor Interface
257 #define IPU_CSI0_SENS_CONF 0x00000000
258 #define IPU_CSI0_SENS_FRM_SIZE 0x00000004
259 #define IPU_CSI0_ACT_FRM_SIZE 0x00000008
260 #define IPU_CSI0_OUT_FRM_CTRL 0x0000000c
261 #define IPU_CSI0_TST_CTRL 0x00000010
262 #define IPU_CSI0_CCIR_CODE_1 0x00000014
263 #define IPU_CSI0_CCIR_CODE_2 0x00000018
264 #define IPU_CSI0_CCIR_CODE_3 0x0000001c
265 #define IPU_CSI0_DI 0x00000020
266 #define IPU_CSI0_SKIP 0x00000024
267 #define IPU_CSI0_CPD_CTRL 0x00000028
268 #define IPU_CSI0_CPD_OFFSET1 0x000000ec
269 #define IPU_CSI0_CPD_OFFSET2 0x000000f0
271 #define IPU_CSI1_SENS_CONF 0x00000000
272 #define IPU_CSI1_SENS_FRM_SIZE 0x00000004
273 #define IPU_CSI1_ACT_FRM_SIZE 0x00000008
274 #define IPU_CSI1_OUT_FRM_CTRL 0x0000000c
275 #define IPU_CSI1_TST_CTRL 0x00000010
276 #define IPU_CSI1_CCIR_CODE_1 0x00000014
277 #define IPU_CSI1_CCIR_CODE_2 0x00000018
278 #define IPU_CSI1_CCIR_CODE_3 0x0000001c
279 #define IPU_CSI1_DI 0x00000020
280 #define IPU_CSI1_SKIP 0x00000024
281 #define IPU_CSI1_CPD_CTRL 0x00000028
282 #define IPU_CSI1_CPD_OFFSET1 0x000000ec
283 #define IPU_CSI1_CPD_OFFSET2 0x000000f0
289 #define IPU_DI_GENERAL 0x00000000
290 #define DI_GENERAL_DISP_Y_SEL 0x70000000
291 #define DI_GENERAL_CLOCK_STOP_MODE 0x0f000000
292 #define DI_GENERAL_DISP_CLOCK_INIT 0x00800000
293 #define DI_GENERAL_MASK_SEL 0x00400000
294 #define DI_GENERAL_VSYNC_EXT 0x00200000
295 #define DI_GENERAL_CLK_EXT 0x00100000
296 #define DI_GENERAL_WATCHDOG_MODE 0x000c0000
297 #define DI_GENERAL_POLARITY_DISP_CLK 0x00020000
298 #define DI_GENERAL_SYNC_COUNT_SEL 0x0000f000
299 #define DI_GENERAL_ERR_TREATMENT 0x00000800
300 #define DI_GENERAL_ERM_VSYNC_SEL 0x00000400
301 #define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8))
302 #define DI_GENERAL_POLARITY(n) (1 << ((n) - 1))
304 #define IPU_DI_BS_CLKGEN0 0x00000004
305 #define DI_BS_CLKGEN0_OFFSET_SHIFT 16
306 #define IPU_DI_BS_CLKGEN1 0x00000008
307 #define DI_BS_CLKGEN1_DOWN_SHIFT 16
308 #define DI_BS_CLKGEN1_UP_SHIFT 0
309 #define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4)
310 #define DI_SW_GEN0_RUN_VAL 0x7ff80000
311 #define DI_SW_GEN0_RUN_RESOL 0x00070000
312 #define DI_SW_GEN0_OFFSET_VAL 0x00007ff8
313 #define DI_SW_GEN0_OFFSET_RESOL 0x00000007
314 #define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \
315 (((run_val) << 19) | ((run_resol) << 16) | \
316 ((offset_val) << 3) | (offset_resol))
317 #define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4)
318 #define DI_SW_GEN1_CNT_POL_GEN_EN 0x60000000
319 #define DI_SW_GEN1_CNT_AUTO_RELOAD 0x10000000
320 #define DI_SW_GEN1_CNT_CLR_SEL 0x0e000000
321 #define DI_SW_GEN1_CNT_DOWN 0x01ff0000
322 #define DI_SW_GEN1_CNT_POL_TRIG_SEL 0x00007000
323 #define DI_SW_GEN1_CNT_POL_CLR_SEL 0x00000e00
324 #define DI_SW_GEN1_CNT_UP 0x000001ff
325 #define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \
326 (((pol_gen_en) << 29) | ((auto_reload) << 28) | \
327 ((clr_sel) << 25) | \
328 ((down) << 16) | ((pol_trig_sel) << 12) | \
329 ((pol_clr_sel) << 9) | (up))
330 #define IPU_DI_SYNC_AS_GEN 0x00000054
331 #define DI_SYNC_AS_GEN_SYNC_START_EN 0x10000000
332 #define DI_SYNC_AS_GEN_VSYNC_SEL 0x0000e000
333 #define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13
334 #define DI_SYNC_AS_GEN_SYNC_STAR 0x00000fff
335 #define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4)
336 #define DI_DW_GEN_ACCESS_SIZE_SHIFT 24
337 #define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16
338 #define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2)
339 #define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \
340 DI_DW_GEN_PIN_SHIFT(n))
341 #define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30)
342 #define DI_DW_SET_DOWN_SHIFT 16
343 #define DI_DW_SET_UP_SHIFT 0
344 #define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4)
345 #define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16)
346 #define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n)))
347 #define IPU_DI_SER_CONF 0x0000015c
348 #define IPU_DI_SSC 0x00000160
349 #define IPU_DI_POL 0x00000164
350 #define DI_POL_DRDY_POLARITY_17 0x00000040
351 #define DI_POL_DRDY_POLARITY_16 0x00000020
352 #define DI_POL_DRDY_POLARITY_15 0x00000010
353 #define DI_POL_DRDY_POLARITY_14 0x00000008
354 #define DI_POL_DRDY_POLARITY_13 0x00000004
355 #define DI_POL_DRDY_POLARITY_12 0x00000002
356 #define DI_POL_DRDY_POLARITY_11 0x00000001
357 #define IPU_DI_AW0 0x00000168
358 #define IPU_DI_AW1 0x0000016c
359 #define IPU_DI_SCR_CONF 0x00000170
360 #define IPU_DI_STAT 0x00000174
364 * Sensor Multi FIFO Controller
366 #define IPU_SMFC_MAP 0x00000000
367 #define IPU_SMFC_WMC 0x00000004
368 #define IPU_SMFC_BS 0x00000008
374 #define IPU_DC_READ_CH_CONF 0x00000000
375 #define IPU_DC_READ_CH_ADDR 0x00000004
377 #define IPU_DC_RL0_CH_0 0x00000008
378 #define IPU_DC_RL1_CH_0 0x0000000c
379 #define IPU_DC_RL2_CH_0 0x00000010
380 #define IPU_DC_RL3_CH_0 0x00000014
381 #define IPU_DC_RL4_CH_0 0x00000018
382 #define IPU_DC_WR_CH_CONF_1 0x0000001c
383 #define IPU_DC_WR_CH_ADDR_1 0x00000020
384 #define IPU_DC_RL0_CH_1 0x00000024
385 #define IPU_DC_RL1_CH_1 0x00000028
386 #define IPU_DC_RL2_CH_1 0x0000002c
387 #define IPU_DC_RL3_CH_1 0x00000030
388 #define IPU_DC_RL4_CH_1 0x00000034
389 #define IPU_DC_WR_CH_CONF_2 0x00000038
390 #define IPU_DC_WR_CH_ADDR_2 0x0000003c
391 #define IPU_DC_RL0_CH_2 0x00000040
392 #define IPU_DC_RL1_CH_2 0x00000044
393 #define IPU_DC_RL2_CH_2 0x00000048
394 #define IPU_DC_RL3_CH_2 0x0000004c
395 #define IPU_DC_RL4_CH_2 0x00000050
396 #define IPU_DC_CMD_CH_CONF_3 0x00000054
397 #define IPU_DC_CMD_CH_CONF_4 0x00000058
398 #define IPU_DC_WR_CH_CONF_5 0x0000005c
399 #define IPU_DC_WR_CH_ADDR_5 0x00000060
400 #define IPU_DC_RL0_CH_5 0x00000064
401 #define IPU_DC_RL1_CH_5 0x00000068
402 #define IPU_DC_RL2_CH_5 0x0000006c
403 #define IPU_DC_RL3_CH_5 0x00000070
404 #define IPU_DC_RL4_CH_5 0x00000074
405 #define IPU_DC_WR_CH_CONF_6 0x00000078
406 #define IPU_DC_WR_CH_ADDR_6 0x0000007c
407 #define IPU_DC_RL0_CH_6 0x00000080
408 #define IPU_DC_RL1_CH_6 0x00000084
409 #define IPU_DC_RL2_CH_6 0x00000088
410 #define IPU_DC_RL3_CH_6 0x0000008c
411 #define IPU_DC_RL4_CH_6 0x00000090
412 #define IPU_DC_WR_CH_CONF1_8 0x00000094
413 #define IPU_DC_WR_CH_CONF2_8 0x00000098
414 #define IPU_DC_RL1_CH_8 0x0000009c
415 #define IPU_DC_RL2_CH_8 0x000000a0
416 #define IPU_DC_RL3_CH_8 0x000000a4
417 #define IPU_DC_RL4_CH_8 0x000000a8
418 #define IPU_DC_RL5_CH_8 0x000000ac
419 #define IPU_DC_RL6_CH_8 0x000000b0
420 #define IPU_DC_WR_CH_CONF1_9 0x000000b4
421 #define IPU_DC_WR_CH_CONF2_9 0x000000b8
422 #define IPU_DC_RL1_CH_9 0x000000bc
423 #define IPU_DC_RL2_CH_9 0x000000c0
424 #define IPU_DC_RL3_CH_9 0x000000c4
425 #define IPU_DC_RL4_CH_9 0x000000c8
426 #define IPU_DC_RL5_CH_9 0x000000cc
427 #define IPU_DC_RL6_CH_9 0x000000d0
429 #define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4)
430 #define DC_RL_CH_0 IPU_DC_RL0_CH_0
431 #define DC_RL_CH_1 IPU_DC_RL0_CH_1
432 #define DC_RL_CH_2 IPU_DC_RL0_CH_2
433 #define DC_RL_CH_5 IPU_DC_RL0_CH_5
434 #define DC_RL_CH_6 IPU_DC_RL0_CH_6
435 #define DC_RL_CH_8 IPU_DC_RL0_CH_8
437 #define DC_RL_EVT_NF 0
438 #define DC_RL_EVT_NL 1
439 #define DC_RL_EVT_EOF 2
440 #define DC_RL_EVT_NFIELD 3
441 #define DC_RL_EVT_EOL 4
442 #define DC_RL_EVT_EOFIELD 5
443 #define DC_RL_EVT_NEW_ADDR 6
444 #define DC_RL_EVT_NEW_CHAN 7
445 #define DC_RL_EVT_NEW_DATA 8
447 #define IPU_DC_GEN 0x000000d4
448 #define IPU_DC_DISP_CONF1_0 0x000000d8
449 #define IPU_DC_DISP_CONF1_1 0x000000dc
450 #define IPU_DC_DISP_CONF1_2 0x000000e0
451 #define IPU_DC_DISP_CONF1_3 0x000000e4
452 #define IPU_DC_DISP_CONF2_0 0x000000e8
453 #define IPU_DC_DISP_CONF2_1 0x000000ec
454 #define IPU_DC_DISP_CONF2_2 0x000000f0
455 #define IPU_DC_DISP_CONF2_3 0x000000f4
456 #define IPU_DC_DI0_CONF_1 0x000000f8
457 #define IPU_DC_DI0_CONF_2 0x000000fc
458 #define IPU_DC_DI1_CONF_1 0x00000100
459 #define IPU_DC_DI1_CONF_2 0x00000104
461 #define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4)
462 #define IPU_DC_MAP_CONF_0 0x00000108
463 #define IPU_DC_MAP_CONF_1 0x0000010c
464 #define IPU_DC_MAP_CONF_2 0x00000110
465 #define IPU_DC_MAP_CONF_3 0x00000114
466 #define IPU_DC_MAP_CONF_4 0x00000118
467 #define IPU_DC_MAP_CONF_5 0x0000011c
468 #define IPU_DC_MAP_CONF_6 0x00000120
469 #define IPU_DC_MAP_CONF_7 0x00000124
470 #define IPU_DC_MAP_CONF_8 0x00000128
471 #define IPU_DC_MAP_CONF_9 0x0000012c
472 #define IPU_DC_MAP_CONF_10 0x00000130
473 #define IPU_DC_MAP_CONF_11 0x00000134
474 #define IPU_DC_MAP_CONF_12 0x00000138
475 #define IPU_DC_MAP_CONF_13 0x0000013c
476 #define IPU_DC_MAP_CONF_14 0x00000140
478 #define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4)
479 #define IPU_DC_MAP_CONF_15 0x00000144
480 #define IPU_DC_MAP_CONF_16 0x00000148
481 #define IPU_DC_MAP_CONF_17 0x0000014c
482 #define IPU_DC_MAP_CONF_18 0x00000150
483 #define IPU_DC_MAP_CONF_19 0x00000154
484 #define IPU_DC_MAP_CONF_20 0x00000158
485 #define IPU_DC_MAP_CONF_21 0x0000015c
486 #define IPU_DC_MAP_CONF_22 0x00000160
487 #define IPU_DC_MAP_CONF_23 0x00000164
488 #define IPU_DC_MAP_CONF_24 0x00000168
489 #define IPU_DC_MAP_CONF_25 0x0000016c
490 #define IPU_DC_MAP_CONF_26 0x00000170
492 #define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4)
493 #define IPU_DC_UGDE0_0 0x00000174
494 #define IPU_DC_UGDE0_1 0x00000178
495 #define IPU_DC_UGDE0_2 0x0000017c
496 #define IPU_DC_UGDE0_3 0x00000180
497 #define IPU_DC_UGDE1_0 0x00000184
498 #define IPU_DC_UGDE1_1 0x00000188
499 #define IPU_DC_UGDE1_2 0x0000018c
500 #define IPU_DC_UGDE1_3 0x00000190
501 #define IPU_DC_UGDE2_0 0x00000194
502 #define IPU_DC_UGDE2_1 0x00000198
503 #define IPU_DC_UGDE2_2 0x0000019c
504 #define IPU_DC_UGDE2_3 0x000001a0
505 #define IPU_DC_UGDE3_0 0x000001a4
506 #define IPU_DC_UGDE3_1 0x000001a8
507 #define IPU_DC_UGDE3_2 0x000001ac
508 #define IPU_DC_UGDE3_3 0x000001b0
509 #define IPU_DC_LLA0 0x000001b4
510 #define IPU_DC_LLA1 0x000001b8
511 #define IPU_DC_R_LLA0 0x000001bc
512 #define IPU_DC_R_LLA1 0x000001c0
513 #define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4
514 #define IPU_DC_STAT 0x000001c8
518 * Display Multi FIFO Controller
520 #define IPU_DMFC_RD_CHAN 0x00000000
521 #define DMFC_RD_CHAN_PPW_C 0x03000000
522 #define DMFC_RD_CHAN_WM_DR_0 0x00e00000
523 #define DMFC_RD_CHAN_WM_SET_0 0x001c0000
524 #define DMFC_RD_CHAN_WM_EN_0 0x00020000
525 #define DMFC_RD_CHAN_BURST_SIZE_0 0x000000c0
526 #define IPU_DMFC_WR_CHAN 0x00000004
527 #define DMFC_WR_CHAN_BUSRT_SIZE_2C 0xc0000000
528 #define DMFC_WR_CHAN_FIFO_SIZE_2C 0x38000000
529 #define DMFC_WR_CHAN_ST_ADDR_2C 0x07000000
530 #define DMFC_WR_CHAN_BURST_SIZE_1C 0x00c00000
531 #define DMFC_WR_CHAN_FIFO_SIZE_1C 0x00380000
532 #define DMFC_WR_CHAN_ST_ADDR_1C 0x00070000
533 #define DMFC_WR_CHAN_BURST_SIZE_2 0x0000c000
534 #define DMFC_WR_CHAN_FIFO_SIZE_2 0x00003800
535 #define DMFC_WR_CHAN_ST_ADDR_2 0x00000700
536 #define DMFC_WR_CHAN_BURST_SIZE_1 0x000000c0
537 #define DMFC_WR_CHAN_FIFO_SIZE_1 0x00000038
538 #define DMFC_WR_CHAN_ST_ADDR_1 0x00000007
539 #define IPU_DMFC_WR_CHAN_DEF 0x00000008
540 #define DMFC_WR_CHAN_DEF_WM_CLR_2C 0xe0000000
541 #define DMFC_WR_CHAN_DEF_WM_SET_2C 0x1c000000
542 #define DMFC_WR_CHAN_DEF_WM_EN_2C 0x02000000
543 #define DMFC_WR_CHAN_DEF_WM_CLR_1C 0x00e00000
544 #define DMFC_WR_CHAN_DEF_WM_SET_1C 0x001c0000
545 #define DMFC_WR_CHAN_DEF_WM_EN_1C 0x00020000
546 #define DMFC_WR_CHAN_DEF_WM_CLR_2 0x0000e000
547 #define DMFC_WR_CHAN_DEF_WM_SET_2 0x00001c00
548 #define DMFC_WR_CHAN_DEF_WM_EN_2 0x00000200
549 #define DMFC_WR_CHAN_DEF_WM_CLR_1 0x000000e0
550 #define DMFC_WR_CHAN_DEF_WM_SET_1 0x0000000c
551 #define DMFC_WR_CHAN_DEF_WM_EN_1 0x00000002
552 #define IPU_DMFC_DP_CHAN 0x0000000c
553 #define DMFC_DP_CHAN_BUSRT_SIZE_6F 0xc0000000
554 #define DMFC_DP_CHAN_FIFO_SIZE_6F 0x38000000
555 #define DMFC_DP_CHAN_ST_ADDR_6F 0x07000000
556 #define DMFC_DP_CHAN_BURST_SIZE_6B 0x00c00000
557 #define DMFC_DP_CHAN_FIFO_SIZE_6B 0x00380000
558 #define DMFC_DP_CHAN_ST_ADDR_6B 0x00070000
559 #define DMFC_DP_CHAN_BURST_SIZE_5F 0x0000c000
560 #define DMFC_DP_CHAN_FIFO_SIZE_5F 0x00003800
561 #define DMFC_DP_CHAN_ST_ADDR_5F 0x00000700
562 #define DMFC_DP_CHAN_BURST_SIZE_5B 0x000000c0
563 #define DMFC_DP_CHAN_FIFO_SIZE_5B 0x00000038
564 #define DMFC_DP_CHAN_ST_ADDR_5B 0x00000007
565 #define IPU_DMFC_DP_CHAN_DEF 0x00000010
566 #define DMFC_DP_CHAN_DEF_WM_CLR_6F 0xe0000000
567 #define DMFC_DP_CHAN_DEF_WM_SET_6F 0x1c000000
568 #define DMFC_DP_CHAN_DEF_WM_EN_6F 0x02000000
569 #define DMFC_DP_CHAN_DEF_WM_CLR_6B 0x00e00000
570 #define DMFC_DP_CHAN_DEF_WM_SET_6B 0x001c0000
571 #define DMFC_DP_CHAN_DEF_WM_EN_6B 0x00020000
572 #define DMFC_DP_CHAN_DEF_WM_CLR_5F 0x0000e000
573 #define DMFC_DP_CHAN_DEF_WM_SET_5F 0x00001c00
574 #define DMFC_DP_CHAN_DEF_WM_EN_5F 0x00000200
575 #define DMFC_DP_CHAN_DEF_WM_CLR_5B 0x000000e0
576 #define DMFC_DP_CHAN_DEF_WM_SET_5B 0x0000001c
577 #define DMFC_DP_CHAN_DEF_WM_EN_5B 0x00000002
578 #define IPU_DMFC_GENERAL1 0x00000014
579 #define DMFC_GENERAL1_WAIT4EOT_9 0x01000000
580 #define DMFC_GENERAL1_WAIT4EOT_6F 0x00800000
581 #define DMFC_GENERAL1_WAIT4EOT_6B 0x00400000
582 #define DMFC_GENERAL1_WAIT4EOT_5F 0x00200000
583 #define DMFC_GENERAL1_WAIT4EOT_5B 0x00100000
584 #define DMFC_GENERAL1_WAIT4EOT_4 0x00080000
585 #define DMFC_GENERAL1_WAIT4EOT_3 0x00040000
586 #define DMFC_GENERAL1_WAIT4EOT_2 0x00020000
587 #define DMFC_GENERAL1_WAIT4EOT_1 0x00010000
588 #define DMFC_GENERAL1_WM_CLR_9 0x0000e000
589 #define DMFC_GENERAL1_WM_SET_9 0x00001c00
590 #define DMFC_GENERAL1_BURST_SIZE_9 0x00000060
591 #define DMFC_GENERAL1_DCDP_SYNC_PR 0x00000003
592 #define DCDP_SYNC_PR_FORBIDDEN 0
593 #define DCDP_SYNC_PR_DC_DP 1
594 #define DCDP_SYNC_PR_DP_DC 2
595 #define DCDP_SYNC_PR_ROUNDROBIN 3
596 #define IPU_DMFC_GENERAL2 0x00000018
597 #define DMFC_GENERAL2_FRAME_HEIGHT_RD 0x1fff0000
598 #define DMFC_GENERAL2_FRAME_WIDTH_RD 0x00001fff
599 #define IPU_DMFC_IC_CTRL 0x0000001c
600 #define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD 0xfff80000
601 #define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD 0x0007ffc0
602 #define DMFC_IC_CTRL_IC_PPW_C 0x00000030
603 #define DMFC_IC_CTRL_IC_IN_PORT 0x00000007
604 #define IC_IN_PORT_CH28 0
605 #define IC_IN_PORT_CH41 1
606 #define IC_IN_PORT_DISABLE 2
607 #define IC_IN_PORT_CH23 4
608 #define IC_IN_PORT_CH27 5
609 #define IC_IN_PORT_CH24 6
610 #define IC_IN_PORT_CH29 7
611 #define IPU_DMFC_WR_CHAN_ALT 0x00000020
612 #define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024
613 #define IPU_DMFC_DP_CHAN_ALT 0x00000028
614 #define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c
615 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT 0xe0000000
616 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT 0x1c000000
617 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT 0x02000000
618 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT 0x00e00000
619 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT 0x001c0000
620 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT 0x00020000
621 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT 0x000000e0
622 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT 0x0000001c
623 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT 0x00000002
624 #define IPU_DMFC_GENERAL1_ALT 0x00000030
625 #define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT 0x00800000
626 #define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT 0x00400000
627 #define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT 0x00100000
628 #define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT 0x00020000
629 #define IPU_DMFC_STAT 0x00000034
630 #define DMFC_STAT_IC_BUFFER_EMPTY 0x02000000
631 #define DMFC_STAT_IC_BUFFER_FULL 0x01000000
632 #define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n))
633 #define DMFC_STAT_FIFO_FULL(n) __BIT((n))
637 * Video De Interkacing Module
639 #define IPU_VDI_FSIZE 0x00000000
640 #define IPU_VDI_C 0x00000004
646 #define IPU_DP_COM_CONF_SYNC 0x00000000
647 #define DP_FG_EN_SYNC 0x00000001
648 #define DP_DP_GWAM_SYNC 0x00000004
649 #define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004
650 #define IPU_DP_FG_POS_SYNC 0x00000008
651 #define IPU_DP_CUR_POS_SYNC 0x0000000c
652 #define IPU_DP_CUR_MAP_SYNC 0x00000010
653 #define IPU_DP_CSC_SYNC_0 0x00000054
654 #define IPU_DP_CSC_SYNC_1 0x00000058
655 #define IPU_DP_CUR_POS_ALT 0x0000005c
656 #define IPU_DP_COM_CONF_ASYNC0 0x00000060
657 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064
658 #define IPU_DP_FG_POS_ASYNC0 0x00000068
659 #define IPU_DP_CUR_POS_ASYNC0 0x0000006c
660 #define IPU_DP_CUR_MAP_ASYNC0 0x00000070
661 #define IPU_DP_CSC_ASYNC0_0 0x000000b4
662 #define IPU_DP_CSC_ASYNC0_1 0x000000b8
663 #define IPU_DP_COM_CONF_ASYNC1 0x000000bc
664 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0
665 #define IPU_DP_FG_POS_ASYNC1 0x000000c4
666 #define IPU_DP_CUR_POS_ASYNC1 0x000000c8
667 #define IPU_DP_CUR_MAP_ASYNC1 0x000000cc
668 #define IPU_DP_CSC_ASYNC1_0 0x00000110
669 #define IPU_DP_CSC_ASYNC1_1 0x00000114
673 * non-Interleaved parameter
675 * param 0: XV W0[ 9: 0]
678 * param 1: YB W0[43:32]
682 * param 2: UBO W0[67:62]
687 * param 3: Reserved W0[112:96]
698 * param 4: FW W0[137:128]
700 * param 5: EBA0 W1[28:0]
702 * param 6: EBA1 W1[57:32]
704 * param 7: ILO W1[77:64]
711 * param 8: TH W1[101:96]
714 * param 9: SLUV W1[141:128]
717 * Interleaved parameter
719 * param 0: XV W0[ 9: 0]
722 * param 1: YB W0[43:32]
727 * param 2: SY W0[68:62]
731 * param 3: SCC W0[96]
737 * DEC_SEL W0[111:110]
749 * param 4: FW W0[137:128]
751 * param 5: EBA0 W1[28:0]
753 * param 6: EBA1 W1[57:32]
755 * param 7: ILO W1[77:64]
762 * param 8: TH W1[101:96]
768 * param 9: OFS0 W1[132:128]
777 #define __IDMA_PARAM(word, shift, size) \
778 ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff))
780 /* non-Interleaved parameter */
782 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10)
783 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9)
784 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13)
785 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12)
786 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1)
787 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1)
788 #define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22)
789 #define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22)
790 #define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4)
791 #define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1)
792 #define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1)
793 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3)
794 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2)
795 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1)
796 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1)
797 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1)
798 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1)
799 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1)
800 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1)
801 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13)
802 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12)
804 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29)
805 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29)
806 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20)
807 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7)
808 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4)
809 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1)
810 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3)
811 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2)
812 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7)
813 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14)
814 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3)
815 #define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14)
816 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1)
818 /* Interleaved parameter */
820 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10)
821 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9)
822 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13)
823 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12)
824 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1)
825 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1)
826 #define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12)
827 #define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11)
828 #define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10)
829 #define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7)
830 #define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10)
831 #define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1)
832 #define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1)
833 #define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7)
834 #define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1)
835 #define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1)
836 #define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3)
837 #define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2)
838 #define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1)
839 #define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1)
840 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3)
841 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2)
842 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1)
843 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1)
844 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1)
845 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1)
846 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1)
847 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1)
848 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13)
849 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12)
851 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29)
852 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29)
853 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20)
854 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7)
855 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4)
856 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1)
857 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3)
858 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2)
859 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7)
860 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14)
861 #define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3)
862 #define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3)
863 #define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3)
864 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3)
865 #define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5)
866 #define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5)
867 #define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5)
868 #define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5)
869 #define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1)
870 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1)
871 #define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1)
874 #define GPUMEM_BASE 0x20000000
875 #define GPUMEM_SIZE 0x20000
877 #define GPU_BASE 0x30000000
878 #define GPU_SIZE 0x10000000
881 * Image Processing Unit
883 * All addresses are relative to the base SoC address.
885 #define IPU_CM_BASE(_base) ((_base) + 0x1e000000)
886 #define IPU_CM_SIZE 0x8000
887 #define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000)
888 #define IPU_IDMAC_SIZE 0x8000
889 #define IPU_DP_BASE(_base) ((_base) + 0x1e018000)
890 #define IPU_DP_SIZE 0x8000
891 #define IPU_IC_BASE(_base) ((_base) + 0x1e020000)
892 #define IPU_IC_SIZE 0x8000
893 #define IPU_IRT_BASE(_base) ((_base) + 0x1e028000)
894 #define IPU_IRT_SIZE 0x8000
895 #define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000)
896 #define IPU_CSI0_SIZE 0x8000
897 #define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000)
898 #define IPU_CSI1_SIZE 0x8000
899 #define IPU_DI0_BASE(_base) ((_base) + 0x1e040000)
900 #define IPU_DI0_SIZE 0x8000
901 #define IPU_DI1_BASE(_base) ((_base) + 0x1e048000)
902 #define IPU_DI1_SIZE 0x8000
903 #define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000)
904 #define IPU_SMFC_SIZE 0x8000
905 #define IPU_DC_BASE(_base) ((_base) + 0x1e058000)
906 #define IPU_DC_SIZE 0x8000
907 #define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000)
908 #define IPU_DMFC_SIZE 0x8000
909 #define IPU_VDI_BASE(_base) ((_base) + 0x1e068000)
910 #define IPU_VDI_SIZE 0x8000
911 #define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000)
912 #define IPU_CPMEM_SIZE 0x20000
913 #define IPU_LUT_BASE(_base) ((_base) + 0x1f020000)
914 #define IPU_LUT_SIZE 0x20000
915 #define IPU_SRM_BASE(_base) ((_base) + 0x1f040000)
916 #define IPU_SRM_SIZE 0x20000
917 #define IPU_TPM_BASE(_base) ((_base) + 0x1f060000)
918 #define IPU_TPM_SIZE 0x20000
919 #define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000)
920 #define IPU_DCTMPL_SIZE 0x20000
922 #endif /* _ARM_IMX_IMX51_IPUV3REG_H */