2 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 * This software was developed by Oleksandr Rybalko under sponsorship
6 * from the FreeBSD Foundation.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 /* Registers definition for Freescale i.MX515 Generic Periodic Timer */
34 #define IMX_GPT_CR 0x0000 /* Control Register R/W */
35 #define GPT_CR_FO3 (1 << 31)
36 #define GPT_CR_FO2 (1 << 30)
37 #define GPT_CR_FO1 (1 << 29)
38 #define GPT_CR_OM3_SHIFT 26
39 #define GPT_CR_OM3_MASK 0x1c000000
40 #define GPT_CR_OM2_SHIFT 23
41 #define GPT_CR_OM2_MASK 0x03800000
42 #define GPT_CR_OM1_SHIFT 20
43 #define GPT_CR_OM1_MASK 0x00700000
44 #define GPT_CR_OMX_NONE 0
45 #define GPT_CR_OMX_TOGGLE 1
46 #define GPT_CR_OMX_CLEAR 2
47 #define GPT_CR_OMX_SET 3
48 #define GPT_CR_OMX_PULSE 4 /* Run CLKSRC on output pin */
49 #define GPT_CR_IM2_SHIFT 18
50 #define GPT_CR_IM2_MASK 0x000c0000
51 #define GPT_CR_IM1_SHIFT 16
52 #define GPT_CR_IM1_MASK 0x00030000
53 #define GPT_CR_IMX_NONE 0
54 #define GPT_CR_IMX_REDGE 1
55 #define GPT_CR_IMX_FEDGE 2
56 #define GPT_CR_IMX_BOTH 3
57 #define GPT_CR_SWR (1 << 15)
58 #define GPT_CR_24MEN (1 << 10)
59 #define GPT_CR_FRR (1 << 9)
60 #define GPT_CR_CLKSRC_NONE (0 << 6)
61 #define GPT_CR_CLKSRC_IPG (1 << 6)
62 #define GPT_CR_CLKSRC_IPG_HIGH (2 << 6)
63 #define GPT_CR_CLKSRC_EXT (3 << 6)
64 #define GPT_CR_CLKSRC_32K (4 << 6)
65 #define GPT_CR_CLKSRC_24M (5 << 6)
66 #define GPT_CR_STOPEN (1 << 5)
67 #define GPT_CR_DOZEEN (1 << 4)
68 #define GPT_CR_WAITEN (1 << 3)
69 #define GPT_CR_DBGEN (1 << 2)
70 #define GPT_CR_ENMOD (1 << 1)
71 #define GPT_CR_EN (1 << 0)
73 #define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */
74 #define GPT_PR_VALUE_SHIFT 0
75 #define GPT_PR_VALUE_MASK 0x00000fff
76 #define GPT_PR_VALUE_SHIFT_24M 12
77 #define GPT_PR_VALUE_MASK_24M 0x0000f000
79 /* Same map for SR and IR */
80 #define IMX_GPT_SR 0x0008 /* Status Register R/W */
81 #define IMX_GPT_IR 0x000c /* Interrupt Register R/W */
82 #define GPT_IR_ROV (1 << 5)
83 #define GPT_IR_IF2 (1 << 4)
84 #define GPT_IR_IF1 (1 << 3)
85 #define GPT_IR_OF3 (1 << 2)
86 #define GPT_IR_OF2 (1 << 1)
87 #define GPT_IR_OF1 (1 << 0)
96 #define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */
97 #define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */
98 #define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */
99 #define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */
100 #define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */
101 #define IMX_GPT_CNT 0x0024 /* Counter Register RO */