2 * Copyright (c) 2014 Ian Lepore
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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12 * documentation and/or other materials provided with the distribution.
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21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Pin mux and pad control driver for imx5 and imx6.
32 * This driver implements the fdt_pinctrl interface for configuring the gpio and
33 * peripheral pins based on fdt configuration data.
35 * When the driver attaches, it walks the entire fdt tree and automatically
36 * configures the pins for each device which has a pinctrl-0 property and whose
37 * status is "okay". In addition it implements the fdt_pinctrl_configure()
38 * method which any other driver can call at any time to reconfigure its pins.
40 * The nature of the fsl,pins property in fdt data makes this driver's job very
41 * easy. Instead of representing each pin and pad configuration using symbolic
42 * properties such as pullup-enable="true" and so on, the data simply contains
43 * the addresses of the registers that control the pins, and the raw values to
44 * store in those registers.
46 * The imx5 and imx6 SoCs also have a small number of "general purpose
47 * registers" in the iomuxc device which are used to control an assortment
48 * of completely unrelated aspects of SoC behavior. This driver provides other
49 * drivers with direct access to those registers via simple accessor functions.
52 #include <sys/param.h>
53 #include <sys/systm.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/malloc.h>
60 #include <machine/bus.h>
61 #include <machine/fdt.h>
63 #include <dev/fdt/fdt_common.h>
64 #include <dev/fdt/fdt_pinctrl.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
69 #include <arm/freescale/imx/imx_iomuxvar.h>
70 #include <arm/freescale/imx/imx_machdep.h>
74 struct resource *mem_res;
78 static struct iomux_softc *iomux_sc;
80 static struct ofw_compat_data compat_data[] = {
81 {"fsl,imx6dl-iomuxc", true},
82 {"fsl,imx6q-iomuxc", true},
83 {"fsl,imx6sl-iomuxc", true},
84 {"fsl,imx6sx-iomuxc", true},
85 {"fsl,imx53-iomuxc", true},
86 {"fsl,imx51-iomuxc", true},
91 * Each tuple in an fsl,pins property contains these fields.
102 #define PADCONF_NONE (1U << 31) /* Do not configure pad. */
103 #define PADCONF_SION (1U << 30) /* Force SION bit in mux register. */
104 #define PADMUX_SION (1U << 4) /* The SION bit in the mux register. */
106 static inline uint32_t
107 RD4(struct iomux_softc *sc, bus_size_t off)
110 return (bus_read_4(sc->mem_res, off));
114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val)
117 bus_write_4(sc->mem_res, off, val);
121 iomux_configure_input(struct iomux_softc *sc, uint32_t reg, uint32_t val)
123 u_int select, mask, shift, width;
125 /* If register and value are zero, there is nothing to configure. */
126 if (reg == 0 && val == 0)
130 * If the config value has 0xff in the high byte it is encoded:
132 * | 0xff | shift | width | select |
133 * We need to mask out the old select value and OR in the new, using a
134 * mask of the given width and shifting the values up by shift.
136 if ((val & 0xff000000) == 0xff000000) {
137 select = val & 0x000000ff;
138 width = (val & 0x0000ff00) >> 8;
139 shift = (val & 0x00ff0000) >> 16;
140 mask = ((1u << width) - 1) << shift;
141 val = (RD4(sc, reg) & ~mask) | (select << shift);
147 iomux_configure_pins(device_t dev, phandle_t cfgxref)
149 struct iomux_softc *sc;
150 struct pincfg *cfgtuples, *cfg;
155 sc = device_get_softc(dev);
156 cfgnode = OF_node_from_xref(cfgxref);
157 ntuples = OF_getencprop_alloc(cfgnode, "fsl,pins", sizeof(*cfgtuples),
158 (void **)&cfgtuples);
162 return (0); /* Empty property is not an error. */
163 for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) {
164 sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0;
165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion);
166 iomux_configure_input(sc, cfg->input_reg, cfg->input_val);
167 if ((cfg->padconf_val & PADCONF_NONE) == 0)
168 WR4(sc, cfg->padconf_reg, cfg->padconf_val);
171 OF_getprop(cfgnode, "name", &name, sizeof(name));
172 printf("%16s: muxreg 0x%04x muxval 0x%02x "
173 "inpreg 0x%04x inpval 0x%02x "
174 "padreg 0x%04x padval 0x%08x\n",
175 name, cfg->mux_reg, cfg->mux_val | sion,
176 cfg->input_reg, cfg->input_val,
177 cfg->padconf_reg, cfg->padconf_val);
180 free(cfgtuples, M_OFWPROP);
185 iomux_probe(device_t dev)
188 if (!ofw_bus_status_okay(dev))
191 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
194 device_set_desc(dev, "Freescale i.MX pin configuration");
195 return (BUS_PROBE_DEFAULT);
199 iomux_detach(device_t dev)
202 /* This device is always present. */
207 iomux_attach(device_t dev)
209 struct iomux_softc * sc;
212 sc = device_get_softc(dev);
215 switch (imx_soc_type()) {
229 device_printf(dev, "Unknown SoC type\n");
234 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
236 if (sc->mem_res == NULL) {
237 device_printf(dev, "Cannot allocate memory resources\n");
244 * Register as a pinctrl device, and call the convenience function that
245 * walks the entire device tree invoking FDT_PINCTRL_CONFIGURE() on any
246 * pinctrl-0 property cells whose xref phandle refers to a configuration
247 * that is a child node of our node in the tree.
249 * The pinctrl bindings documentation specifically mentions that the
250 * pinctrl device itself may have a pinctrl-0 property which contains
251 * static configuration to be applied at device init time. The tree
252 * walk will automatically handle this for us when it passes through our
255 fdt_pinctrl_register(dev, "fsl,pins");
256 fdt_pinctrl_configure_tree(dev);
262 imx_iomux_gpr_get(u_int regnum)
264 struct iomux_softc * sc;
267 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
268 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
269 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
271 return (RD4(iomux_sc, regnum * 4));
275 imx_iomux_gpr_set(u_int regnum, uint32_t val)
277 struct iomux_softc * sc;
280 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
281 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
282 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
284 WR4(iomux_sc, regnum * 4, val);
288 imx_iomux_gpr_set_masked(u_int regnum, uint32_t clrbits, uint32_t setbits)
290 struct iomux_softc * sc;
294 KASSERT(sc != NULL, ("%s called before attach", __FUNCTION__));
295 KASSERT(regnum >= 0 && regnum <= sc->last_gpreg,
296 ("%s bad regnum %u, max %u", __FUNCTION__, regnum, sc->last_gpreg));
298 val = RD4(iomux_sc, regnum * 4);
299 val = (val & ~clrbits) | setbits;
300 WR4(iomux_sc, regnum * 4, val);
303 static device_method_t imx_iomux_methods[] = {
304 /* Device interface */
305 DEVMETHOD(device_probe, iomux_probe),
306 DEVMETHOD(device_attach, iomux_attach),
307 DEVMETHOD(device_detach, iomux_detach),
309 /* fdt_pinctrl interface */
310 DEVMETHOD(fdt_pinctrl_configure,iomux_configure_pins),
315 static driver_t imx_iomux_driver = {
318 sizeof(struct iomux_softc),
321 static devclass_t imx_iomux_devclass;
323 EARLY_DRIVER_MODULE(imx_iomux, simplebus, imx_iomux_driver,
324 imx_iomux_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_LATE);