2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * SDHCI driver glue for Freescale i.MX SoC family.
33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/types.h>
40 #include <sys/callout.h>
41 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/resource.h>
48 #include <sys/sysctl.h>
49 #include <sys/taskqueue.h>
52 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/intr.h>
56 #include <arm/freescale/imx/imx_ccmvar.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
61 #include <dev/mmc/bridge.h>
62 #include <dev/mmc/mmcreg.h>
63 #include <dev/mmc/mmcbrvar.h>
65 #include <dev/sdhci/sdhci.h>
68 struct imx_sdhci_softc {
70 struct resource * mem_res;
71 struct resource * irq_res;
73 struct sdhci_slot slot;
74 struct callout r1bfix_callout;
75 sbintime_t r1bfix_timeout_at;
77 uint32_t sdclockreg_freq_bits;
78 uint32_t cmd_and_mode;
79 uint32_t r1bfix_intmask;
82 boolean_t force_card_present;
85 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
86 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
87 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
89 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
90 #define HWTYPE_ESDHC 1 /* imx5x and earlier. */
91 #define HWTYPE_USDHC 2 /* imx6. */
93 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
94 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
95 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
96 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
97 #define SDHC_VEND_IPGEN (1 << 11)
98 #define SDHC_VEND_HCKEN (1 << 12)
99 #define SDHC_VEND_PEREN (1 << 13)
101 #define SDHC_PRES_STATE 0x24
102 #define SDHC_PRES_CIHB (1 << 0)
103 #define SDHC_PRES_CDIHB (1 << 1)
104 #define SDHC_PRES_DLA (1 << 2)
105 #define SDHC_PRES_SDSTB (1 << 3)
106 #define SDHC_PRES_IPGOFF (1 << 4)
107 #define SDHC_PRES_HCKOFF (1 << 5)
108 #define SDHC_PRES_PEROFF (1 << 6)
109 #define SDHC_PRES_SDOFF (1 << 7)
110 #define SDHC_PRES_WTA (1 << 8)
111 #define SDHC_PRES_RTA (1 << 9)
112 #define SDHC_PRES_BWEN (1 << 10)
113 #define SDHC_PRES_BREN (1 << 11)
114 #define SDHC_PRES_RTR (1 << 12)
115 #define SDHC_PRES_CINST (1 << 16)
116 #define SDHC_PRES_CDPL (1 << 18)
117 #define SDHC_PRES_WPSPL (1 << 19)
118 #define SDHC_PRES_CLSL (1 << 23)
119 #define SDHC_PRES_DLSL_SHIFT 24
120 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
122 #define SDHC_PROT_CTRL 0x28
123 #define SDHC_PROT_LED (1 << 0)
124 #define SDHC_PROT_WIDTH_1BIT (0 << 1)
125 #define SDHC_PROT_WIDTH_4BIT (1 << 1)
126 #define SDHC_PROT_WIDTH_8BIT (2 << 1)
127 #define SDHC_PROT_WIDTH_MASK (3 << 1)
128 #define SDHC_PROT_D3CD (1 << 3)
129 #define SDHC_PROT_EMODE_BIG (0 << 4)
130 #define SDHC_PROT_EMODE_HALF (1 << 4)
131 #define SDHC_PROT_EMODE_LITTLE (2 << 4)
132 #define SDHC_PROT_EMODE_MASK (3 << 4)
133 #define SDHC_PROT_SDMA (0 << 8)
134 #define SDHC_PROT_ADMA1 (1 << 8)
135 #define SDHC_PROT_ADMA2 (2 << 8)
136 #define SDHC_PROT_ADMA264 (3 << 8)
137 #define SDHC_PROT_DMA_MASK (3 << 8)
138 #define SDHC_PROT_CDTL (1 << 6)
139 #define SDHC_PROT_CDSS (1 << 7)
141 #define SDHC_INT_STATUS 0x30
143 #define SDHC_CLK_IPGEN (1 << 0)
144 #define SDHC_CLK_HCKEN (1 << 1)
145 #define SDHC_CLK_PEREN (1 << 2)
146 #define SDHC_CLK_DIVISOR_MASK 0x000000f0
147 #define SDHC_CLK_DIVISOR_SHIFT 4
148 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00
149 #define SDHC_CLK_PRESCALE_SHIFT 8
151 static struct ofw_compat_data compat_data[] = {
152 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
153 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
154 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
155 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
159 static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable);
160 static void imx_sdhci_r1bfix_func(void *arg);
162 static inline uint32_t
163 RD4(struct imx_sdhci_softc *sc, bus_size_t off)
166 return (bus_read_4(sc->mem_res, off));
170 WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val)
173 bus_write_4(sc->mem_res, off, val);
177 imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
179 struct imx_sdhci_softc *sc = device_get_softc(dev);
180 uint32_t val32, wrk32;
183 * Most of the things in the standard host control register are in the
184 * hardware's wider protocol control register, but some of the bits are
187 if (off == SDHCI_HOST_CONTROL) {
188 wrk32 = RD4(sc, SDHC_PROT_CTRL);
189 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
190 SDHCI_CTRL_FORCE_CARD);
191 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
192 case SDHC_PROT_WIDTH_1BIT:
193 /* Value is already 0. */
195 case SDHC_PROT_WIDTH_4BIT:
196 val32 |= SDHCI_CTRL_4BITBUS;
198 case SDHC_PROT_WIDTH_8BIT:
199 val32 |= SDHCI_CTRL_8BITBUS;
202 switch (wrk32 & SDHC_PROT_DMA_MASK) {
204 /* Value is already 0. */
206 case SDHC_PROT_ADMA1:
207 /* This value is deprecated, should never appear. */
209 case SDHC_PROT_ADMA2:
210 val32 |= SDHCI_CTRL_ADMA2;
212 case SDHC_PROT_ADMA264:
213 val32 |= SDHCI_CTRL_ADMA264;
220 * XXX can't find the bus power on/off knob. For now we have to say the
221 * power is always on and always set to the same voltage.
223 if (off == SDHCI_POWER_CONTROL) {
224 return (SDHCI_POWER_ON | SDHCI_POWER_300);
228 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
232 imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
234 struct imx_sdhci_softc *sc = device_get_softc(dev);
235 uint32_t val32, wrk32;
237 if (sc->hwtype == HWTYPE_USDHC) {
239 * The USDHC hardware has nothing in the version register, but
240 * it's v3 compatible with all our translation code.
242 if (off == SDHCI_HOST_VERSION) {
243 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
246 * The USDHC hardware moved the transfer mode bits to the mixed
247 * control register, fetch them from there.
249 if (off == SDHCI_TRANSFER_MODE)
250 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
252 } else if (sc->hwtype == HWTYPE_ESDHC) {
255 * The ESDHC hardware has the typical 32-bit combined "command
256 * and mode" register that we have to cache so that command
257 * isn't written until after mode. On a read, just retrieve the
258 * cached values last written.
260 if (off == SDHCI_TRANSFER_MODE) {
261 return (sc->cmd_and_mode >> 16);
262 } else if (off == SDHCI_COMMAND_FLAGS) {
263 return (sc->cmd_and_mode & 0x0000ffff);
268 * This hardware only manages one slot. Synthesize a slot interrupt
269 * status register... if there are any enabled interrupts active they
270 * must be coming from our one and only slot.
272 if (off == SDHCI_SLOT_INT_STATUS) {
273 val32 = RD4(sc, SDHCI_INT_STATUS);
274 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
275 return (val32 ? 1 : 0);
279 * The clock enable bit is in the vendor register and the clock-stable
280 * bit is in the present state register. Transcribe them as if they
281 * were in the clock control register where they should be.
282 * XXX Is it important that we distinguish between "internal" and "card"
283 * clocks? Probably not; transcribe the card clock status to both bits.
285 if (off == SDHCI_CLOCK_CONTROL) {
287 wrk32 = RD4(sc, SDHC_VEND_SPEC);
288 if (wrk32 & SDHC_VEND_FRC_SDCLK_ON)
289 val32 |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN;
290 wrk32 = RD4(sc, SDHC_PRES_STATE);
291 if (wrk32 & SDHC_PRES_SDSTB)
292 val32 |= SDHCI_CLOCK_INT_STABLE;
293 val32 |= sc->sdclockreg_freq_bits;
297 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
301 imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
303 struct imx_sdhci_softc *sc = device_get_softc(dev);
304 uint32_t val32, wrk32;
306 val32 = RD4(sc, off);
309 * The hardware leaves the base clock frequency out of the capabilities
310 * register; fill it in. The timeout clock is the same as the active
311 * output sdclock; we indicate that with a quirk setting so don't
312 * populate the timeout frequency bits.
314 * XXX Turn off (for now) features the hardware can do but this driver
315 * doesn't yet handle (1.8v, suspend/resume, etc).
317 if (off == SDHCI_CAPABILITIES) {
318 val32 &= ~SDHCI_CAN_VDD_180;
319 val32 &= ~SDHCI_CAN_DO_SUSPEND;
320 val32 |= SDHCI_CAN_DO_8BITBUS;
321 val32 |= (sc->baseclk_hz / 1000000) << SDHCI_CLOCK_BASE_SHIFT;
326 * The hardware moves bits around in the present state register to make
327 * room for all 8 data line state bits. To translate, mask out all the
328 * bits which are not in the same position in both registers (this also
329 * masks out some freescale-specific bits in locations defined as
330 * reserved by sdhci), then shift the data line and retune request bits
331 * down to their standard locations.
333 if (off == SDHCI_PRESENT_STATE) {
336 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
337 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
338 if (sc->force_card_present)
339 val32 |= SDHCI_CARD_PRESENT;
344 * imx_sdhci_intr() can synthesize a DATA_END interrupt following a
345 * command with an R1B response, mix it into the hardware status.
347 if (off == SDHCI_INT_STATUS) {
348 return (val32 | sc->r1bfix_intmask);
355 imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
356 uint32_t *data, bus_size_t count)
358 struct imx_sdhci_softc *sc = device_get_softc(dev);
360 bus_read_multi_4(sc->mem_res, off, data, count);
364 imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
366 struct imx_sdhci_softc *sc = device_get_softc(dev);
370 * Most of the things in the standard host control register are in the
371 * hardware's wider protocol control register, but some of the bits are
374 if (off == SDHCI_HOST_CONTROL) {
375 val32 = RD4(sc, SDHC_PROT_CTRL);
376 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
377 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
378 val32 |= (val & SDHCI_CTRL_LED);
379 if (val & SDHCI_CTRL_8BITBUS)
380 val32 |= SDHC_PROT_WIDTH_8BIT;
382 val32 |= (val & SDHCI_CTRL_4BITBUS);
383 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
384 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
385 WR4(sc, SDHC_PROT_CTRL, val32);
389 /* XXX I can't find the bus power on/off knob; do nothing. */
390 if (off == SDHCI_POWER_CONTROL) {
394 val32 = RD4(sc, off & ~3);
395 val32 &= ~(0xff << (off & 3) * 8);
396 val32 |= (val << (off & 3) * 8);
398 WR4(sc, off & ~3, val32);
402 imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
404 struct imx_sdhci_softc *sc = device_get_softc(dev);
407 /* The USDHC hardware moved the transfer mode bits to mixed control. */
408 if (sc->hwtype == HWTYPE_USDHC) {
409 if (off == SDHCI_TRANSFER_MODE) {
410 val32 = RD4(sc, USDHC_MIX_CONTROL);
413 // XXX acmd23 not supported here (or by sdhci driver)
414 WR4(sc, USDHC_MIX_CONTROL, val32);
420 * The clock control stuff is complex enough to have its own routine
421 * that can both change speeds and en/disable the clock output. Also,
422 * save the register bits in SDHCI format so that we can play them back
423 * in the read2 routine without complex decoding.
425 if (off == SDHCI_CLOCK_CONTROL) {
426 sc->sdclockreg_freq_bits = val & 0xffc0;
427 if (val & SDHCI_CLOCK_CARD_EN) {
428 imx_sdhc_set_clock(sc, true);
430 imx_sdhc_set_clock(sc, false);
435 * Figure out whether we need to check the DAT0 line for busy status at
436 * interrupt time. The controller should be doing this, but for some
437 * reason it doesn't. There are two cases:
438 * - R1B response with no data transfer should generate a DATA_END (aka
439 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
440 * there's no data transfer there's no DATA_END interrupt. This is
441 * documented; they seem to think it's a feature.
442 * - R1B response after Auto-CMD12 appears to not work, even though
443 * there's a control bit for it (bit 3) in the vendor register.
444 * When we're starting a command that needs a manual DAT0 line check at
445 * interrupt time, we leave ourselves a note in r1bfix_type so that we
446 * can do the extra work in imx_sdhci_intr().
448 if (off == SDHCI_COMMAND_FLAGS) {
449 if (val & SDHCI_CMD_DATA) {
450 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
451 val32 = RD4(sc, USDHC_MIX_CONTROL);
452 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
453 sc->r1bfix_type = R1BFIX_AC12;
455 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
458 sc->r1bfix_type = R1BFIX_NODATA;
463 val32 = RD4(sc, off & ~3);
464 val32 &= ~(0xffff << (off & 3) * 8);
465 val32 |= ((val & 0xffff) << (off & 3) * 8);
466 WR4(sc, off & ~3, val32);
470 imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
472 struct imx_sdhci_softc *sc = device_get_softc(dev);
474 /* Clear synthesized interrupts, then pass the value to the hardware. */
475 if (off == SDHCI_INT_STATUS) {
476 sc->r1bfix_intmask &= ~val;
483 imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
484 uint32_t *data, bus_size_t count)
486 struct imx_sdhci_softc *sc = device_get_softc(dev);
488 bus_write_multi_4(sc->mem_res, off, data, count);
492 imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable)
494 uint32_t divisor, enable_bits, enable_reg, freq, prescale, val32;
496 if (sc->hwtype == HWTYPE_ESDHC) {
497 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) &
499 enable_reg = SDHCI_CLOCK_CONTROL;
500 enable_bits = SDHC_CLK_IPGEN | SDHC_CLK_HCKEN |
503 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) &
505 divisor |= ((sc->sdclockreg_freq_bits >>
506 SDHCI_DIVIDER_HI_SHIFT) &
507 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
508 enable_reg = SDHCI_CLOCK_CONTROL;
509 enable_bits = SDHC_VEND_IPGEN | SDHC_VEND_HCKEN |
513 WR4(sc, SDHC_VEND_SPEC,
514 RD4(sc, SDHC_VEND_SPEC) & ~SDHC_VEND_FRC_SDCLK_ON);
515 WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits);
521 freq = sc->baseclk_hz;
523 freq = sc->baseclk_hz / (2 * divisor);
525 for (prescale = 2; prescale < freq / prescale / 16;)
528 for (divisor = 1; freq < freq / prescale / divisor;)
534 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
535 val32 &= ~SDHC_CLK_DIVISOR_MASK;
536 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
537 val32 &= ~SDHC_CLK_PRESCALE_MASK;
538 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
539 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
541 WR4(sc, enable_reg, RD4(sc, enable_reg) | enable_bits);
542 WR4(sc, SDHC_VEND_SPEC,
543 RD4(sc, SDHC_VEND_SPEC) | SDHC_VEND_FRC_SDCLK_ON);
547 imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc)
551 mtx_assert(&sc->slot.mtx, MA_OWNED);
554 * Check the DAT0 line status using both the DLA (data line active) and
555 * CDIHB (data inhibit) bits in the present state register. In theory
556 * just DLA should do the trick, but in practice it takes both. If the
557 * DAT0 line is still being held and we're not yet beyond the timeout
558 * point, just schedule another callout to check again later.
560 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
562 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
563 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
564 imx_sdhci_r1bfix_func, sc, 0);
569 * If we reach this point with the inhibit bits still set, we've got a
570 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0
571 * line has been released, and we synthesize a DATA_END, and if the type
572 * of fix needed was on a command-without-data we also now add in the
573 * original INT_RESPONSE that we suppressed earlier.
576 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
578 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
579 if (sc->r1bfix_type == R1BFIX_NODATA)
580 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
583 sc->r1bfix_type = R1BFIX_NONE;
588 imx_sdhci_r1bfix_func(void * arg)
590 struct imx_sdhci_softc *sc = arg;
591 boolean_t r1bwait_done;
593 mtx_lock(&sc->slot.mtx);
594 r1bwait_done = imx_sdhci_r1bfix_is_wait_done(sc);
595 mtx_unlock(&sc->slot.mtx);
597 sdhci_generic_intr(&sc->slot);
601 imx_sdhci_intr(void *arg)
603 struct imx_sdhci_softc *sc = arg;
606 mtx_lock(&sc->slot.mtx);
609 * Manually check the DAT0 line for R1B response types that the
610 * controller fails to handle properly. The controller asserts the done
611 * interrupt while the card is still asserting busy with the DAT0 line.
613 * We check DAT0 immediately because most of the time, especially on a
614 * read, the card will actually be done by time we get here. If it's
615 * not, then the wait_done routine will schedule a callout to re-check
616 * periodically until it is done. In that case we clear the interrupt
617 * out of the hardware now so that we can present it later when the DAT0
620 * If we need to wait for the the DAT0 line to be released, we set up a
621 * timeout point 250ms in the future. This number comes from the SD
622 * spec, which allows a command to take that long. In the real world,
623 * cards tend to take 10-20ms for a long-running command such as a write
624 * or erase that spans two pages.
626 switch (sc->r1bfix_type) {
628 intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_RESPONSE;
631 intmask = RD4(sc, SDHC_INT_STATUS) & SDHCI_INT_DATA_END;
638 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
639 if (!imx_sdhci_r1bfix_is_wait_done(sc)) {
640 WR4(sc, SDHC_INT_STATUS, intmask);
641 bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4,
642 BUS_SPACE_BARRIER_WRITE);
646 mtx_unlock(&sc->slot.mtx);
647 sdhci_generic_intr(&sc->slot);
651 imx_sdhci_get_ro(device_t bus, device_t child)
658 imx_sdhci_detach(device_t dev)
665 imx_sdhci_attach(device_t dev)
667 struct imx_sdhci_softc *sc = device_get_softc(dev);
673 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
674 if (sc->hwtype == HWTYPE_NONE)
675 panic("Impossible: not compatible in imx_sdhci_attach()");
678 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
681 device_printf(dev, "cannot allocate memory window\n");
687 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
690 device_printf(dev, "cannot allocate interrupt\n");
695 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
696 NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) {
697 device_printf(dev, "cannot setup interrupt handler\n");
702 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
705 * DMA is not really broken, I just haven't implemented it yet.
707 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
710 * Set the buffer watermark level to 128 words (512 bytes) for both read
711 * and write. The hardware has a restriction that when the read or
712 * write ready status is asserted, that means you can read exactly the
713 * number of words set in the watermark register before you have to
714 * re-check the status and potentially wait for more data. The main
715 * sdhci driver provides no hook for doing status checking on less than
716 * a full block boundary, so we set the watermark level to be a full
717 * block. Reads and writes where the block size is less than the
718 * watermark size will work correctly too, no need to change the
719 * watermark for different size blocks. However, 128 is the maximum
720 * allowed for the watermark, so PIO is limitted to 512 byte blocks
721 * (which works fine for SD cards, may be a problem for SDIO some day).
723 * XXX need named constants for this stuff.
725 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
727 sc->baseclk_hz = imx_ccm_sdhci_hz();
730 * If the slot is flagged with the non-removable property, set our flag
731 * to always force the SDHCI_CARD_PRESENT bit on.
733 * XXX Workaround for gpio-based card detect...
735 * We don't have gpio support yet. If there's a cd-gpios property just
736 * force the SDHCI_CARD_PRESENT bit on for now. If there isn't really a
737 * card there it will fail to probe at the mmc layer and nothing bad
738 * happens except instantiating an mmcN device for an empty slot.
740 node = ofw_bus_get_node(dev);
741 if (OF_hasprop(node, "non-removable"))
742 sc->force_card_present = true;
743 else if (OF_hasprop(node, "cd-gpios")) {
744 /* XXX put real gpio hookup here. */
745 sc->force_card_present = true;
748 callout_init(&sc->r1bfix_callout, true);
749 sdhci_init_slot(dev, &sc->slot, 0);
751 bus_generic_probe(dev);
752 bus_generic_attach(dev);
754 sdhci_start_slot(&sc->slot);
760 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
764 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
770 imx_sdhci_probe(device_t dev)
773 if (!ofw_bus_status_okay(dev))
776 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
778 device_set_desc(dev, "Freescale eSDHC controller");
779 return (BUS_PROBE_DEFAULT);
781 device_set_desc(dev, "Freescale uSDHC controller");
782 return (BUS_PROBE_DEFAULT);
789 static device_method_t imx_sdhci_methods[] = {
790 /* Device interface */
791 DEVMETHOD(device_probe, imx_sdhci_probe),
792 DEVMETHOD(device_attach, imx_sdhci_attach),
793 DEVMETHOD(device_detach, imx_sdhci_detach),
796 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
797 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
798 DEVMETHOD(bus_print_child, bus_generic_print_child),
800 /* MMC bridge interface */
801 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
802 DEVMETHOD(mmcbr_request, sdhci_generic_request),
803 DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro),
804 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
805 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
807 /* SDHCI registers accessors */
808 DEVMETHOD(sdhci_read_1, imx_sdhci_read_1),
809 DEVMETHOD(sdhci_read_2, imx_sdhci_read_2),
810 DEVMETHOD(sdhci_read_4, imx_sdhci_read_4),
811 DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4),
812 DEVMETHOD(sdhci_write_1, imx_sdhci_write_1),
813 DEVMETHOD(sdhci_write_2, imx_sdhci_write_2),
814 DEVMETHOD(sdhci_write_4, imx_sdhci_write_4),
815 DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4),
820 static devclass_t imx_sdhci_devclass;
822 static driver_t imx_sdhci_driver = {
825 sizeof(struct imx_sdhci_softc),
828 DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0);
829 MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1);