2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * SDHCI driver glue for Freescale i.MX SoC family.
33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/resource.h>
44 #include <sys/taskqueue.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/intr.h>
50 #include <arm/freescale/imx/imx51_ccmvar.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/mmc/bridge.h>
56 #include <dev/mmc/mmcreg.h>
57 #include <dev/mmc/mmcbrvar.h>
59 #include <dev/sdhci/sdhci.h>
62 struct imx_sdhci_softc {
64 struct resource * mem_res;
65 struct resource * irq_res;
67 struct sdhci_slot slot;
69 uint32_t sdclockreg_freq_bits;
70 uint32_t cmd_and_mode;
71 uint32_t r1bfix_intmask;
74 boolean_t force_card_present;
77 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
78 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
79 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
81 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
82 #define HWTYPE_ESDHC 1 /* imx5x and earlier. */
83 #define HWTYPE_USDHC 2 /* imx6. */
85 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
86 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
87 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
88 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
89 #define SDHC_VEND_IPGEN (1 << 11)
90 #define SDHC_VEND_HCKEN (1 << 12)
91 #define SDHC_VEND_PEREN (1 << 13)
93 #define SDHC_PRES_STATE 0x24
94 #define SDHC_PRES_CIHB (1 << 0)
95 #define SDHC_PRES_CDIHB (1 << 1)
96 #define SDHC_PRES_DLA (1 << 2)
97 #define SDHC_PRES_SDSTB (1 << 3)
98 #define SDHC_PRES_IPGOFF (1 << 4)
99 #define SDHC_PRES_HCKOFF (1 << 5)
100 #define SDHC_PRES_PEROFF (1 << 6)
101 #define SDHC_PRES_SDOFF (1 << 7)
102 #define SDHC_PRES_WTA (1 << 8)
103 #define SDHC_PRES_RTA (1 << 9)
104 #define SDHC_PRES_BWEN (1 << 10)
105 #define SDHC_PRES_BREN (1 << 11)
106 #define SDHC_PRES_RTR (1 << 12)
107 #define SDHC_PRES_CINST (1 << 16)
108 #define SDHC_PRES_CDPL (1 << 18)
109 #define SDHC_PRES_WPSPL (1 << 19)
110 #define SDHC_PRES_CLSL (1 << 23)
111 #define SDHC_PRES_DLSL_SHIFT 24
112 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
114 #define SDHC_PROT_CTRL 0x28
115 #define SDHC_PROT_LED (1 << 0)
116 #define SDHC_PROT_WIDTH_1BIT (0 << 1)
117 #define SDHC_PROT_WIDTH_4BIT (1 << 1)
118 #define SDHC_PROT_WIDTH_8BIT (2 << 1)
119 #define SDHC_PROT_WIDTH_MASK (3 << 1)
120 #define SDHC_PROT_D3CD (1 << 3)
121 #define SDHC_PROT_EMODE_BIG (0 << 4)
122 #define SDHC_PROT_EMODE_HALF (1 << 4)
123 #define SDHC_PROT_EMODE_LITTLE (2 << 4)
124 #define SDHC_PROT_EMODE_MASK (3 << 4)
125 #define SDHC_PROT_SDMA (0 << 8)
126 #define SDHC_PROT_ADMA1 (1 << 8)
127 #define SDHC_PROT_ADMA2 (2 << 8)
128 #define SDHC_PROT_ADMA264 (3 << 8)
129 #define SDHC_PROT_DMA_MASK (3 << 8)
130 #define SDHC_PROT_CDTL (1 << 6)
131 #define SDHC_PROT_CDSS (1 << 7)
133 #define SDHC_CLK_IPGEN (1 << 0)
134 #define SDHC_CLK_HCKEN (1 << 1)
135 #define SDHC_CLK_PEREN (1 << 2)
136 #define SDHC_CLK_DIVISOR_MASK 0x000000f0
137 #define SDHC_CLK_DIVISOR_SHIFT 4
138 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00
139 #define SDHC_CLK_PRESCALE_SHIFT 8
141 static struct ofw_compat_data compat_data[] = {
142 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
143 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
144 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
145 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
149 static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable);
151 static inline uint32_t
152 RD4(struct imx_sdhci_softc *sc, bus_size_t off)
155 return (bus_read_4(sc->mem_res, off));
159 WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val)
162 bus_write_4(sc->mem_res, off, val);
166 imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
168 struct imx_sdhci_softc *sc = device_get_softc(dev);
169 uint32_t val32, wrk32;
172 * Most of the things in the standard host control register are in the
173 * hardware's wider protocol control register, but some of the bits are
176 if (off == SDHCI_HOST_CONTROL) {
177 wrk32 = RD4(sc, SDHC_PROT_CTRL);
178 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
179 SDHCI_CTRL_FORCE_CARD);
180 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
181 case SDHC_PROT_WIDTH_1BIT:
182 /* Value is already 0. */
184 case SDHC_PROT_WIDTH_4BIT:
185 val32 |= SDHCI_CTRL_4BITBUS;
187 case SDHC_PROT_WIDTH_8BIT:
188 val32 |= SDHCI_CTRL_8BITBUS;
191 switch (wrk32 & SDHC_PROT_DMA_MASK) {
193 /* Value is already 0. */
195 case SDHC_PROT_ADMA1:
196 /* This value is deprecated, should never appear. */
198 case SDHC_PROT_ADMA2:
199 val32 |= SDHCI_CTRL_ADMA2;
201 case SDHC_PROT_ADMA264:
202 val32 |= SDHCI_CTRL_ADMA264;
209 * XXX can't find the bus power on/off knob. For now we have to say the
210 * power is always on and always set to the same voltage.
212 if (off == SDHCI_POWER_CONTROL) {
213 return (SDHCI_POWER_ON | SDHCI_POWER_300);
217 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
221 imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
223 struct imx_sdhci_softc *sc = device_get_softc(dev);
224 uint32_t val32, wrk32;
226 if (sc->hwtype == HWTYPE_USDHC) {
228 * The USDHC hardware has nothing in the version register, but
229 * it's v3 compatible with all our translation code.
231 if (off == SDHCI_HOST_VERSION) {
232 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
235 * The USDHC hardware moved the transfer mode bits to the mixed
236 * control register, fetch them from there.
238 if (off == SDHCI_TRANSFER_MODE)
239 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
241 } else if (sc->hwtype == HWTYPE_ESDHC) {
244 * The ESDHC hardware has the typical 32-bit combined "command
245 * and mode" register that we have to cache so that command
246 * isn't written until after mode. On a read, just retrieve the
247 * cached values last written.
249 if (off == SDHCI_TRANSFER_MODE) {
250 return (sc->cmd_and_mode >> 16);
251 } else if (off == SDHCI_COMMAND_FLAGS) {
252 return (sc->cmd_and_mode & 0x0000ffff);
257 * This hardware only manages one slot. Synthesize a slot interrupt
258 * status register... if there are any enabled interrupts active they
259 * must be coming from our one and only slot.
261 if (off == SDHCI_SLOT_INT_STATUS) {
262 val32 = RD4(sc, SDHCI_INT_STATUS);
263 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
264 return (val32 ? 1 : 0);
268 * The clock enable bit is in the vendor register and the clock-stable
269 * bit is in the present state register. Transcribe them as if they
270 * were in the clock control register where they should be.
271 * XXX Is it important that we distinguish between "internal" and "card"
272 * clocks? Probably not; transcribe the card clock status to both bits.
274 if (off == SDHCI_CLOCK_CONTROL) {
276 wrk32 = RD4(sc, SDHC_VEND_SPEC);
277 if (wrk32 & SDHC_VEND_FRC_SDCLK_ON)
278 val32 |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN;
279 wrk32 = RD4(sc, SDHC_PRES_STATE);
280 if (wrk32 & SDHC_PRES_SDSTB)
281 val32 |= SDHCI_CLOCK_INT_STABLE;
282 val32 |= sc->sdclockreg_freq_bits;
286 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
290 imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
292 struct imx_sdhci_softc *sc = device_get_softc(dev);
293 uint32_t val32, wrk32;
295 val32 = RD4(sc, off);
298 * The hardware leaves the base clock frequency out of the capabilities
299 * register; fill it in. The timeout clock is the same as the active
300 * output sdclock; we indicate that with a quirk setting so don't
301 * populate the timeout frequency bits.
303 * XXX Turn off (for now) features the hardware can do but this driver
304 * doesn't yet handle (1.8v, suspend/resume, etc).
306 if (off == SDHCI_CAPABILITIES) {
307 val32 &= ~SDHCI_CAN_VDD_180;
308 val32 &= ~SDHCI_CAN_DO_SUSPEND;
309 val32 |= SDHCI_CAN_DO_8BITBUS;
310 val32 |= (sc->baseclk_hz / 1000000) << SDHCI_CLOCK_BASE_SHIFT;
315 * The hardware moves bits around in the present state register to make
316 * room for all 8 data line state bits. To translate, mask out all the
317 * bits which are not in the same position in both registers (this also
318 * masks out some freescale-specific bits in locations defined as
319 * reserved by sdhci), then shift the data line and retune request bits
320 * down to their standard locations.
322 if (off == SDHCI_PRESENT_STATE) {
325 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
326 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
327 if (sc->force_card_present)
328 val32 |= SDHCI_CARD_PRESENT;
333 * imx_sdhci_intr() can synthesize a DATA_END interrupt following a
334 * command with an R1B response, mix it into the hardware status.
336 if (off == SDHCI_INT_STATUS) {
337 return (val32 | sc->r1bfix_intmask);
344 imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
345 uint32_t *data, bus_size_t count)
347 struct imx_sdhci_softc *sc = device_get_softc(dev);
349 bus_read_multi_4(sc->mem_res, off, data, count);
353 imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
355 struct imx_sdhci_softc *sc = device_get_softc(dev);
359 * Most of the things in the standard host control register are in the
360 * hardware's wider protocol control register, but some of the bits are
363 if (off == SDHCI_HOST_CONTROL) {
364 val32 = RD4(sc, SDHC_PROT_CTRL);
365 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
366 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
367 val32 |= (val & SDHCI_CTRL_LED);
368 if (val & SDHCI_CTRL_8BITBUS)
369 val32 |= SDHC_PROT_WIDTH_8BIT;
371 val32 |= (val & SDHCI_CTRL_4BITBUS);
372 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
373 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
374 WR4(sc, SDHC_PROT_CTRL, val32);
378 /* XXX I can't find the bus power on/off knob; do nothing. */
379 if (off == SDHCI_POWER_CONTROL) {
383 val32 = RD4(sc, off & ~3);
384 val32 &= ~(0xff << (off & 3) * 8);
385 val32 |= (val << (off & 3) * 8);
387 WR4(sc, off & ~3, val32);
391 imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
393 struct imx_sdhci_softc *sc = device_get_softc(dev);
396 /* The USDHC hardware moved the transfer mode bits to mixed control. */
397 if (sc->hwtype == HWTYPE_USDHC) {
398 if (off == SDHCI_TRANSFER_MODE) {
399 val32 = RD4(sc, USDHC_MIX_CONTROL);
402 // XXX acmd23 not supported here (or by sdhci driver)
403 WR4(sc, USDHC_MIX_CONTROL, val32);
409 * The clock control stuff is complex enough to have its own routine
410 * that can both change speeds and en/disable the clock output. Also,
411 * save the register bits in SDHCI format so that we can play them back
412 * in the read2 routine without complex decoding.
414 if (off == SDHCI_CLOCK_CONTROL) {
415 sc->sdclockreg_freq_bits = val & 0xffc0;
416 if (val & SDHCI_CLOCK_CARD_EN) {
417 imx_sdhc_set_clock(sc, true);
419 imx_sdhc_set_clock(sc, false);
424 * Figure out whether we need to check the DAT0 line for busy status at
425 * interrupt time. The controller should be doing this, but for some
426 * reason it doesn't. There are two cases:
427 * - R1B response with no data transfer should generate a DATA_END (aka
428 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
429 * there's no data transfer there's no DATA_END interrupt. This is
430 * documented; they seem to think it's a feature.
431 * - R1B response after Auto-CMD12 appears to not work, even though
432 * there's a control bit for it (bit 3) in the vendor register.
433 * When we're starting a command that needs a manual DAT0 line check at
434 * interrupt time, we leave ourselves a note in r1bfix_type so that we
435 * can do the extra work in imx_sdhci_intr().
437 if (off == SDHCI_COMMAND_FLAGS) {
438 if (val & SDHCI_CMD_DATA) {
439 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
440 val32 = RD4(sc, USDHC_MIX_CONTROL);
441 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
442 sc->r1bfix_type = R1BFIX_AC12;
444 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
445 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
446 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
447 sc->r1bfix_type = R1BFIX_NODATA;
452 val32 = RD4(sc, off & ~3);
453 val32 &= ~(0xffff << (off & 3) * 8);
454 val32 |= ((val & 0xffff) << (off & 3) * 8);
455 WR4(sc, off & ~3, val32);
459 imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
461 struct imx_sdhci_softc *sc = device_get_softc(dev);
463 /* Clear synthesized interrupts, then pass the value to the hardware. */
464 if (off == SDHCI_INT_STATUS) {
465 sc->r1bfix_intmask &= ~val;
472 imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
473 uint32_t *data, bus_size_t count)
475 struct imx_sdhci_softc *sc = device_get_softc(dev);
477 bus_write_multi_4(sc->mem_res, off, data, count);
481 imx_sdhc_set_clock(struct imx_sdhci_softc *sc, int enable)
483 uint32_t divisor, enable_bits, enable_reg, freq, prescale, val32;
485 if (sc->hwtype == HWTYPE_ESDHC) {
486 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) &
488 enable_reg = SDHCI_CLOCK_CONTROL;
489 enable_bits = SDHC_CLK_IPGEN | SDHC_CLK_HCKEN |
492 divisor = (sc->sdclockreg_freq_bits >> SDHCI_DIVIDER_SHIFT) &
494 divisor |= ((sc->sdclockreg_freq_bits >>
495 SDHCI_DIVIDER_HI_SHIFT) &
496 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN;
497 enable_reg = SDHCI_CLOCK_CONTROL;
498 enable_bits = SDHC_VEND_IPGEN | SDHC_VEND_HCKEN |
502 WR4(sc, SDHC_VEND_SPEC,
503 RD4(sc, SDHC_VEND_SPEC) & ~SDHC_VEND_FRC_SDCLK_ON);
504 WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits);
510 freq = sc->baseclk_hz;
512 freq = sc->baseclk_hz / (2 * divisor);
514 for (prescale = 2; prescale < freq / prescale / 16;)
517 for (divisor = 1; freq < freq / prescale / divisor;)
523 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
524 val32 &= ~SDHC_CLK_DIVISOR_MASK;
525 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
526 val32 &= ~SDHC_CLK_PRESCALE_MASK;
527 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
528 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
530 WR4(sc, enable_reg, RD4(sc, enable_reg) | enable_bits);
531 WR4(sc, SDHC_VEND_SPEC,
532 RD4(sc, SDHC_VEND_SPEC) | SDHC_VEND_FRC_SDCLK_ON);
536 imx_sdhci_intr(void *arg)
538 struct imx_sdhci_softc *sc = arg;
541 intmask = RD4(sc, SDHCI_INT_STATUS);
544 * Manually check the DAT0 line for R1B response types that the
545 * controller fails to handle properly.
547 * To do the NODATA fix, when the RESPONSE (COMMAND_COMPLETE) interrupt
548 * occurs, we have to wait for the DAT0 line to be released, then
549 * synthesize a DATA_END (TRANSFER_COMPLETE) interrupt, which we do by
550 * storing SDHCI_INT_DATA_END into a variable that gets ORed into the
551 * return value when the SDHCI_INT_STATUS register is read.
553 * For the AC12 fix, when the DATA_END interrupt occurs we wait for the
554 * DAT0 line to be released, and the waiting is all the fix we need.
556 if ((sc->r1bfix_type == R1BFIX_NODATA &&
557 (intmask & SDHCI_INT_RESPONSE)) ||
558 (sc->r1bfix_type == R1BFIX_AC12 &&
559 (intmask & SDHCI_INT_DATA_END))) {
562 /* XXX use a callout or something instead of busy-waiting. */
563 while (count < 250000 &&
564 (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_DLA)) {
569 sc->r1bfix_intmask = SDHCI_INT_DATA_TIMEOUT;
570 else if (sc->r1bfix_type == R1BFIX_NODATA)
571 sc->r1bfix_intmask = SDHCI_INT_DATA_END;
572 sc->r1bfix_type = R1BFIX_NONE;
575 sdhci_generic_intr(&sc->slot);
579 imx_sdhci_get_ro(device_t bus, device_t child)
586 imx_sdhci_detach(device_t dev)
593 imx_sdhci_attach(device_t dev)
595 struct imx_sdhci_softc *sc = device_get_softc(dev);
601 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
602 if (sc->hwtype == HWTYPE_NONE)
603 panic("Impossible: not compatible in imx_sdhci_attach()");
606 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
609 device_printf(dev, "cannot allocate memory window\n");
615 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
618 device_printf(dev, "cannot allocate interrupt\n");
623 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
624 NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) {
625 device_printf(dev, "cannot setup interrupt handler\n");
630 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
633 * DMA is not really broken, I just haven't implemented it yet.
635 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
638 * Set the buffer watermark level to 128 words (512 bytes) for both read
639 * and write. The hardware has a restriction that when the read or
640 * write ready status is asserted, that means you can read exactly the
641 * number of words set in the watermark register before you have to
642 * re-check the status and potentially wait for more data. The main
643 * sdhci driver provides no hook for doing status checking on less than
644 * a full block boundary, so we set the watermark level to be a full
645 * block. Reads and writes where the block size is less than the
646 * watermark size will work correctly too, no need to change the
647 * watermark for different size blocks. However, 128 is the maximum
648 * allowed for the watermark, so PIO is limitted to 512 byte blocks
649 * (which works fine for SD cards, may be a problem for SDIO some day).
651 * XXX need named constants for this stuff.
653 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
655 /* XXX get imx6 clock frequency from CCM */
656 if (sc->hwtype == HWTYPE_USDHC) {
657 sc->baseclk_hz = 200000000;
658 } else if (sc->hwtype == HWTYPE_ESDHC) {
659 sc->baseclk_hz = imx51_get_clock(IMX51CLK_PERCLK_ROOT);
662 sdhci_init_slot(dev, &sc->slot, 0);
665 * If the slot is flagged with the non-removable property, set our flag
666 * to always force the SDHCI_CARD_PRESENT bit on.
668 * XXX Workaround for gpio-based card detect...
670 * We don't have gpio support yet. If there's a cd-gpios property just
671 * force the SDHCI_CARD_PRESENT bit on for now. If there isn't really a
672 * card there it will fail to probe at the mmc layer and nothing bad
673 * happens except instantiating a /dev/mmcN device for an empty slot.
675 node = ofw_bus_get_node(dev);
676 if (OF_hasprop(node, "non-removable"))
677 sc->force_card_present = true;
678 else if (OF_hasprop(node, "cd-gpios")) {
679 /* XXX put real gpio hookup here. */
680 sc->force_card_present = true;
683 bus_generic_probe(dev);
684 bus_generic_attach(dev);
686 sdhci_start_slot(&sc->slot);
692 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
694 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
696 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
702 imx_sdhci_probe(device_t dev)
705 if (!ofw_bus_status_okay(dev))
708 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
710 device_set_desc(dev, "Freescale eSDHC controller");
711 return (BUS_PROBE_DEFAULT);
713 device_set_desc(dev, "Freescale uSDHC controller");
714 return (BUS_PROBE_DEFAULT);
721 static device_method_t imx_sdhci_methods[] = {
722 /* Device interface */
723 DEVMETHOD(device_probe, imx_sdhci_probe),
724 DEVMETHOD(device_attach, imx_sdhci_attach),
725 DEVMETHOD(device_detach, imx_sdhci_detach),
728 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
729 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
730 DEVMETHOD(bus_print_child, bus_generic_print_child),
732 /* MMC bridge interface */
733 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
734 DEVMETHOD(mmcbr_request, sdhci_generic_request),
735 DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro),
736 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
737 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
739 /* SDHCI registers accessors */
740 DEVMETHOD(sdhci_read_1, imx_sdhci_read_1),
741 DEVMETHOD(sdhci_read_2, imx_sdhci_read_2),
742 DEVMETHOD(sdhci_read_4, imx_sdhci_read_4),
743 DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4),
744 DEVMETHOD(sdhci_write_1, imx_sdhci_write_1),
745 DEVMETHOD(sdhci_write_2, imx_sdhci_write_2),
746 DEVMETHOD(sdhci_write_4, imx_sdhci_write_4),
747 DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4),
752 static devclass_t imx_sdhci_devclass;
754 static driver_t imx_sdhci_driver = {
757 sizeof(struct imx_sdhci_softc),
760 DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0);
761 MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1);