2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Vybrid Family Inter-Integrated Circuit (I2C)
29 * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013
33 * This driver is based on the I2C driver for i.MX
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
49 #include <dev/iicbus/iiconf.h>
50 #include <dev/iicbus/iicbus.h>
52 #include "iicbus_if.h"
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
59 #include <machine/bus.h>
60 #include <machine/fdt.h>
61 #include <machine/cpu.h>
62 #include <machine/intr.h>
64 #include <arm/freescale/vybrid/vf_common.h>
66 #define I2C_IBAD 0x0 /* I2C Bus Address Register */
67 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */
68 #define I2C_IBCR 0x2 /* I2C Bus Control Register */
69 #define IBCR_MDIS (1 << 7) /* Module disable. */
70 #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */
71 #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */
72 #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */
73 #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */
74 #define IBCR_RSTA (1 << 2) /* Repeat Start. */
75 #define IBCR_DMAEN (1 << 1) /* DMA Enable. */
76 #define I2C_IBSR 0x3 /* I2C Bus Status Register */
77 #define IBSR_TCF (1 << 7) /* Transfer complete. */
78 #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */
79 #define IBSR_IBB (1 << 5) /* Bus busy. */
80 #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */
81 #define IBSR_SRW (1 << 2) /* Slave Read/Write. */
82 #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */
83 #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */
84 #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */
85 #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */
86 #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */
87 #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */
90 #define vf_i2c_dbg(_sc, fmt, args...) \
91 device_printf((_sc)->dev, fmt, ##args)
93 #define vf_i2c_dbg(_sc, fmt, args...)
96 static int i2c_repeated_start(device_t, u_char, int);
97 static int i2c_start(device_t, u_char, int);
98 static int i2c_stop(device_t);
99 static int i2c_reset(device_t, u_char, u_char, u_char *);
100 static int i2c_read(device_t, char *, int, int *, int, int);
101 static int i2c_write(device_t, const char *, int, int *, int);
104 struct resource *res[2];
106 bus_space_handle_t bsh;
112 static struct resource_spec i2c_spec[] = {
113 { SYS_RES_MEMORY, 0, RF_ACTIVE },
114 { SYS_RES_IRQ, 0, RF_ACTIVE },
119 i2c_probe(device_t dev)
122 if (!ofw_bus_status_okay(dev))
125 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-i2c"))
128 device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)");
129 return (BUS_PROBE_DEFAULT);
133 i2c_attach(device_t dev)
135 struct i2c_softc *sc;
137 sc = device_get_softc(dev);
140 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
142 if (bus_alloc_resources(dev, i2c_spec, sc->res)) {
143 device_printf(dev, "could not allocate resources\n");
147 /* Memory interface */
148 sc->bst = rman_get_bustag(sc->res[0]);
149 sc->bsh = rman_get_bushandle(sc->res[0]);
151 WRITE1(sc, I2C_IBIC, IBIC_BIIE);
153 sc->iicbus = device_add_child(dev, "iicbus", -1);
154 if (sc->iicbus == NULL) {
155 device_printf(dev, "could not add iicbus child");
156 mtx_destroy(&sc->mutex);
160 bus_generic_attach(dev);
165 /* Wait for transfer interrupt flag */
167 wait_for_iif(struct i2c_softc *sc)
173 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
174 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
180 return (IIC_ETIMEOUT);
183 /* Wait for free bus */
185 wait_for_nibb(struct i2c_softc *sc)
191 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0)
196 return (IIC_ETIMEOUT);
199 /* Wait for transfer complete+interrupt flag */
201 wait_for_icf(struct i2c_softc *sc)
207 if (READ1(sc, I2C_IBSR) & IBSR_TCF) {
208 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
209 WRITE1(sc, I2C_IBSR, IBSR_IBIF);
216 return (IIC_ETIMEOUT);
220 i2c_repeated_start(device_t dev, u_char slave, int timeout)
222 struct i2c_softc *sc;
226 sc = device_get_softc(dev);
228 vf_i2c_dbg(sc, "i2c repeated start\n");
230 mtx_lock(&sc->mutex);
232 WRITE1(sc, I2C_IBAD, slave);
234 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) {
235 mtx_unlock(&sc->mutex);
236 return (IIC_EBUSBSY);
239 /* Set repeated start condition */
242 reg = READ1(sc, I2C_IBCR);
243 reg |= (IBCR_RSTA | IBCR_IBIE);
244 WRITE1(sc, I2C_IBCR, reg);
248 /* Write target address - LSB is R/W bit */
249 WRITE1(sc, I2C_IBDR, slave);
251 error = wait_for_iif(sc);
253 mtx_unlock(&sc->mutex);
262 i2c_start(device_t dev, u_char slave, int timeout)
264 struct i2c_softc *sc;
268 sc = device_get_softc(dev);
270 vf_i2c_dbg(sc, "i2c start\n");
272 mtx_lock(&sc->mutex);
274 WRITE1(sc, I2C_IBAD, slave);
276 if (READ1(sc, I2C_IBSR) & IBSR_IBB) {
277 mtx_unlock(&sc->mutex);
278 vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n");
279 return (IIC_EBUSBSY);
282 /* Set start condition */
283 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE);
284 WRITE1(sc, I2C_IBCR, reg);
289 WRITE1(sc, I2C_IBCR, reg);
291 /* Write target address - LSB is R/W bit */
292 WRITE1(sc, I2C_IBDR, slave);
294 error = wait_for_iif(sc);
296 mtx_unlock(&sc->mutex);
298 vf_i2c_dbg(sc, "cant i2c start: iif error\n");
306 i2c_stop(device_t dev)
308 struct i2c_softc *sc;
310 sc = device_get_softc(dev);
312 vf_i2c_dbg(sc, "i2c stop\n");
314 mtx_lock(&sc->mutex);
316 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE);
320 /* Reset controller if bus still busy after STOP */
321 if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
322 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
324 WRITE1(sc, I2C_IBCR, IBCR_NOACK);
326 mtx_unlock(&sc->mutex);
332 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
334 struct i2c_softc *sc;
336 sc = device_get_softc(dev);
338 vf_i2c_dbg(sc, "i2c reset\n");
349 mtx_lock(&sc->mutex);
350 WRITE1(sc, I2C_IBCR, IBCR_MDIS);
354 WRITE1(sc, I2C_IBFD, 20);
355 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */
359 mtx_unlock(&sc->mutex);
365 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
367 struct i2c_softc *sc;
370 sc = device_get_softc(dev);
372 vf_i2c_dbg(sc, "i2c read\n");
376 mtx_lock(&sc->mutex);
380 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
383 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL);
390 while (*read < len) {
391 error = wait_for_icf(sc);
393 mtx_unlock(&sc->mutex);
397 if ((*read == len - 2) && last) {
398 /* NO ACK on last byte */
399 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \
403 if ((*read == len - 1) && last) {
404 /* Transfer done, remove master bit */
405 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK);
408 *buf++ = READ1(sc, I2C_IBDR);
411 mtx_unlock(&sc->mutex);
417 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
419 struct i2c_softc *sc;
422 sc = device_get_softc(dev);
424 vf_i2c_dbg(sc, "i2c write\n");
428 mtx_lock(&sc->mutex);
429 while (*sent < len) {
431 WRITE1(sc, I2C_IBDR, *buf++);
433 error = wait_for_iif(sc);
435 mtx_unlock(&sc->mutex);
441 mtx_unlock(&sc->mutex);
446 static device_method_t i2c_methods[] = {
447 DEVMETHOD(device_probe, i2c_probe),
448 DEVMETHOD(device_attach, i2c_attach),
450 DEVMETHOD(iicbus_callback, iicbus_null_callback),
451 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start),
452 DEVMETHOD(iicbus_start, i2c_start),
453 DEVMETHOD(iicbus_stop, i2c_stop),
454 DEVMETHOD(iicbus_reset, i2c_reset),
455 DEVMETHOD(iicbus_read, i2c_read),
456 DEVMETHOD(iicbus_write, i2c_write),
457 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
462 static driver_t i2c_driver = {
465 sizeof(struct i2c_softc),
468 static devclass_t i2c_devclass;
470 DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
471 DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);