1 /* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */
4 * Copyright (c) 1994 Mark Brinicombe.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the RiscBSD team.
18 * 4. The name "RiscBSD" nor the name of the author may be used to
19 * endorse or promote products derived from this software without specific
20 * prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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37 #ifndef _MACHINE_PTE_H_
38 #define _MACHINE_PTE_H_
40 #define PDSHIFT 20 /* LOG2(NBPDR) */
41 #define NBPD (1 << PDSHIFT) /* bytes/page dir */
42 #define NPTEPD (NBPD / PAGE_SIZE)
45 typedef uint32_t pd_entry_t; /* page directory entry */
46 typedef uint32_t pt_entry_t; /* page table entry */
49 #define PD_MASK 0xfff00000 /* page directory address bits */
50 #define PT_MASK 0x000ff000 /* page table address bits */
52 #define PG_FRAME 0xfffff000
54 /* The PT_SIZE definition is misleading... A page table is only 0x400
55 * bytes long. But since VM mapping can only be done to 0x1000 a single
56 * 1KB blocks cannot be steered to a va by itself. Therefore the
57 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
58 * was allocated for a PT then the other 3KB would also get mapped
59 * whenever the 1KB was mapped.
62 #define PT_RSIZE 0x0400 /* Real page table size */
63 #define PT_SIZE 0x1000
64 #define PD_SIZE 0x4000
66 /* Page table types and masks */
67 #define L1_PAGE 0x01 /* L1 page table mapping */
68 #define L1_SECTION 0x02 /* L1 section mapping */
69 #define L1_FPAGE 0x03 /* L1 fine page mapping */
70 #define L1_MASK 0x03 /* Mask for L1 entry type */
71 #define L2_LPAGE 0x01 /* L2 large page (64KB) */
72 #define L2_SPAGE 0x02 /* L2 small page (4KB) */
73 #define L2_MASK 0x03 /* Mask for L2 entry type */
74 #define L2_INVAL 0x00 /* L2 invalid type */
76 /* PTE construction macros */
77 #define L2_LPTE(p, a, f) ((p) | PT_AP(a) | L2_LPAGE | (f))
78 #define L2_SPTE(p, a, f) ((p) | PT_AP(a) | L2_SPAGE | (f))
79 #define L2_PTE(p, a) L2_SPTE((p), (a), PT_CACHEABLE)
80 #define L2_PTE_NC(p, a) L2_SPTE((p), (a), PT_B)
81 #define L2_PTE_NC_NB(p, a) L2_SPTE((p), (a), 0)
82 #define L1_SECPTE(p, a, f) ((p) | ((a) << AP_SECTION_SHIFT) | (f) \
85 #define L1_PTE(p) ((p) | 0x00 | L1_PAGE | PT_U)
86 #define L1_SEC(p, c) L1_SECPTE((p), AP_KRW, (c))
88 #define L1_SEC_SIZE (1 << PDSHIFT)
89 #define L2_LPAGE_SIZE (NBPG * 16)
92 #define DOMAIN_FAULT 0x00
93 #define DOMAIN_CLIENT 0x01
94 #define DOMAIN_RESERVED 0x02
95 #define DOMAIN_MANAGER 0x03
97 /* L1 and L2 address masks */
98 #define L1_ADDR_MASK 0xfffffc00
99 #define L2_ADDR_MASK 0xfffff000
102 * The ARM MMU architecture was introduced with ARM v3 (previous ARM
103 * architecture versions used an optional off-CPU memory controller
104 * to perform address translation).
106 * The ARM MMU consists of a TLB and translation table walking logic.
107 * There is typically one TLB per memory interface (or, put another
108 * way, one TLB per software-visible cache).
110 * The ARM MMU is capable of mapping memory in the following chunks:
112 * 1M Sections (L1 table)
114 * 64K Large Pages (L2 table)
116 * 4K Small Pages (L2 table)
118 * 1K Tiny Pages (L2 table)
120 * There are two types of L2 tables: Coarse Tables and Fine Tables.
121 * Coarse Tables can map Large and Small Pages. Fine Tables can
124 * Coarse Tables can define 4 Subpages within Large and Small pages.
125 * Subpages define different permissions for each Subpage within
128 * Coarse Tables are 1K in length. Fine tables are 4K in length.
130 * The Translation Table Base register holds the pointer to the
131 * L1 Table. The L1 Table is a 16K contiguous chunk of memory
132 * aligned to a 16K boundary. Each entry in the L1 Table maps
133 * 1M of virtual address space, either via a Section mapping or
136 * In addition, the Fast Context Switching Extension (FCSE) is available
137 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
138 * TLB/cache flushes on context switch by use of a smaller address space
139 * and a "process ID" that modifies the virtual address before being
140 * presented to the translation logic.
143 /* ARMv6 super-sections. */
144 #define L1_SUP_SIZE 0x01000000 /* 16M */
145 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
146 #define L1_SUP_FRAME (~L1_SUP_OFFSET)
147 #define L1_SUP_SHIFT 24
149 #define L1_S_SIZE 0x00100000 /* 1M */
150 #define L1_S_OFFSET (L1_S_SIZE - 1)
151 #define L1_S_FRAME (~L1_S_OFFSET)
152 #define L1_S_SHIFT 20
154 #define L2_L_SIZE 0x00010000 /* 64K */
155 #define L2_L_OFFSET (L2_L_SIZE - 1)
156 #define L2_L_FRAME (~L2_L_OFFSET)
157 #define L2_L_SHIFT 16
159 #define L2_S_SIZE 0x00001000 /* 4K */
160 #define L2_S_OFFSET (L2_S_SIZE - 1)
161 #define L2_S_FRAME (~L2_S_OFFSET)
162 #define L2_S_SHIFT 12
164 #define L2_T_SIZE 0x00000400 /* 1K */
165 #define L2_T_OFFSET (L2_T_SIZE - 1)
166 #define L2_T_FRAME (~L2_T_OFFSET)
167 #define L2_T_SHIFT 10
170 * The NetBSD VM implementation only works on whole pages (4K),
171 * whereas the ARM MMU's Coarse tables are sized in terms of 1K
172 * (16K L1 table, 1K L2 table).
174 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
177 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
178 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
180 #define L1_TABLE_SIZE 0x4000 /* 16K */
181 #define L2_TABLE_SIZE 0x1000 /* 4K */
183 * The new pmap deals with the 1KB coarse L2 tables by
184 * allocating them from a pool. Until every port has been converted,
185 * keep the old L2_TABLE_SIZE define lying around. Converted ports
186 * should use L2_TABLE_SIZE_REAL until then.
188 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */
194 #define L1_TYPE_INV 0x00 /* Invalid (fault) */
195 #define L1_TYPE_C 0x01 /* Coarse L2 */
196 #define L1_TYPE_S 0x02 /* Section */
197 #define L1_TYPE_F 0x03 /* Fine L2 */
198 #define L1_TYPE_MASK 0x03 /* mask of type bits */
200 /* L1 Section Descriptor */
201 #define L1_S_B 0x00000004 /* bufferable Section */
202 #define L1_S_C 0x00000008 /* cacheable Section */
203 #define L1_S_IMP 0x00000010 /* implementation defined */
204 #define L1_S_DOM(x) ((x) << 5) /* domain */
205 #define L1_S_DOM_MASK L1_S_DOM(0xf)
206 #define L1_S_AP(x) ((x) << 10) /* access permissions */
207 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
208 #define L1_SHARED (1 << 16)
210 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
211 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
213 #define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */
215 /* L1 Coarse Descriptor */
216 #define L1_C_IMP0 0x00000004 /* implementation defined */
217 #define L1_C_IMP1 0x00000008 /* implementation defined */
218 #define L1_C_IMP2 0x00000010 /* implementation defined */
219 #define L1_C_DOM(x) ((x) << 5) /* domain */
220 #define L1_C_DOM_MASK L1_C_DOM(0xf)
221 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
223 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
225 /* L1 Fine Descriptor */
226 #define L1_F_IMP0 0x00000004 /* implementation defined */
227 #define L1_F_IMP1 0x00000008 /* implementation defined */
228 #define L1_F_IMP2 0x00000010 /* implementation defined */
229 #define L1_F_DOM(x) ((x) << 5) /* domain */
230 #define L1_F_DOM_MASK L1_F_DOM(0xf)
231 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
233 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
239 #define L2_TYPE_INV 0x00 /* Invalid (fault) */
240 #define L2_TYPE_L 0x01 /* Large Page */
241 #define L2_TYPE_S 0x02 /* Small Page */
242 #define L2_TYPE_T 0x03 /* Tiny Page */
243 #define L2_TYPE_MASK 0x03 /* mask of type bits */
246 * This L2 Descriptor type is available on XScale processors
247 * when using a Coarse L1 Descriptor. The Extended Small
248 * Descriptor has the same format as the XScale Tiny Descriptor,
249 * but describes a 4K page, rather than a 1K page.
251 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */
253 #define L2_B 0x00000004 /* Bufferable page */
254 #define L2_C 0x00000008 /* Cacheable page */
255 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
256 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
257 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
258 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
259 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
261 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
262 #define L2_XSCALE_L_S(x) (1 << 15) /* Shared */
263 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
266 * Access Permissions for L1 and L2 Descriptors.
268 #define AP_W 0x01 /* writable */
269 #define AP_U 0x02 /* user */
272 * Short-hand for common AP_* constants.
274 * Note: These values assume the S (System) bit is set and
275 * the R (ROM) bit is clear in CP15 register 1.
277 #define AP_KR 0x00 /* kernel read */
278 #define AP_KRW 0x01 /* kernel read/write */
279 #define AP_KRWUR 0x02 /* kernel read/write usr read */
280 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */
283 * Domain Types for the Domain Access Control Register.
285 #define DOMAIN_FAULT 0x00 /* no access */
286 #define DOMAIN_CLIENT 0x01 /* client */
287 #define DOMAIN_RESERVED 0x02 /* reserved */
288 #define DOMAIN_MANAGER 0x03 /* manager */
291 * Type Extension bits for XScale processors.
293 * Behavior of C and B when X == 0:
295 * C B Cacheable Bufferable Write Policy Line Allocate Policy
298 * 1 0 Y Y Write-through Read Allocate
299 * 1 1 Y Y Write-back Read Allocate
301 * Behavior of C and B when X == 1:
302 * C B Cacheable Bufferable Write Policy Line Allocate Policy
303 * 0 0 - - - - DO NOT USE
305 * 1 0 Mini-Data - - -
306 * 1 1 Y Y Write-back R/W Allocate
308 #define TEX_XSCALE_X 0x01 /* X modifies C and B */
309 #define TEX_XSCALE_E 0x02
310 #define TEX_XSCALE_T 0x04
316 * Cache attributes with L2 present, S = 0
317 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
318 * 0 0 0 0 0 N N - N N
319 * 0 0 0 0 1 N N - N Y
320 * 0 0 0 1 0 Y Y WT N Y
321 * 0 0 0 1 1 Y Y WB Y Y
322 * 0 0 1 0 0 N N - Y Y
323 * 0 0 1 0 1 N N - N N
324 * 0 0 1 1 0 Y Y - - N
325 * 0 0 1 1 1 Y Y WT Y Y
326 * 0 1 0 0 0 N N - N N
327 * 0 1 0 0 1 N/A N/A N/A N/A N/A
328 * 0 1 0 1 0 N/A N/A N/A N/A N/A
329 * 0 1 0 1 1 N/A N/A N/A N/A N/A
330 * 0 1 1 X X N/A N/A N/A N/A N/A
331 * 1 X 0 0 0 N N - N Y
332 * 1 X 0 0 1 Y N WB N Y
333 * 1 X 0 1 0 Y N WT N Y
334 * 1 X 0 1 1 Y N WB Y Y
335 * 1 X 1 0 0 N N - Y Y
336 * 1 X 1 0 1 Y Y WB Y Y
337 * 1 X 1 1 0 Y Y WT Y Y
338 * 1 X 1 1 1 Y Y WB Y Y
343 * Cache attributes with L2 present, S = 1
344 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
345 * 0 0 0 0 0 N N - N N
346 * 0 0 0 0 1 N N - N Y
347 * 0 0 0 1 0 Y Y - N Y
348 * 0 0 0 1 1 Y Y WT Y Y
349 * 0 0 1 0 0 N N - Y Y
350 * 0 0 1 0 1 N N - N N
351 * 0 0 1 1 0 Y Y - - N
352 * 0 0 1 1 1 Y Y WT Y Y
353 * 0 1 0 0 0 N N - N N
354 * 0 1 0 0 1 N/A N/A N/A N/A N/A
355 * 0 1 0 1 0 N/A N/A N/A N/A N/A
356 * 0 1 0 1 1 N/A N/A N/A N/A N/A
357 * 0 1 1 X X N/A N/A N/A N/A N/A
358 * 1 X 0 0 0 N N - N Y
359 * 1 X 0 0 1 Y N - N Y
360 * 1 X 0 1 0 Y N - N Y
361 * 1 X 0 1 1 Y N - Y Y
362 * 1 X 1 0 0 N N - Y Y
363 * 1 X 1 0 1 Y Y WT Y Y
364 * 1 X 1 1 0 Y Y WT Y Y
365 * 1 X 1 1 1 Y Y WT Y Y
367 #endif /* !_MACHINE_PTE_H_ */