2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _ARM_LPC_LPCREG_H
30 #define _ARM_LPC_LPCREG_H
32 #define LPC_DEV_PHYS_BASE 0x40000000
33 #define LPC_DEV_P5_PHYS_BASE 0x20000000
34 #define LPC_DEV_P6_PHYS_BASE 0x30000000
35 #define LPC_DEV_SIZE 0x10000000
38 * Interrupt controller (from UM10326: LPC32x0 User manual, page 87)
41 #define LPC_INTC_MIC_ER 0x0000
42 #define LPC_INTC_MIC_RSR 0x0004
43 #define LPC_INTC_MIC_SR 0x0008
44 #define LPC_INTC_MIC_APR 0x000c
45 #define LPC_INTC_MIC_ATR 0x0010
46 #define LPC_INTC_MIC_ITR 0x0014
47 #define LPC_INTC_SIC1_ER 0x4000
48 #define LPC_INTC_SIC1_RSR 0x4004
49 #define LPC_INTC_SIC1_SR 0x4008
50 #define LPC_INTC_SIC1_APR 0x400c
51 #define LPC_INTC_SIC1_ATR 0x4010
52 #define LPC_INTC_SIC1_ITR 0x4014
53 #define LPC_INTC_SIC2_ER 0x8000
54 #define LPC_INTC_SIC2_RSR 0x8004
55 #define LPC_INTC_SIC2_SR 0x8008
56 #define LPC_INTC_SIC2_APR 0x800c
57 #define LPC_INTC_SIC2_ATR 0x8010
58 #define LPC_INTC_SIC2_ITR 0x8014
62 * Timer 0|1|2|3|4|5. (from UM10326: LPC32x0 User manual, page 540)
64 #define LPC_TIMER_IR 0x00
65 #define LPC_TIMER_TCR 0x04
66 #define LPC_TIMER_TCR_ENABLE (1 << 0)
67 #define LPC_TIMER_TCR_RESET (1 << 1)
68 #define LPC_TIMER_TC 0x08
69 #define LPC_TIMER_PR 0x0c
70 #define LPC_TIMER_PC 0x10
71 #define LPC_TIMER_MCR 0x14
72 #define LPC_TIMER_MCR_MR0I (1 << 0)
73 #define LPC_TIMER_MCR_MR0R (1 << 1)
74 #define LPC_TIMER_MCR_MR0S (1 << 2)
75 #define LPC_TIMER_MCR_MR1I (1 << 3)
76 #define LPC_TIMER_MCR_MR1R (1 << 4)
77 #define LPC_TIMER_MCR_MR1S (1 << 5)
78 #define LPC_TIMER_MCR_MR2I (1 << 6)
79 #define LPC_TIMER_MCR_MR2R (1 << 7)
80 #define LPC_TIMER_MCR_MR2S (1 << 8)
81 #define LPC_TIMER_MCR_MR3I (1 << 9)
82 #define LPC_TIMER_MCR_MR3R (1 << 10)
83 #define LPC_TIMER_MCR_MR3S (1 << 11)
84 #define LPC_TIMER_MR0 0x18
85 #define LPC_TIMER_CTCR 0x70
88 * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572)
90 #define LPC_WDTIM_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x3c000)
91 #define LPC_WDTIM_INT 0x00
92 #define LPC_WDTIM_CTRL 0x04
93 #define LPC_WDTIM_COUNTER 0x08
94 #define LPC_WDTIM_MCTRL 0x0c
95 #define LPC_WDTIM_MATCH0 0x10
96 #define LPC_WDTIM_EMR 0x14
97 #define LPC_WDTIM_PULSE 0x18
98 #define LPC_WDTIM_RES 0x1c
99 #define LPC_WDTIM_SIZE 0x20
102 * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58)
104 #define LPC_CLKPWR_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x4000)
105 #define LPC_CLKPWR_PWR_CTRL 0x44
106 #define LPC_CLKPWR_OSC_CTRL 0x4c
107 #define LPC_CLKPWR_SYSCLK_CTRL 0x50
108 #define LPC_CLKPWR_PLL397_CTRL 0x48
109 #define LPC_CLKPWR_HCLKPLL_CTRL 0x58
110 #define LPC_CLKPWR_HCLKDIV_CTRL 0x40
111 #define LPC_CLKPWR_TEST_CTRL 0xa4
112 #define LPC_CLKPWR_AUTOCLK_CTRL 0xec
113 #define LPC_CLKPWR_START_ER_PIN 0x30
114 #define LPC_CLKPWR_START_ER_INT 0x20
115 #define LPC_CLKPWR_P0_INTR_ER 0x18
116 #define LPC_CLKPWR_START_SR_PIN 0x38
117 #define LPC_CLKPWR_START_SR_INT 0x28
118 #define LPC_CLKPWR_START_RSR_PIN 0x34
119 #define LPC_CLKPWR_START_RSR_INT 0x24
120 #define LPC_CLKPWR_START_APR_PIN 0x3c
121 #define LPC_CLKPWR_START_APR_INT 0x2c
122 #define LPC_CLKPWR_USB_CTRL 0x64
123 #define LPC_CLKPWR_USB_CTRL_SLAVE_HCLK (1 << 24)
124 #define LPC_CLKPWR_USB_CTRL_I2C_EN (1 << 23)
125 #define LPC_CLKPWR_USB_CTRL_DEV_NEED_CLK_EN (1 << 22)
126 #define LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN (1 << 21)
127 #define LPC_CLKPWR_USB_CTRL_BUSKEEPER (1 << 19)
128 #define LPC_CLKPWR_USB_CTRL_CLK_EN2 (1 << 18)
129 #define LPC_CLKPWR_USB_CTRL_CLK_EN1 (1 << 17)
130 #define LPC_CLKPWR_USB_CTRL_PLL_PDOWN (1 << 16)
131 #define LPC_CLKPWR_USB_CTRL_BYPASS (1 << 15)
132 #define LPC_CLKPWR_USB_CTRL_DIRECT_OUT (1 << 14)
133 #define LPC_CLKPWR_USB_CTRL_FEEDBACK (1 << 13)
134 #define LPC_CLKPWR_USB_CTRL_POSTDIV(_x) ((_x & 0x3) << 11)
135 #define LPC_CLKPWR_USB_CTRL_PREDIV(_x) ((_x & 0x3) << 9)
136 #define LPC_CLKPWR_USB_CTRL_FDBKDIV(_x) (((_x-1) & 0xff) << 1)
137 #define LPC_CLKPWR_USB_CTRL_PLL_LOCK (1 << 0)
138 #define LPC_CLKPWR_USBDIV_CTRL 0x1c
139 #define LPC_CLKPWR_MS_CTRL 0x80
140 #define LPC_CLKPWR_MS_CTRL_DISABLE_SD (1 << 10)
141 #define LPC_CLKPWR_MS_CTRL_CLOCK_EN (1 << 9)
142 #define LPC_CLKPWR_MS_CTRL_MSSDIO23_PAD (1 << 8)
143 #define LPC_CLKPWR_MS_CTRL_MSSDIO1_PAD (1 << 7)
144 #define LPC_CLKPWR_MS_CTRL_MSSDIO0_PAD (1 << 6)
145 #define LPC_CLKPWR_MS_CTRL_SD_CLOCK (1 << 5)
146 #define LPC_CLKPWR_MS_CTRL_CLKDIV_MASK 0xf
147 #define LPC_CLKPWR_DMACLK_CTRL 0xe8
148 #define LPC_CLKPWR_DMACLK_CTRL_EN (1 << 0)
149 #define LPC_CLKPWR_FLASHCLK_CTRL 0xc8
150 #define LPC_CLKPWR_MACCLK_CTRL 0x90
151 #define LPC_CLKPWR_MACCLK_CTRL_REG (1 << 0)
152 #define LPC_CLKPWR_MACCLK_CTRL_SLAVE (1 << 1)
153 #define LPC_CLKPWR_MACCLK_CTRL_MASTER (1 << 2)
154 #define LPC_CLKPWR_MACCLK_CTRL_HDWINF(_n) ((_n & 0x3) << 3)
155 #define LPC_CLKPWR_LCDCLK_CTRL 0x54
156 #define LPC_CLKPWR_LCDCLK_CTRL_DISPTYPE (1 << 8)
157 #define LPC_CLKPWR_LCDCLK_CTRL_MODE(_n) ((_n & 0x3) << 6)
158 #define LPC_CLKPWR_LCDCLK_CTRL_MODE_12 0x0
159 #define LPC_CLKPWR_LCDCLK_CTRL_MODE_15 0x1
160 #define LPC_CLKPWR_LCDCLK_CTRL_MODE_16 0x2
161 #define LPC_CLKPWR_LCDCLK_CTRL_MODE_24 0x3
162 #define LPC_CLKPWR_LCDCLK_CTRL_HCLKEN (1 << 5)
163 #define LPC_CLKPWR_LCDCLK_CTRL_CLKDIV(_n) ((_n) & 0x1f)
164 #define LPC_CLKPWR_I2S_CTRL 0x7c
165 #define LPC_CLKPWR_SSP_CTRL 0x78
166 #define LPC_CLKPWR_SSP_CTRL_SSP1RXDMA (1 << 5)
167 #define LPC_CLKPWR_SSP_CTRL_SSP1TXDMA (1 << 4)
168 #define LPC_CLKPWR_SSP_CTRL_SSP0RXDMA (1 << 3)
169 #define LPC_CLKPWR_SSP_CTRL_SSP0TXDMA (1 << 2)
170 #define LPC_CLKPWR_SSP_CTRL_SSP1EN (1 << 1)
171 #define LPC_CLKPWR_SSP_CTRL_SSP0EN (1 << 0)
172 #define LPC_CLKPWR_SPI_CTRL 0xc4
173 #define LPC_CLKPWR_I2CCLK_CTRL 0xac
174 #define LPC_CLKPWR_TIMCLK_CTRL1 0xc0
175 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER4 (1 << 0)
176 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER5 (1 << 1)
177 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER0 (1 << 2)
178 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER1 (1 << 3)
179 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER2 (1 << 4)
180 #define LPC_CLKPWR_TIMCLK_CTRL1_TIMER3 (1 << 5)
181 #define LPC_CLKPWR_TIMCLK_CTRL1_MOTORCTL (1 << 6)
182 #define LPC_CLKPWR_TIMCLK_CTRL 0xbc
183 #define LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG (1 << 0)
184 #define LPC_CLKPWR_TIMCLK_CTRL_HSTIMER (1 << 1)
185 #define LPC_CLKPWR_ADCLK_CTRL 0xb4
186 #define LPC_CLKPWR_ADCLK_CTRL1 0x60
187 #define LPC_CLKPWR_KEYCLK_CTRL 0xb0
188 #define LPC_CLKPWR_PWMCLK_CTRL 0xb8
189 #define LPC_CLKPWR_UARTCLK_CTRL 0xe4
190 #define LPC_CLKPWR_POS0_IRAM_CTRL 0x110
191 #define LPC_CLKPWR_POS1_IRAM_CTRL 0x114
192 #define LPC_CLKPWR_SIZE 0x118
194 /* Additional UART registers in CLKPWR address space. */
195 #define LPC_CLKPWR_UART_U3CLK 0xd0
196 #define LPC_CLKPWR_UART_U4CLK 0xd4
197 #define LPC_CLKPWR_UART_U5CLK 0xd8
198 #define LPC_CLKPWR_UART_U6CLK 0xdc
199 #define LPC_CLKPWR_UART_UCLK_HCLK (1 << 16)
200 #define LPC_CLKPWR_UART_UCLK_X(_n) (((_n) & 0xff) << 8)
201 #define LPC_CLKPWR_UART_UCLK_Y(_n) ((_n) & 0xff)
202 #define LPC_CLKPWR_UART_IRDACLK 0xe0
204 /* Additional UART registers */
205 #define LPC_UART_BASE 0x80000
206 #define LPC_UART_CONTROL_BASE 0x54000
207 #define LPC_UART5_BASE 0x90000
208 #define LPC_UART_CTRL 0x00
209 #define LPC_UART_CLKMODE 0x04
210 #define LPC_UART_CLKMODE_UART3(_n) (((_n) & 0x3) << 4)
211 #define LPC_UART_CLKMODE_UART4(_n) (((_n) & 0x3) << 6)
212 #define LPC_UART_CLKMODE_UART5(_n) (((_n) & 0x3) << 8)
213 #define LPC_UART_CLKMODE_UART6(_n) (((_n) & 0x3) << 10)
214 #define LPC_UART_LOOP 0x08
215 #define LPC_UART_CONTROL_SIZE 0x0c
216 #define LPC_UART_FIFOSIZE 64
219 * Real time clock. (from UM10326: LPC32x0 User manual, page 566)
221 #define LPC_RTC_UCOUNT 0x00
222 #define LPC_RTC_DCOUNT 0x04
223 #define LPC_RTC_MATCH0 0x08
224 #define LPC_RTC_MATCH1 0x0c
225 #define LPC_RTC_CTRL 0x10
226 #define LPC_RTC_CTRL_ONSW (1 << 7)
227 #define LPC_RTC_CTRL_DISABLE (1 << 6)
228 #define LPC_RTC_CTRL_RTCRESET (1 << 4)
229 #define LPC_RTC_CTRL_MATCH0ONSW (1 << 3)
230 #define LPC_RTC_CTRL_MATCH1ONSW (1 << 2)
231 #define LPC_RTC_CTRL_MATCH1INTR (1 << 1)
232 #define LPC_RTC_CTRL_MATCH0INTR (1 << 0)
233 #define LPC_RTC_INTSTAT 0x14
234 #define LPC_RTC_KEY 0x18
235 #define LPC_RTC_SRAM_BEGIN 0x80
236 #define LPC_RTC_SRAM_END 0xff
239 * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436)
241 #define LPC_SD_PHYS_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000)
242 #define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz
243 #define LPC_SD_POWER 0x00
244 #define LPC_SD_POWER_OPENDRAIN (1 << 6)
245 #define LPC_SD_POWER_CTRL_OFF 0x00
246 #define LPC_SD_POWER_CTRL_UP 0x02
247 #define LPC_SD_POWER_CTRL_ON 0x03
248 #define LPC_SD_CLOCK 0x04
249 #define LPC_SD_CLOCK_WIDEBUS (1 << 11)
250 #define LPC_SD_CLOCK_BYPASS (1 << 10)
251 #define LPC_SD_CLOCK_PWRSAVE (1 << 9)
252 #define LPC_SD_CLOCK_ENABLE (1 << 8)
253 #define LPC_SD_CLOCK_CLKDIVMASK 0xff
254 #define LPC_SD_ARGUMENT 0x08
255 #define LPC_SD_COMMAND 0x0c
256 #define LPC_SD_COMMAND_ENABLE (1 << 10)
257 #define LPC_SD_COMMAND_PENDING (1 << 9)
258 #define LPC_SD_COMMAND_INTERRUPT (1 << 8)
259 #define LPC_SD_COMMAND_LONGRSP (1 << 7)
260 #define LPC_SD_COMMAND_RESPONSE (1 << 6)
261 #define LPC_SD_COMMAND_CMDINDEXMASK 0x3f
262 #define LPC_SD_RESPCMD 0x10
263 #define LPC_SD_RESP0 0x14
264 #define LPC_SD_RESP1 0x18
265 #define LPC_SD_RESP2 0x1c
266 #define LPC_SD_RESP3 0x20
267 #define LPC_SD_DATATIMER 0x24
268 #define LPC_SD_DATALENGTH 0x28
269 #define LPC_SD_DATACTRL 0x2c
270 #define LPC_SD_DATACTRL_BLOCKSIZESHIFT 4
271 #define LPC_SD_DATACTRL_BLOCKSIZEMASK 0xf
272 #define LPC_SD_DATACTRL_DMAENABLE (1 << 3)
273 #define LPC_SD_DATACTRL_MODE (1 << 2)
274 #define LPC_SD_DATACTRL_WRITE (0 << 1)
275 #define LPC_SD_DATACTRL_READ (1 << 1)
276 #define LPC_SD_DATACTRL_ENABLE (1 << 0)
277 #define LPC_SD_DATACNT 0x30
278 #define LPC_SD_STATUS 0x34
279 #define LPC_SD_STATUS_RXDATAAVLBL (1 << 21)
280 #define LPC_SD_STATUS_TXDATAAVLBL (1 << 20)
281 #define LPC_SD_STATUS_RXFIFOEMPTY (1 << 19)
282 #define LPC_SD_STATUS_TXFIFOEMPTY (1 << 18)
283 #define LPC_SD_STATUS_RXFIFOFULL (1 << 17)
284 #define LPC_SD_STATUS_TXFIFOFULL (1 << 16)
285 #define LPC_SD_STATUS_RXFIFOHALFFULL (1 << 15)
286 #define LPC_SD_STATUS_TXFIFOHALFEMPTY (1 << 14)
287 #define LPC_SD_STATUS_RXACTIVE (1 << 13)
288 #define LPC_SD_STATUS_TXACTIVE (1 << 12)
289 #define LPC_SD_STATUS_CMDACTIVE (1 << 11)
290 #define LPC_SD_STATUS_DATABLOCKEND (1 << 10)
291 #define LPC_SD_STATUS_STARTBITERR (1 << 9)
292 #define LPC_SD_STATUS_DATAEND (1 << 8)
293 #define LPC_SD_STATUS_CMDSENT (1 << 7)
294 #define LPC_SD_STATUS_CMDRESPEND (1 << 6)
295 #define LPC_SD_STATUS_RXOVERRUN (1 << 5)
296 #define LPC_SD_STATUS_TXUNDERRUN (1 << 4)
297 #define LPC_SD_STATUS_DATATIMEOUT (1 << 3)
298 #define LPC_SD_STATUS_CMDTIMEOUT (1 << 2)
299 #define LPC_SD_STATUS_DATACRCFAIL (1 << 1)
300 #define LPC_SD_STATUS_CMDCRCFAIL (1 << 0)
301 #define LPC_SD_CLEAR 0x38
302 #define LPC_SD_MASK0 0x03c
303 #define LPC_SD_MASK1 0x40
304 #define LPC_SD_FIFOCNT 0x48
305 #define LPC_SD_FIFO 0x80
308 * USB OTG controller (from UM10326: LPC32x0 User manual, page 410)
310 #define LPC_OTG_INT_STATUS 0x100
311 #define LPC_OTG_INT_ENABLE 0x104
312 #define LPC_OTG_INT_SET 0x108
313 #define LPC_OTG_INT_CLEAR 0x10c
314 #define LPC_OTG_STATUS 0x110
315 #define LPC_OTG_STATUS_ATOB_HNP_TRACK (1 << 9)
316 #define LPC_OTG_STATUS_BTOA_HNP_TACK (1 << 8)
317 #define LPC_OTG_STATUS_TRANSP_I2C_EN (1 << 7)
318 #define LPC_OTG_STATUS_TIMER_RESET (1 << 6)
319 #define LPC_OTG_STATUS_TIMER_EN (1 << 5)
320 #define LPC_OTG_STATUS_TIMER_MODE (1 << 4)
321 #define LPC_OTG_STATUS_TIMER_SCALE (1 << 2)
322 #define LPC_OTG_STATUS_HOST_EN (1 << 0)
323 #define LPC_OTG_TIMER 0x114
324 #define LPC_OTG_I2C_TXRX 0x300
325 #define LPC_OTG_I2C_STATUS 0x304
326 #define LPC_OTG_I2C_STATUS_TFE (1 << 11)
327 #define LPC_OTG_I2C_STATUS_TFF (1 << 10)
328 #define LPC_OTG_I2C_STATUS_RFE (1 << 9)
329 #define LPC_OTG_I2C_STATUS_RFF (1 << 8)
330 #define LPC_OTG_I2C_STATUS_SDA (1 << 7)
331 #define LPC_OTG_I2C_STATUS_SCL (1 << 6)
332 #define LPC_OTG_I2C_STATUS_ACTIVE (1 << 5)
333 #define LPC_OTG_I2C_STATUS_DRSI (1 << 4)
334 #define LPC_OTG_I2C_STATUS_DRMI (1 << 3)
335 #define LPC_OTG_I2C_STATUS_NAI (1 << 2)
336 #define LPC_OTG_I2C_STATUS_AFI (1 << 1)
337 #define LPC_OTG_I2C_STATUS_TDI (1 << 0)
338 #define LPC_OTG_I2C_CTRL 0x308
339 #define LPC_OTG_I2C_CTRL_SRST (1 << 8)
340 #define LPC_OTG_I2C_CTRL_TFFIE (1 << 7)
341 #define LPC_OTG_I2C_CTRL_RFDAIE (1 << 6)
342 #define LPC_OTG_I2C_CTRL_RFFIE (1 << 5)
343 #define LPC_OTG_I2C_CTRL_DRSIE (1 << 4)
344 #define LPC_OTG_I2C_CTRL_DRMIE (1 << 3)
345 #define LPC_OTG_I2C_CTRL_NAIE (1 << 2)
346 #define LPC_OTG_I2C_CTRL_AFIE (1 << 1)
347 #define LPC_OTG_I2C_CTRL_TDIE (1 << 0)
348 #define LPC_OTG_I2C_CLKHI 0x30c
349 #define LPC_OTG_I2C_CLKLO 0x310
350 #define LPC_OTG_CLOCK_CTRL 0xff4
351 #define LPC_OTG_CLOCK_CTRL_AHB_EN (1 << 4)
352 #define LPC_OTG_CLOCK_CTRL_OTG_EN (1 << 3)
353 #define LPC_OTG_CLOCK_CTRL_I2C_EN (1 << 2)
354 #define LPC_OTG_CLOCK_CTRL_DEV_EN (1 << 1)
355 #define LPC_OTG_CLOCK_CTRL_HOST_EN (1 << 0)
356 #define LPC_OTG_CLOCK_STATUS 0xff8
359 * ISP3101 USB transceiver registers
361 #define LPC_ISP3101_I2C_ADDR 0x2d
362 #define LPC_ISP3101_MODE_CONTROL_1 0x04
363 #define LPC_ISP3101_MC1_SPEED_REG (1 << 0)
364 #define LPC_ISP3101_MC1_SUSPEND_REG (1 << 1)
365 #define LPC_ISP3101_MC1_DAT_SE0 (1 << 2)
366 #define LPC_ISP3101_MC1_TRANSPARENT (1 << 3)
367 #define LPC_ISP3101_MC1_BDIS_ACON_EN (1 << 4)
368 #define LPC_ISP3101_MC1_OE_INT_EN (1 << 5)
369 #define LPC_ISP3101_MC1_UART_EN (1 << 6)
370 #define LPC_ISP3101_MODE_CONTROL_2 0x12
371 #define LPC_ISP3101_MC2_GLOBAL_PWR_DN (1 << 0)
372 #define LPC_ISP3101_MC2_SPD_SUSP_CTRL (1 << 1)
373 #define LPC_ISP3101_MC2_BI_DI (1 << 2)
374 #define LPC_ISP3101_MC2_TRANSP_BDIR0 (1 << 3)
375 #define LPC_ISP3101_MC2_TRANSP_BDIR1 (1 << 4)
376 #define LPC_ISP3101_MC2_AUDIO_EN (1 << 5)
377 #define LPC_ISP3101_MC2_PSW_EN (1 << 6)
378 #define LPC_ISP3101_MC2_EN2V7 (1 << 7)
379 #define LPC_ISP3101_OTG_CONTROL_1 0x06
380 #define LPC_ISP3101_OTG1_DP_PULLUP (1 << 0)
381 #define LPC_ISP3101_OTG1_DM_PULLUP (1 << 1)
382 #define LPC_ISP3101_OTG1_DP_PULLDOWN (1 << 2)
383 #define LPC_ISP3101_OTG1_DM_PULLDOWN (1 << 3)
384 #define LPC_ISP3101_OTG1_ID_PULLDOWN (1 << 4)
385 #define LPC_ISP3101_OTG1_VBUS_DRV (1 << 5)
386 #define LPC_ISP3101_OTG1_VBUS_DISCHRG (1 << 6)
387 #define LPC_ISP3101_OTG1_VBUS_CHRG (1 << 7)
388 #define LPC_ISP3101_OTG_CONTROL_2 0x10
389 #define LPC_ISP3101_OTG_INTR_LATCH 0x0a
390 #define LPC_ISP3101_OTG_INTR_FALLING 0x0c
391 #define LPC_ISP3101_OTG_INTR_RISING 0x0e
392 #define LPC_ISP3101_REG_CLEAR_ADDR 0x01
395 * LCD Controller (from UM10326: LPC32x0 User manual, page 229)
397 #define LPC_LCD_TIMH 0x00
398 #define LPC_LCD_TIMH_HBP(_n) (((_n) & 0xff) << 24)
399 #define LPC_LCD_TIMH_HFP(_n) (((_n) & 0xff) << 16)
400 #define LPC_LCD_TIMH_HSW(_n) (((_n) & 0xff) << 8)
401 #define LPC_LCD_TIMH_PPL(_n) (((_n) / 16 - 1) << 2)
402 #define LPC_LCD_TIMV 0x04
403 #define LPC_LCD_TIMV_VBP(_n) (((_n) & 0xff) << 24)
404 #define LPC_LCD_TIMV_VFP(_n) (((_n) & 0xff) << 16)
405 #define LPC_LCD_TIMV_VSW(_n) (((_n) & 0x3f) << 10)
406 #define LPC_LCD_TIMV_LPP(_n) ((_n) & 0x1ff)
407 #define LPC_LCD_POL 0x08
408 #define LPC_LCD_POL_PCD_HI (((_n) & 0x1f) << 27)
409 #define LPC_LCD_POL_BCD (1 << 26)
410 #define LPC_LCD_POL_CPL(_n) (((_n) & 0x3ff) << 16)
411 #define LPC_LCD_POL_IOE (1 << 14)
412 #define LPC_LCD_POL_IPC (1 << 13)
413 #define LPC_LCD_POL_IHS (1 << 12)
414 #define LPC_LCD_POL_IVS (1 << 11)
415 #define LPC_LCD_POL_ACB(_n) ((_n & 0x1f) << 6)
416 #define LPC_LCD_POL_CLKSEL (1 << 5)
417 #define LPC_LCD_POL_PCD_LO(_n) ((_n) & 0x1f)
418 #define LPC_LCD_LE 0x0c
419 #define LPC_LCD_LE_LEE (1 << 16)
420 #define LPC_LCD_LE_LED ((_n) & 0x7f)
421 #define LPC_LCD_UPBASE 0x10
422 #define LPC_LCD_LPBASE 0x14
423 #define LPC_LCD_CTRL 0x18
424 #define LPC_LCD_CTRL_WATERMARK (1 << 16)
425 #define LPC_LCD_CTRL_LCDVCOMP(_n) (((_n) & 0x3) << 12)
426 #define LPC_LCD_CTRL_LCDPWR (1 << 11)
427 #define LPC_LCD_CTRL_BEPO (1 << 10)
428 #define LPC_LCD_CTRL_BEBO (1 << 9)
429 #define LPC_LCD_CTRL_BGR (1 << 8)
430 #define LPC_LCD_CTRL_LCDDUAL (1 << 7)
431 #define LPC_LCD_CTRL_LCDMONO8 (1 << 6)
432 #define LPC_LCD_CTRL_LCDTFT (1 << 5)
433 #define LPC_LCD_CTRL_LCDBW (1 << 4)
434 #define LPC_LCD_CTRL_LCDBPP(_n) (((_n) & 0x7) << 1)
435 #define LPC_LCD_CTRL_BPP1 0
436 #define LPC_LCD_CTRL_BPP2 1
437 #define LPC_LCD_CTRL_BPP4 2
438 #define LPC_LCD_CTRL_BPP8 3
439 #define LPC_LCD_CTRL_BPP16 4
440 #define LPC_LCD_CTRL_BPP24 5
441 #define LPC_LCD_CTRL_BPP16_565 6
442 #define LPC_LCD_CTRL_BPP12_444 7
443 #define LPC_LCD_CTRL_LCDEN (1 << 0)
444 #define LPC_LCD_INTMSK 0x1c
445 #define LPC_LCD_INTRAW 0x20
446 #define LPC_LCD_INTSTAT 0x24
447 #define LPC_LCD_INTCLR 0x28
448 #define LPC_LCD_UPCURR 0x2c
449 #define LPC_LCD_LPCURR 0x30
450 #define LPC_LCD_PAL 0x200
451 #define LPC_LCD_CRSR_IMG 0x800
452 #define LPC_LCD_CRSR_CTRL 0xc00
453 #define LPC_LCD_CRSR_CFG 0xc04
454 #define LPC_LCD_CRSR_PAL0 0xc08
455 #define LPC_LCD_CRSR_PAL1 0xc0c
456 #define LPC_LCD_CRSR_XY 0xc10
457 #define LPC_LCD_CRSR_CLIP 0xc14
458 #define LPC_LCD_CRSR_INTMSK 0xc20
459 #define LPC_LCD_CRSR_INTCLR 0xc24
460 #define LPC_LCD_CRSR_INTRAW 0xc28
461 #define LPC_LCD_CRSR_INTSTAT 0xc2c
464 * SPI interface (from UM10326: LPC32x0 User manual, page 483)
466 #define LPC_SPI_GLOBAL 0x00
467 #define LPC_SPI_GLOBAL_RST (1 << 1)
468 #define LPC_SPI_GLOBAL_ENABLE (1 << 0)
469 #define LPC_SPI_CON 0x04
470 #define LPC_SPI_CON_UNIDIR (1 << 23)
471 #define LPC_SPI_CON_BHALT (1 << 22)
472 #define LPC_SPI_CON_BPOL (1 << 21)
473 #define LPC_SPI_CON_MSB (1 << 19)
474 #define LPC_SPI_CON_MODE(_n) ((_n & 0x3) << 16)
475 #define LPC_SPI_CON_RXTX (1 << 15)
476 #define LPC_SPI_CON_THR (1 << 14)
477 #define LPC_SPI_CON_SHIFT_OFF (1 << 13)
478 #define LPC_SPI_CON_BITNUM(_n) ((_n & 0xf) << 9)
479 #define LPC_SPI_CON_MS (1 << 7)
480 #define LPC_SPI_CON_RATE(_n) (_n & 0x7f)
481 #define LPC_SPI_FRM 0x08
482 #define LPC_SPI_IER 0x0c
483 #define LPC_SPI_IER_INTEOT (1 << 1)
484 #define LPC_SPI_IER_INTTHR (1 << 0)
485 #define LPC_SPI_STAT 0x10
486 #define LPC_SPI_STAT_INTCLR (1 << 8)
487 #define LPC_SPI_STAT_EOT (1 << 7)
488 #define LPC_SPI_STAT_BUSYLEV (1 << 6)
489 #define LPC_SPI_STAT_SHIFTACT (1 << 3)
490 #define LPC_SPI_STAT_BF (1 << 2)
491 #define LPC_SPI_STAT_THR (1 << 1)
492 #define LPC_SPI_STAT_BE (1 << 0)
493 #define LPC_SPI_DAT 0x14
494 #define LPC_SPI_TIM_CTRL 0x400
495 #define LPC_SPI_TIM_COUNT 0x404
496 #define LPC_SPI_TIM_STAT 0x408
499 * SSP interface (from UM10326: LPC32x0 User manual, page 500)
501 #define LPC_SSP0_BASE 0x4c00
502 #define LPC_SSP1_BASE 0xc000
503 #define LPC_SSP_CR0 0x00
504 #define LPC_SSP_CR0_DSS(_n) ((_n-1) & 0xf)
505 #define LPC_SSP_CR0_TI (1 << 4)
506 #define LPC_SSP_CR0_MICROWIRE (1 << 5)
507 #define LPC_SSP_CR0_CPOL (1 << 6)
508 #define LPC_SSP_CR0_CPHA (1 << 7)
509 #define LPC_SSP_CR0_SCR(_n) ((_x & & 0xff) << 8)
510 #define LPC_SSP_CR1 0x04
511 #define LPC_SSP_CR1_LBM (1 << 0)
512 #define LPC_SSP_CR1_SSE (1 << 1)
513 #define LPC_SSP_CR1_MS (1 << 2)
514 #define LPC_SSP_CR1_SOD (1 << 3)
515 #define LPC_SSP_DR 0x08
516 #define LPC_SSP_SR 0x0c
517 #define LPC_SSP_SR_TFE (1 << 0)
518 #define LPC_SSP_SR_TNF (1 << 1)
519 #define LPC_SSP_SR_RNE (1 << 2)
520 #define LPC_SSP_SR_RFF (1 << 3)
521 #define LPC_SSP_SR_BSY (1 << 4)
522 #define LPC_SSP_CPSR 0x10
523 #define LPC_SSP_IMSC 0x14
524 #define LPC_SSP_IMSC_RORIM (1 << 0)
525 #define LPC_SSP_IMSC_RTIM (1 << 1)
526 #define LPC_SSP_IMSC_RXIM (1 << 2)
527 #define LPC_SSP_IMSC_TXIM (1 << 3)
528 #define LPC_SSP_RIS 0x18
529 #define LPC_SSP_RIS_RORRIS (1 << 0)
530 #define LPC_SSP_RIS_RTRIS (1 << 1)
531 #define LPC_SSP_RIS_RXRIS (1 << 2)
532 #define LPC_SSP_RIS_TXRIS (1 << 3)
533 #define LPC_SSP_MIS 0x1c
534 #define LPC_SSP_ICR 0x20
535 #define LPC_SSP_DMACR 0x24
538 * GPIO (from UM10326: LPC32x0 User manual, page 606)
540 #define LPC_GPIO_PHYS_BASE (LPC_DEV_PHYS_BASE + 0x28000)
541 #define LPC_GPIO_P0_COUNT 8
542 #define LPC_GPIO_P1_COUNT 24
543 #define LPC_GPIO_P2_COUNT 13
544 #define LPC_GPIO_P3_COUNT 52
545 #define LPC_GPIO_P0_INP_STATE 0x40
546 #define LPC_GPIO_P0_OUTP_SET 0x44
547 #define LPC_GPIO_P0_OUTP_CLR 0x48
548 #define LPC_GPIO_P0_OUTP_STATE 0x4c
549 #define LPC_GPIO_P0_DIR_SET 0x50
550 #define LPC_GPIO_P0_DIR_CLR 0x54
551 #define LPC_GPIO_P0_DIR_STATE 0x58
552 #define LPC_GPIO_P1_INP_STATE 0x60
553 #define LPC_GPIO_P1_OUTP_SET 0x64
554 #define LPC_GPIO_P1_OUTP_CLR 0x68
555 #define LPC_GPIO_P1_OUTP_STATE 0x6c
556 #define LPC_GPIO_P1_DIR_SET 0x70
557 #define LPC_GPIO_P1_DIR_CLR 0x74
558 #define LPC_GPIO_P1_DIR_STATE 0x78
559 #define LPC_GPIO_P2_INP_STATE 0x1c
560 #define LPC_GPIO_P2_OUTP_SET 0x20
561 #define LPC_GPIO_P2_OUTP_CLR 0x24
562 #define LPC_GPIO_P2_DIR_SET 0x10
563 #define LPC_GPIO_P2_DIR_CLR 0x14
564 #define LPC_GPIO_P2_DIR_STATE 0x14
565 #define LPC_GPIO_P3_INP_STATE 0x00
566 #define LPC_GPIO_P3_OUTP_SET 0x04
567 #define LPC_GPIO_P3_OUTP_CLR 0x08
568 #define LPC_GPIO_P3_OUTP_STATE 0x0c
569 #define LPC_GPIO_SIZE 0x80
571 /* Aliases for logical pin numbers: */
572 #define LPC_GPIO_GPI_00(_n) (0 + _n)
573 #define LPC_GPIO_GPI_15(_n) (10 + _n)
574 #define LPC_GPIO_GPI_25 (19)
575 #define LPC_GPIO_GPI_27(_n) (20 + _n)
576 #define LPC_GPIO_GPO_00(_n) (22 + _n)
577 #define LPC_GPIO_GPIO_00(_n) (46 + _n)
578 /* SPI devices chip selects: */
579 #define SSD1289_CS_PIN LPC_GPIO_GPO_00(4)
580 #define SSD1289_DC_PIN LPC_GPIO_GPO_00(5)
581 #define ADS7846_CS_PIN LPC_GPIO_GPO_00(11)
582 #define ADS7846_INTR_PIN LPC_GPIO_GPIO_00(0)
585 * GPDMA controller (from UM10326: LPC32x0 User manual, page 106)
587 #define LPC_DMAC_INTSTAT 0x00
588 #define LPC_DMAC_INTTCSTAT 0x04
589 #define LPC_DMAC_INTTCCLEAR 0x08
590 #define LPC_DMAC_INTERRSTAT 0x0c
591 #define LPC_DMAC_INTERRCLEAR 0x10
592 #define LPC_DMAC_RAWINTTCSTAT 0x14
593 #define LPC_DMAC_RAWINTERRSTAT 0x18
594 #define LPC_DMAC_ENABLED_CHANNELS 0x1c
595 #define LPC_DMAC_SOFTBREQ 0x20
596 #define LPC_DMAC_SOFTSREQ 0x24
597 #define LPC_DMAC_SOFTLBREQ 0x28
598 #define LPC_DMAC_SOFTLSREQ 0x2c
599 #define LPC_DMAC_CONFIG 0x30
600 #define LPC_DMAC_CONFIG_M1 (1 << 2)
601 #define LPC_DMAC_CONFIG_M0 (1 << 1)
602 #define LPC_DMAC_CONFIG_ENABLE (1 << 0)
603 #define LPC_DMAC_CHADDR(_n) (0x100 + (_n * 0x20))
604 #define LPC_DMAC_CHNUM 8
605 #define LPC_DMAC_CHSIZE 0x20
606 #define LPC_DMAC_CH_SRCADDR 0x00
607 #define LPC_DMAC_CH_DSTADDR 0x04
608 #define LPC_DMAC_CH_LLI 0x08
609 #define LPC_DMAC_CH_LLI_AHB1 (1 << 0)
610 #define LPC_DMAC_CH_CONTROL 0x0c
611 #define LPC_DMAC_CH_CONTROL_I (1U << 31)
612 #define LPC_DMAC_CH_CONTROL_DI (1 << 27)
613 #define LPC_DMAC_CH_CONTROL_SI (1 << 26)
614 #define LPC_DMAC_CH_CONTROL_D (1 << 25)
615 #define LPC_DMAC_CH_CONTROL_S (1 << 24)
616 #define LPC_DMAC_CH_CONTROL_WIDTH_4 2
617 #define LPC_DMAC_CH_CONTROL_DWIDTH(_n) ((_n & 0x7) << 21)
618 #define LPC_DMAC_CH_CONTROL_SWIDTH(_n) ((_n & 0x7) << 18)
619 #define LPC_DMAC_CH_CONTROL_BURST_8 2
620 #define LPC_DMAC_CH_CONTROL_DBSIZE(_n) ((_n & 0x7) << 15)
621 #define LPC_DMAC_CH_CONTROL_SBSIZE(_n) ((_n & 0x7) << 12)
622 #define LPC_DMAC_CH_CONTROL_XFERLEN(_n) (_n & 0xfff)
623 #define LPC_DMAC_CH_CONFIG 0x10
624 #define LPC_DMAC_CH_CONFIG_H (1 << 18)
625 #define LPC_DMAC_CH_CONFIG_A (1 << 17)
626 #define LPC_DMAC_CH_CONFIG_L (1 << 16)
627 #define LPC_DMAC_CH_CONFIG_ITC (1 << 15)
628 #define LPC_DMAC_CH_CONFIG_IE (1 << 14)
629 #define LPC_DMAC_CH_CONFIG_FLOWCNTL(_n) ((_n & 0x7) << 11)
630 #define LPC_DMAC_CH_CONFIG_DESTP(_n) ((_n & 0x1f) << 6)
631 #define LPC_DMAC_CH_CONFIG_SRCP(_n) ((_n & 0x1f) << 1)
632 #define LPC_DMAC_CH_CONFIG_E (1 << 0)
634 /* DMA flow control values */
635 #define LPC_DMAC_FLOW_D_M2M 0
636 #define LPC_DMAC_FLOW_D_M2P 1
637 #define LPC_DMAC_FLOW_D_P2M 2
638 #define LPC_DMAC_FLOW_D_P2P 3
639 #define LPC_DMAC_FLOW_DP_P2P 4
640 #define LPC_DMAC_FLOW_P_M2P 5
641 #define LPC_DMAC_FLOW_P_P2M 6
642 #define LPC_DMAC_FLOW_SP_P2P 7
644 /* DMA peripheral ID's */
645 #define LPC_DMAC_I2S0_DMA0_ID 0
646 #define LPC_DMAC_NAND_ID 1
647 #define LPC_DMAC_IS21_DMA0_ID 2
648 #define LPC_DMAC_SSP1_ID 3
649 #define LPC_DMAC_SPI2_ID 3
650 #define LPC_DMAC_SD_ID 4
651 #define LPC_DMAC_UART1_TX_ID 5
652 #define LPC_DMAC_UART1_RX_ID 6
653 #define LPC_DMAC_UART2_TX_ID 7
654 #define LPC_DMAC_UART2_RX_ID 8
655 #define LPC_DMAC_UART7_TX_ID 9
656 #define LPC_DMAC_UART7_RX_ID 10
657 #define LPC_DMAC_I2S1_DMA1_ID 10
658 #define LPC_DMAC_SPI1_ID 11
659 #define LPC_DMAC_SSP1_TX_ID 11
660 #define LPC_DMAC_NAND2_ID 12
661 #define LPC_DMAC_I2S0_DMA1_ID 13
662 #define LPC_DMAC_SSP0_RX 14
663 #define LPC_DMAC_SSP0_TX 15
665 #endif /* _ARM_LPC_LPCREG_H */