2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended to Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/module.h>
41 #include <machine/bus.h>
42 #include <machine/intr.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
47 #include <arm/mv/mvreg.h>
48 #include <arm/mv/mvvar.h>
51 struct resource * ic_res[1];
52 bus_space_tag_t ic_bst;
53 bus_space_handle_t ic_bsh;
58 static struct resource_spec mv_ic_spec[] = {
59 { SYS_RES_MEMORY, 0, RF_ACTIVE },
63 static struct mv_ic_softc *mv_ic_sc = NULL;
65 static int mv_ic_probe(device_t);
66 static int mv_ic_attach(device_t);
68 uint32_t mv_ic_get_cause(void);
69 uint32_t mv_ic_get_mask(void);
70 void mv_ic_set_mask(uint32_t);
71 uint32_t mv_ic_get_cause_hi(void);
72 uint32_t mv_ic_get_mask_hi(void);
73 void mv_ic_set_mask_hi(uint32_t);
74 uint32_t mv_ic_get_cause_error(void);
75 uint32_t mv_ic_get_mask_error(void);
76 void mv_ic_set_mask_error(uint32_t);
77 static void arm_mask_irq_all(void);
80 mv_ic_probe(device_t dev)
83 if (!ofw_bus_status_okay(dev))
86 if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
89 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
94 mv_ic_attach(device_t dev)
96 struct mv_ic_softc *sc;
97 uint32_t dev_id, rev_id;
100 sc = (struct mv_ic_softc *)device_get_softc(dev);
102 if (mv_ic_sc != NULL)
106 soc_id(&dev_id, &rev_id);
108 sc->ic_high_regs = 0;
109 sc->ic_error_regs = 0;
111 if (dev_id == MV_DEV_88F6281 ||
112 dev_id == MV_DEV_88F6282 ||
113 dev_id == MV_DEV_MV78100 ||
114 dev_id == MV_DEV_MV78100_Z0)
115 sc->ic_high_regs = 1;
117 if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
118 sc->ic_error_regs = 1;
120 error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
122 device_printf(dev, "could not allocate resources\n");
126 sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
127 sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
129 /* Mask all interrupts */
135 static device_method_t mv_ic_methods[] = {
136 DEVMETHOD(device_probe, mv_ic_probe),
137 DEVMETHOD(device_attach, mv_ic_attach),
141 static driver_t mv_ic_driver = {
144 sizeof(struct mv_ic_softc),
147 static devclass_t mv_ic_devclass;
149 DRIVER_MODULE(ic, simplebus, mv_ic_driver, mv_ic_devclass, 0, 0);
152 arm_get_next_irq(int last)
157 filt = ~((last >= 0) ? (2 << last) - 1 : 0);
158 irq = mv_ic_get_cause() & mv_ic_get_mask();
160 next = ffs(irq & filt) - 1;
163 if (mv_ic_sc->ic_high_regs) {
164 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
165 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
167 next = ffs(irq & filt) + 31;
171 if (mv_ic_sc->ic_error_regs) {
172 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
173 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
175 next = ffs(irq & filt) + 63;
182 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
187 arm_mask_irq_all(void)
192 if (mv_ic_sc->ic_high_regs)
193 mv_ic_set_mask_hi(0);
195 if (mv_ic_sc->ic_error_regs)
196 mv_ic_set_mask_error(0);
200 arm_mask_irq(uintptr_t nb)
205 mr = mv_ic_get_mask();
209 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
210 mr = mv_ic_get_mask_hi();
211 mr &= ~(1 << (nb - 32));
212 mv_ic_set_mask_hi(mr);
214 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
215 mr = mv_ic_get_mask_error();
216 mr &= ~(1 << (nb - 64));
217 mv_ic_set_mask_error(mr);
222 arm_unmask_irq(uintptr_t nb)
227 mr = mv_ic_get_mask();
231 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
232 mr = mv_ic_get_mask_hi();
233 mr |= (1 << (nb - 32));
234 mv_ic_set_mask_hi(mr);
236 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
237 mr = mv_ic_get_mask_error();
238 mr |= (1 << (nb - 64));
239 mv_ic_set_mask_error(mr);
244 mv_ic_set_mask(uint32_t val)
247 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
255 return (bus_space_read_4(mv_ic_sc->ic_bst,
256 mv_ic_sc->ic_bsh, IRQ_MASK));
260 mv_ic_get_cause(void)
263 return (bus_space_read_4(mv_ic_sc->ic_bst,
264 mv_ic_sc->ic_bsh, IRQ_CAUSE));
268 mv_ic_set_mask_hi(uint32_t val)
271 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
276 mv_ic_get_mask_hi(void)
279 return (bus_space_read_4(mv_ic_sc->ic_bst,
280 mv_ic_sc->ic_bsh, IRQ_MASK_HI));
284 mv_ic_get_cause_hi(void)
287 return (bus_space_read_4(mv_ic_sc->ic_bst,
288 mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
292 mv_ic_set_mask_error(uint32_t val)
295 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
296 IRQ_MASK_ERROR, val);
300 mv_ic_get_mask_error(void)
303 return (bus_space_read_4(mv_ic_sc->ic_bst,
304 mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
308 mv_ic_get_cause_error(void)
311 return (bus_space_read_4(mv_ic_sc->ic_bst,
312 mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));