2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended to Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <machine/bus.h>
41 #include <machine/intr.h>
43 #include <arm/mv/mvreg.h>
44 #include <arm/mv/mvvar.h>
47 struct resource * ic_res[1];
48 bus_space_tag_t ic_bst;
49 bus_space_handle_t ic_bsh;
54 static struct resource_spec mv_ic_spec[] = {
55 { SYS_RES_MEMORY, 0, RF_ACTIVE },
59 static struct mv_ic_softc *mv_ic_sc = NULL;
61 static int mv_ic_probe(device_t);
62 static int mv_ic_attach(device_t);
64 uint32_t mv_ic_get_cause(void);
65 uint32_t mv_ic_get_mask(void);
66 void mv_ic_set_mask(uint32_t);
67 uint32_t mv_ic_get_cause_hi(void);
68 uint32_t mv_ic_get_mask_hi(void);
69 void mv_ic_set_mask_hi(uint32_t);
70 uint32_t mv_ic_get_cause_error(void);
71 uint32_t mv_ic_get_mask_error(void);
72 void mv_ic_set_mask_error(uint32_t);
73 static void arm_mask_irq_all(void);
76 mv_ic_probe(device_t dev)
79 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
84 mv_ic_attach(device_t dev)
86 struct mv_ic_softc *sc;
87 uint32_t dev_id, rev_id;
90 sc = (struct mv_ic_softc *)device_get_softc(dev);
96 soc_id(&dev_id, &rev_id);
99 sc->ic_error_regs = 0;
101 if (dev_id == MV_DEV_88F6281 || dev_id == MV_DEV_MV78100 ||
102 dev_id == MV_DEV_MV78100_Z0)
103 sc->ic_high_regs = 1;
105 if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
106 sc->ic_error_regs = 1;
108 error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
110 device_printf(dev, "could not allocate resources\n");
114 sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
115 sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
117 /* Mask all interrupts */
123 static device_method_t mv_ic_methods[] = {
124 DEVMETHOD(device_probe, mv_ic_probe),
125 DEVMETHOD(device_attach, mv_ic_attach),
129 static driver_t mv_ic_driver = {
132 sizeof(struct mv_ic_softc),
135 static devclass_t mv_ic_devclass;
137 DRIVER_MODULE(ic, mbus, mv_ic_driver, mv_ic_devclass, 0, 0);
140 arm_get_next_irq(int last __unused)
144 irq = mv_ic_get_cause() & mv_ic_get_mask();
146 return (ffs(irq) - 1);
148 if (mv_ic_sc->ic_high_regs) {
149 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
151 return (ffs(irq) + 31);
154 if (mv_ic_sc->ic_error_regs) {
155 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
157 return (ffs(irq) + 63);
164 arm_mask_irq_all(void)
169 if (mv_ic_sc->ic_high_regs)
170 mv_ic_set_mask_hi(0);
172 if (mv_ic_sc->ic_error_regs)
173 mv_ic_set_mask_error(0);
177 arm_mask_irq(uintptr_t nb)
182 mr = mv_ic_get_mask();
186 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
187 mr = mv_ic_get_mask_hi();
188 mr &= ~(1 << (nb - 32));
189 mv_ic_set_mask_hi(mr);
191 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
192 mr = mv_ic_get_mask_error();
193 mr &= ~(1 << (nb - 64));
194 mv_ic_set_mask_error(mr);
199 arm_unmask_irq(uintptr_t nb)
204 mr = mv_ic_get_mask();
208 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
209 mr = mv_ic_get_mask_hi();
210 mr |= (1 << (nb - 32));
211 mv_ic_set_mask_hi(mr);
213 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
214 mr = mv_ic_get_mask_error();
215 mr |= (1 << (nb - 64));
216 mv_ic_set_mask_error(mr);
221 mv_ic_set_mask(uint32_t val)
224 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
232 return (bus_space_read_4(mv_ic_sc->ic_bst,
233 mv_ic_sc->ic_bsh, IRQ_MASK));
237 mv_ic_get_cause(void)
240 return (bus_space_read_4(mv_ic_sc->ic_bst,
241 mv_ic_sc->ic_bsh, IRQ_CAUSE));
245 mv_ic_set_mask_hi(uint32_t val)
248 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
253 mv_ic_get_mask_hi(void)
256 return (bus_space_read_4(mv_ic_sc->ic_bst,
257 mv_ic_sc->ic_bsh, IRQ_MASK_HI));
261 mv_ic_get_cause_hi(void)
264 return (bus_space_read_4(mv_ic_sc->ic_bst,
265 mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
269 mv_ic_set_mask_error(uint32_t val)
272 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
273 IRQ_MASK_ERROR, val);
277 mv_ic_get_mask_error(void)
280 return (bus_space_read_4(mv_ic_sc->ic_bst,
281 mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
285 mv_ic_get_cause_error(void)
288 return (bus_space_read_4(mv_ic_sc->ic_bst,
289 mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));