2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Marvell integrated PCI/PCI-Express controller driver.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/queue.h>
49 #include <sys/endian.h>
54 #include <dev/pci/pcivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcib_private.h>
60 #include <machine/resource.h>
61 #include <machine/bus.h>
63 #include <arm/mv/mvreg.h>
64 #include <arm/mv/mvvar.h>
66 #define PCI_CFG_ENA (1 << 31)
67 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
68 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
69 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
70 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
72 #define PCI_REG_CFG_ADDR 0x0C78
73 #define PCI_REG_CFG_DATA 0x0C7C
74 #define PCI_REG_P2P_CONF 0x1D14
76 #define PCIE_REG_CFG_ADDR 0x18F8
77 #define PCIE_REG_CFG_DATA 0x18FC
78 #define PCIE_REG_CONTROL 0x1A00
79 #define PCIE_CTRL_LINK1X 0x00000001
80 #define PCIE_REG_STATUS 0x1A04
81 #define PCIE_REG_IRQ_MASK 0x1910
83 #define STATUS_LINK_DOWN 1
84 #define STATUS_BUS_OFFS 8
85 #define STATUS_BUS_MASK (0xFF << STATUS_BUS_OFFS)
86 #define STATUS_DEV_OFFS 16
87 #define STATUS_DEV_MASK (0x1F << STATUS_DEV_OFFS)
89 #define P2P_CONF_BUS_OFFS 16
90 #define P2P_CONF_BUS_MASK (0xFF << P2P_CONF_BUS_OFFS)
91 #define P2P_CONF_DEV_OFFS 24
92 #define P2P_CONF_DEV_MASK (0x1F << P2P_CONF_DEV_OFFS)
94 #define PCI_VENDORID_MRVL 0x11AB
96 struct pcib_mbus_softc {
99 struct rman sc_iomem_rman;
100 bus_addr_t sc_iomem_base;
101 bus_addr_t sc_iomem_size;
102 bus_addr_t sc_iomem_alloc; /* Next allocation. */
104 struct rman sc_ioport_rman;
105 bus_addr_t sc_ioport_base;
106 bus_addr_t sc_ioport_size;
107 bus_addr_t sc_ioport_alloc; /* Next allocation. */
109 struct resource *sc_res;
110 bus_space_handle_t sc_bsh;
111 bus_space_tag_t sc_bst;
114 int sc_busnr; /* Host bridge bus number */
115 int sc_devnr; /* Host bridge device number */
117 const struct obio_pci *sc_info;
120 static void pcib_mbus_identify(driver_t *driver, device_t parent);
121 static int pcib_mbus_probe(device_t);
122 static int pcib_mbus_attach(device_t);
124 static struct resource *pcib_mbus_alloc_resource(device_t, device_t, int, int *,
125 u_long, u_long, u_long, u_int);
126 static int pcib_mbus_release_resource(device_t, device_t, int, int,
128 static int pcib_mbus_read_ivar(device_t, device_t, int, uintptr_t *);
129 static int pcib_mbus_write_ivar(device_t, device_t, int, uintptr_t);
131 static int pcib_mbus_maxslots(device_t);
132 static uint32_t pcib_mbus_read_config(device_t, u_int, u_int, u_int, u_int,
134 static void pcib_mbus_write_config(device_t, u_int, u_int, u_int, u_int,
136 static int pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot);
137 static int pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot,
138 int func, int barno);
139 static void pcib_mbus_init_bridge(struct pcib_mbus_softc *sc, int bus, int slot,
141 static int pcib_mbus_init_resources(struct pcib_mbus_softc *sc, int bus,
142 int slot, int func, int hdrtype);
145 * Bus interface definitions.
147 static device_method_t pcib_mbus_methods[] = {
148 /* Device interface */
149 DEVMETHOD(device_identify, pcib_mbus_identify),
150 DEVMETHOD(device_probe, pcib_mbus_probe),
151 DEVMETHOD(device_attach, pcib_mbus_attach),
154 DEVMETHOD(bus_print_child, bus_generic_print_child),
155 DEVMETHOD(bus_read_ivar, pcib_mbus_read_ivar),
156 DEVMETHOD(bus_write_ivar, pcib_mbus_write_ivar),
157 DEVMETHOD(bus_alloc_resource, pcib_mbus_alloc_resource),
158 DEVMETHOD(bus_release_resource, pcib_mbus_release_resource),
159 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
160 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
161 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
162 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
165 DEVMETHOD(pcib_maxslots, pcib_mbus_maxslots),
166 DEVMETHOD(pcib_read_config, pcib_mbus_read_config),
167 DEVMETHOD(pcib_write_config, pcib_mbus_write_config),
168 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
173 static driver_t pcib_mbus_driver = {
176 sizeof(struct pcib_mbus_softc),
179 devclass_t pcib_devclass;
181 DRIVER_MODULE(pcib, mbus, pcib_mbus_driver, pcib_devclass, 0, 0);
183 static struct mtx pcicfg_mtx;
186 pcib_write_irq_mask(struct pcib_mbus_softc *sc, uint32_t mask)
189 if (!sc->sc_info->op_type != MV_TYPE_PCI)
192 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
193 PCIE_REG_IRQ_MASK, mask);
197 pcib_mbus_hw_cfginit(void)
199 static int opened = 0;
204 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
209 pcib_mbus_hw_cfgread(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
210 u_int func, u_int reg, int bytes)
212 uint32_t addr, data, ca, cd;
214 ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
215 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
216 cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
217 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
218 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
219 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
221 mtx_lock_spin(&pcicfg_mtx);
222 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
227 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
231 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
235 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
239 mtx_unlock_spin(&pcicfg_mtx);
244 pcib_mbus_hw_cfgwrite(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
245 u_int func, u_int reg, uint32_t data, int bytes)
247 uint32_t addr, ca, cd;
249 ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
250 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
251 cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
252 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
253 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
254 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
256 mtx_lock_spin(&pcicfg_mtx);
257 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
261 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
262 cd + (reg & 3), data);
265 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
266 cd + (reg & 2), htole16(data));
269 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
273 mtx_unlock_spin(&pcicfg_mtx);
277 pcib_mbus_maxslots(device_t dev)
279 struct pcib_mbus_softc *sc = device_get_softc(dev);
281 return ((sc->sc_info->op_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
285 pcib_mbus_read_config(device_t dev, u_int bus, u_int slot, u_int func,
286 u_int reg, int bytes)
288 struct pcib_mbus_softc *sc = device_get_softc(dev);
291 if (bus == sc->sc_busnr && slot == sc->sc_devnr)
294 return (pcib_mbus_hw_cfgread(sc, bus, slot, func, reg, bytes));
298 pcib_mbus_write_config(device_t dev, u_int bus, u_int slot, u_int func,
299 u_int reg, uint32_t val, int bytes)
301 struct pcib_mbus_softc *sc = device_get_softc(dev);
304 if (bus == sc->sc_busnr && slot == sc->sc_devnr)
307 pcib_mbus_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
311 pcib_mbus_add_child(driver_t *driver, device_t parent, struct pcib_mbus_softc *sc)
316 /* Configure CPU decoding windows */
317 error = decode_win_cpu_set(sc->sc_info->op_io_win_target,
318 sc->sc_info->op_io_win_attr, sc->sc_info->op_io_base,
319 sc->sc_info->op_io_size, -1);
321 device_printf(parent, "Could not set up CPU decode "
322 "window for PCI IO\n");
325 error = decode_win_cpu_set(sc->sc_info->op_mem_win_target,
326 sc->sc_info->op_mem_win_attr, sc->sc_info->op_mem_base,
327 sc->sc_info->op_mem_size, -1);
329 device_printf(parent, "Could not set up CPU decode "
330 "windows for PCI MEM\n");
334 /* Create driver instance */
335 child = BUS_ADD_CHILD(parent, 0, driver->name, -1);
336 bus_set_resource(child, SYS_RES_MEMORY, 0,
337 sc->sc_info->op_base, sc->sc_info->op_size);
338 device_set_softc(child, sc);
342 pcib_mbus_identify(driver_t *driver, device_t parent)
344 const struct obio_pci *info = mv_pci_info;
345 struct pcib_mbus_softc *sc;
348 while (info->op_base) {
349 sc = malloc(driver->size, M_DEVBUF, M_NOWAIT | M_ZERO);
351 device_printf(parent, "Could not allocate pcib "
355 sc->sc_info = info++;
358 * PCI bridge objects are instantiated immediately. PCI-Express
359 * bridges require more complicated handling depending on
360 * platform configuration.
362 if (sc->sc_info->op_type == MV_TYPE_PCI) {
363 pcib_mbus_add_child(driver, parent, sc);
368 * Read link configuration
371 sc->sc_res = BUS_ALLOC_RESOURCE(parent, parent, SYS_RES_MEMORY,
372 &sc->sc_rid, sc->sc_info->op_base, sc->sc_info->op_base +
373 sc->sc_info->op_size - 1, sc->sc_info->op_size,
375 if (sc->sc_res == NULL) {
376 device_printf(parent, "Could not map pcib memory\n");
380 sc->sc_bst = rman_get_bustag(sc->sc_res);
381 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
383 control = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
386 BUS_RELEASE_RESOURCE(parent, parent, SYS_RES_MEMORY, sc->sc_rid,
390 * If this PCI-E port (controller) is configured (by the
391 * underlying firmware) with lane width other than 1x, there
392 * are auxiliary resources defined for aggregating more width
393 * on our lane. Skip all such entries as they are not
394 * standalone ports and must not have a device object
397 if ((control & PCIE_CTRL_LINK1X) == 0)
398 while (info->op_base &&
399 info->op_type == MV_TYPE_PCIE_AGGR_LANE)
402 pcib_mbus_add_child(driver, parent, sc);
407 pcib_mbus_probe(device_t self)
410 struct pcib_mbus_softc *sc;
411 const char *id, *type;
413 int rv = ENOENT, bus, dev;
415 sc = device_get_softc(self);
418 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
420 if (sc->sc_res == NULL) {
421 device_printf(self, "Could not map memory\n");
425 sc->sc_bst = rman_get_bustag(sc->sc_res);
426 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
428 pcib_mbus_hw_cfginit();
430 /* Retrieve configuration of the bridge */
431 if (sc->sc_info->op_type == MV_TYPE_PCI) {
432 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
434 bus = sc->sc_busnr = (val & P2P_CONF_BUS_MASK) >>
436 dev = sc->sc_devnr = (val & P2P_CONF_DEV_MASK) >>
439 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS);
440 if (val & STATUS_LINK_DOWN)
442 bus = sc->sc_busnr = (val & STATUS_BUS_MASK) >> STATUS_BUS_OFFS;
443 dev = sc->sc_devnr = (val & STATUS_DEV_MASK) >> STATUS_DEV_OFFS;
446 val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_VENDOR, 2);
447 if (val != PCI_VENDORID_MRVL)
450 val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_DEVICE, 2);
469 * According to documentation ID 0x7820 is assigned to MV78200.
470 * However some MV78100 chips also use it.
472 id = "MV78100/MV78200";
475 device_printf(self, "unknown Marvell PCI bridge: %x\n", val);
480 val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, PCIR_CAP_PTR, 1);
482 val = pcib_mbus_hw_cfgread(sc, bus, dev, 0, val, 2);
483 switch (val & 0xff) {
488 type = "PCI-Express";
491 val = (val >> 8) & 0xff;
494 snprintf(buf, sizeof(buf), "Marvell %s %s host controller", id,
496 device_set_desc_copy(self, buf);
497 rv = BUS_PROBE_DEFAULT;
499 bus_release_resource(self, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
504 pcib_mbus_attach(device_t self)
506 struct pcib_mbus_softc *sc;
510 sc = device_get_softc(self);
514 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
516 if (sc->sc_res == NULL) {
517 device_printf(self, "Could not map memory\n");
520 sc->sc_bst = rman_get_bustag(sc->sc_res);
521 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
523 /* Enable PCI bridge */
524 val = pcib_mbus_hw_cfgread(sc, sc->sc_busnr, sc->sc_devnr, 0,
526 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
528 pcib_mbus_hw_cfgwrite(sc, sc->sc_busnr, sc->sc_devnr, 0,
529 PCIR_COMMAND, val, 2);
531 sc->sc_iomem_base = sc->sc_info->op_mem_base;
532 sc->sc_iomem_size = sc->sc_info->op_mem_size;
533 sc->sc_iomem_alloc = sc->sc_info->op_mem_base;
535 sc->sc_ioport_base = sc->sc_info->op_io_base;
536 sc->sc_ioport_size = sc->sc_info->op_io_size;
537 sc->sc_ioport_alloc = sc->sc_info->op_io_base;
539 sc->sc_iomem_rman.rm_type = RMAN_ARRAY;
540 err = rman_init(&sc->sc_iomem_rman);
544 sc->sc_ioport_rman.rm_type = RMAN_ARRAY;
545 err = rman_init(&sc->sc_ioport_rman);
547 rman_fini(&sc->sc_iomem_rman);
551 err = rman_manage_region(&sc->sc_iomem_rman, sc->sc_iomem_base,
552 sc->sc_iomem_base + sc->sc_iomem_size - 1);
556 err = rman_manage_region(&sc->sc_ioport_rman, sc->sc_ioport_base,
557 sc->sc_ioport_base + sc->sc_ioport_size - 1);
561 err = pcib_mbus_init(sc, sc->sc_busnr, pcib_mbus_maxslots(sc->sc_dev));
565 device_add_child(self, "pci", -1);
566 return (bus_generic_attach(self));
569 rman_fini(&sc->sc_iomem_rman);
570 rman_fini(&sc->sc_ioport_rman);
575 pcib_mbus_init_bar(struct pcib_mbus_softc *sc, int bus, int slot, int func,
578 bus_addr_t *allocp, limit;
579 uint32_t addr, bar, mask, size;
582 reg = PCIR_BAR(barno);
583 bar = pcib_mbus_read_config(sc->sc_dev, bus, slot, func, reg, 4);
587 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
588 width = ((bar & 7) == 4) ? 2 : 1;
590 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
591 size = pcib_mbus_read_config(sc->sc_dev, bus, slot, func, reg, 4);
593 /* Get BAR type and size */
596 allocp = &sc->sc_ioport_alloc;
597 limit = sc->sc_ioport_base + sc->sc_ioport_size;
599 if ((size & 0xffff0000) == 0)
603 allocp = &sc->sc_iomem_alloc;
604 limit = sc->sc_iomem_base + sc->sc_iomem_size;
610 /* Sanity check (must be a power of 2) */
614 addr = (*allocp + mask) & ~mask;
615 if ((*allocp = addr + size) > limit)
619 printf("PCI %u:%u:%u: reg %x: size=%08x: addr=%08x\n",
620 bus, slot, func, reg, size, addr);
622 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
624 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, reg + 4,
631 pcib_mbus_init_bridge(struct pcib_mbus_softc *sc, int bus, int slot, int func)
633 bus_addr_t io_base, mem_base;
634 uint32_t io_limit, mem_limit;
637 io_base = sc->sc_info->op_io_base;
638 io_limit = io_base + sc->sc_info->op_io_size - 1;
639 mem_base = sc->sc_info->op_mem_base;
640 mem_limit = mem_base + sc->sc_info->op_mem_size - 1;
642 /* Configure I/O decode registers */
643 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
645 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
647 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
649 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
652 /* Configure memory decode registers */
653 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
655 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
658 /* Disable memory prefetch decode */
659 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
661 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
663 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
665 pcib_mbus_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
668 secbus = pcib_mbus_read_config(sc->sc_dev, bus, slot, func,
671 /* Configure buses behind the bridge */
672 pcib_mbus_init(sc, secbus, PCI_SLOTMAX);
676 pcib_mbus_init_resources(struct pcib_mbus_softc *sc, int bus, int slot,
677 int func, int hdrtype)
679 const struct obio_pci_irq_map *map = sc->sc_info->op_pci_irq_map;
680 int maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
681 int bar = 0, irq = -1;
684 /* Program the base address registers */
685 while (bar < maxbar) {
686 i = pcib_mbus_init_bar(sc, bus, slot, func, bar);
689 device_printf(sc->sc_dev,
690 "PCI IO/Memory space exhausted\n");
695 /* Perform interrupt routing */
696 pin = pcib_mbus_read_config(sc->sc_dev, bus, slot, func,
700 while (map->opim_irq >= 0) {
701 if ((map->opim_slot == slot || map->opim_slot < 0) &&
702 (map->opim_pin == pin || map->opim_pin < 0))
708 irq = sc->sc_info->op_irq;
711 pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
712 PCIR_INTLINE, irq, 1);
714 device_printf(sc->sc_dev, "Missing IRQ routing information "
715 "for PCI device %u:%u:%u\n", bus, slot, func);
723 pcib_mbus_init(struct pcib_mbus_softc *sc, int bus, int maxslot)
725 int slot, func, maxfunc, error;
726 uint8_t hdrtype, command, class, subclass;
728 for (slot = 0; slot <= maxslot; slot++) {
730 for (func = 0; func <= maxfunc; func++) {
731 hdrtype = pcib_mbus_read_config(sc->sc_dev, bus, slot,
732 func, PCIR_HDRTYPE, 1);
734 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
737 if (func == 0 && (hdrtype & PCIM_MFDEV))
738 maxfunc = PCI_FUNCMAX;
740 command = pcib_mbus_read_config(sc->sc_dev, bus, slot,
741 func, PCIR_COMMAND, 1);
742 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
743 pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
744 PCIR_COMMAND, command, 1);
746 error = pcib_mbus_init_resources(sc, bus, slot, func,
752 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
754 pcib_mbus_write_config(sc->sc_dev, bus, slot, func,
755 PCIR_COMMAND, command, 1);
757 /* Handle PCI-PCI bridges */
758 class = pcib_mbus_read_config(sc->sc_dev, bus, slot,
759 func, PCIR_CLASS, 1);
760 subclass = pcib_mbus_read_config(sc->sc_dev, bus, slot,
761 func, PCIR_SUBCLASS, 1);
763 if (class != PCIC_BRIDGE ||
764 subclass != PCIS_BRIDGE_PCI)
767 pcib_mbus_init_bridge(sc, bus, slot, func);
771 /* Enable all ABCD interrupts */
772 pcib_write_irq_mask(sc, (0xF << 24));
777 static struct resource *
778 pcib_mbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
779 u_long start, u_long end, u_long count, u_int flags)
781 struct pcib_mbus_softc *sc = device_get_softc(dev);
782 struct rman *rm = NULL;
783 struct resource *res;
787 rm = &sc->sc_ioport_rman;
790 rm = &sc->sc_iomem_rman;
793 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
794 type, rid, start, end, count, flags));
797 res = rman_reserve_resource(rm, start, end, count, flags, child);
801 rman_set_rid(res, *rid);
802 rman_set_bustag(res, obio_tag);
803 rman_set_bushandle(res, start);
805 if (flags & RF_ACTIVE)
806 if (bus_activate_resource(child, type, *rid, res)) {
807 rman_release_resource(res);
815 pcib_mbus_release_resource(device_t dev, device_t child, int type, int rid,
816 struct resource *res)
819 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
820 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
823 return (rman_release_resource(res));
827 pcib_mbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
829 struct pcib_mbus_softc *sc = device_get_softc(dev);
833 *result = sc->sc_busnr;
835 case PCIB_IVAR_DOMAIN:
836 *result = device_get_unit(dev);
844 pcib_mbus_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
846 struct pcib_mbus_softc *sc = device_get_softc(dev);
850 sc->sc_busnr = value;