2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * Adapted to Marvell SoC by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
41 #include <sys/timeet.h>
42 #include <sys/timetc.h>
43 #include <sys/watchdog.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
46 #include <machine/frame.h>
47 #include <machine/intr.h>
49 #include <arm/mv/mvreg.h>
50 #include <arm/mv/mvvar.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #define INITIAL_TIMECOUNTER (0xffffffff)
56 #define MAX_WATCHDOG_TICKS (0xffffffff)
58 #if defined(SOC_MV_ARMADAXP)
59 #define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
61 #define MV_CLOCK_SRC get_tclk()
64 struct mv_timer_softc {
65 struct resource * timer_res[2];
66 bus_space_tag_t timer_bst;
67 bus_space_handle_t timer_bsh;
72 static struct resource_spec mv_timer_spec[] = {
73 { SYS_RES_MEMORY, 0, RF_ACTIVE },
74 { SYS_RES_IRQ, 0, RF_ACTIVE },
78 static struct mv_timer_softc *timer_softc = NULL;
79 static int timers_initialized = 0;
81 static int mv_timer_probe(device_t);
82 static int mv_timer_attach(device_t);
84 static int mv_hardclock(void *);
85 static unsigned mv_timer_get_timecount(struct timecounter *);
87 static uint32_t mv_get_timer_control(void);
88 static void mv_set_timer_control(uint32_t);
89 static uint32_t mv_get_timer(uint32_t);
90 static void mv_set_timer(uint32_t, uint32_t);
91 static void mv_set_timer_rel(uint32_t, uint32_t);
92 static void mv_watchdog_enable(void);
93 static void mv_watchdog_disable(void);
94 static void mv_watchdog_event(void *, unsigned int, int *);
95 static int mv_timer_start(struct eventtimer *et,
96 sbintime_t first, sbintime_t period);
97 static int mv_timer_stop(struct eventtimer *et);
98 static void mv_setup_timers(void);
100 static struct timecounter mv_timer_timecounter = {
101 .tc_get_timecount = mv_timer_get_timecount,
102 .tc_name = "CPUTimer1",
103 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */
104 .tc_counter_mask = ~0u,
109 mv_timer_probe(device_t dev)
112 if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
115 device_set_desc(dev, "Marvell CPU Timer");
120 mv_timer_attach(device_t dev)
124 struct mv_timer_softc *sc;
125 #if !defined(SOC_MV_ARMADAXP)
126 uint32_t irq_cause, irq_mask;
129 if (timer_softc != NULL)
132 sc = (struct mv_timer_softc *)device_get_softc(dev);
135 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
137 device_printf(dev, "could not allocate resources\n");
141 sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
142 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
144 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
145 mv_watchdog_disable();
146 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
148 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
149 mv_hardclock, NULL, sc, &ihl) != 0) {
150 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
151 device_printf(dev, "Could not setup interrupt.\n");
156 #if !defined(SOC_MV_ARMADAXP)
157 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
158 irq_cause &= IRQ_TIMER0_CLR;
160 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
161 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
162 irq_mask |= IRQ_TIMER0_MASK;
163 irq_mask &= ~IRQ_TIMER1_MASK;
164 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
166 sc->et.et_name = "CPUTimer0";
167 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
168 sc->et.et_quality = 1000;
170 sc->et.et_frequency = MV_CLOCK_SRC;
171 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
172 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
173 sc->et.et_start = mv_timer_start;
174 sc->et.et_stop = mv_timer_stop;
176 et_register(&sc->et);
177 mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
178 tc_init(&mv_timer_timecounter);
184 mv_hardclock(void *arg)
186 struct mv_timer_softc *sc;
189 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
190 irq_cause &= IRQ_TIMER0_CLR;
191 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
193 sc = (struct mv_timer_softc *)arg;
194 if (sc->et.et_active)
195 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
197 return (FILTER_HANDLED);
200 static device_method_t mv_timer_methods[] = {
201 DEVMETHOD(device_probe, mv_timer_probe),
202 DEVMETHOD(device_attach, mv_timer_attach),
207 static driver_t mv_timer_driver = {
210 sizeof(struct mv_timer_softc),
213 static devclass_t mv_timer_devclass;
215 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
218 mv_timer_get_timecount(struct timecounter *tc)
221 return (INITIAL_TIMECOUNTER - mv_get_timer(1));
228 cpu_initclocks_bsp();
234 uint32_t val, val_temp;
237 if (!timers_initialized) {
238 for (; usec > 0; usec--)
239 for (val = 100; val > 0; val--)
240 __asm __volatile("nop" ::: "memory");
244 val = mv_get_timer(1);
245 nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
248 val_temp = mv_get_timer(1);
250 nticks -= (val - val_temp);
252 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
259 mv_get_timer_control(void)
262 return (bus_space_read_4(timer_softc->timer_bst,
263 timer_softc->timer_bsh, CPU_TIMER_CONTROL));
267 mv_set_timer_control(uint32_t val)
270 bus_space_write_4(timer_softc->timer_bst,
271 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
275 mv_get_timer(uint32_t timer)
278 return (bus_space_read_4(timer_softc->timer_bst,
279 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
283 mv_set_timer(uint32_t timer, uint32_t val)
286 bus_space_write_4(timer_softc->timer_bst,
287 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
291 mv_set_timer_rel(uint32_t timer, uint32_t val)
294 bus_space_write_4(timer_softc->timer_bst,
295 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
299 mv_watchdog_enable(void)
301 uint32_t val, irq_cause;
302 #if !defined(SOC_MV_ARMADAXP)
306 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
307 irq_cause &= IRQ_TIMER_WD_CLR;
308 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
310 #if defined(SOC_MV_ARMADAXP)
311 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
312 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
313 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
315 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
316 irq_mask |= IRQ_TIMER_WD_MASK;
317 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
319 val = read_cpu_ctrl(RSTOUTn_MASK);
320 val |= WD_RST_OUT_EN;
321 write_cpu_ctrl(RSTOUTn_MASK, val);
324 val = mv_get_timer_control();
325 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
326 #if defined(SOC_MV_ARMADAXP)
327 val |= CPU_TIMER_WD_25MHZ_EN;
329 mv_set_timer_control(val);
333 mv_watchdog_disable(void)
335 uint32_t val, irq_cause;
336 #if !defined(SOC_MV_ARMADAXP)
340 val = mv_get_timer_control();
341 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
342 mv_set_timer_control(val);
344 #if defined(SOC_MV_ARMADAXP)
345 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
346 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
347 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
349 val = read_cpu_ctrl(RSTOUTn_MASK);
350 val &= ~WD_RST_OUT_EN;
351 write_cpu_ctrl(RSTOUTn_MASK, val);
353 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
354 irq_mask &= ~(IRQ_TIMER_WD_MASK);
355 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
358 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
359 irq_cause &= IRQ_TIMER_WD_CLR;
360 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
365 * Watchdog event handler.
368 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
373 mtx_lock(&timer_softc->timer_mtx);
375 mv_watchdog_disable();
378 * Watchdog timeout is in nanosecs, calculation according to
381 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
382 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
383 if (ticks > MAX_WATCHDOG_TICKS)
384 mv_watchdog_disable();
386 /* Timer 2 is the watchdog */
387 mv_set_timer(2, ticks);
388 mv_watchdog_enable();
392 mtx_unlock(&timer_softc->timer_mtx);
396 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
398 struct mv_timer_softc *sc;
401 /* Calculate dividers. */
402 sc = (struct mv_timer_softc *)et->et_priv;
404 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
408 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
412 /* Apply configuration. */
413 mv_set_timer_rel(0, val);
414 mv_set_timer(0, val1);
415 val = mv_get_timer_control();
416 val |= CPU_TIMER0_EN;
418 val |= CPU_TIMER0_AUTO;
420 val &= ~CPU_TIMER0_AUTO;
421 mv_set_timer_control(val);
426 mv_timer_stop(struct eventtimer *et)
430 val = mv_get_timer_control();
431 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
432 mv_set_timer_control(val);
437 mv_setup_timers(void)
441 mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
442 mv_set_timer(1, INITIAL_TIMECOUNTER);
443 val = mv_get_timer_control();
444 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
445 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
446 #if defined(SOC_MV_ARMADAXP)
447 /* Enable 25MHz mode */
448 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
450 mv_set_timer_control(val);
451 timers_initialized = 1;