sys/arm/mv/timer.c

   1 /*-
   2  * Copyright (c) 2006 Benno Rice.
   3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   4  * All rights reserved.
   5  *
   6  * Adapted to Marvell SoC by Semihalf.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/malloc.h>
  40 #include <sys/rman.h>
  41 #include <sys/timeet.h>
  42 #include <sys/timetc.h>
  43 #include <sys/watchdog.h>
  44 #include <machine/bus.h>
  45 #include <machine/cpu.h>
  46 #include <machine/intr.h>
  47
  48 #include <arm/mv/mvreg.h>
  49 #include <arm/mv/mvvar.h>
  50
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #define INITIAL_TIMECOUNTER     (0xffffffff)
  55 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  56
  57 #if defined(SOC_MV_ARMADAXP)
  58 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
  59 #else
  60 #define MV_CLOCK_SRC            get_tclk()
  61 #endif
  62
  63 struct mv_timer_softc {
  64         struct resource *       timer_res[2];
  65         bus_space_tag_t         timer_bst;
  66         bus_space_handle_t      timer_bsh;
  67         struct mtx              timer_mtx;
  68         struct eventtimer       et;
  69 };
  70
  71 static struct resource_spec mv_timer_spec[] = {
  72         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  73         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  74         { -1, 0 }
  75 };
  76
  77 static struct mv_timer_softc *timer_softc = NULL;
  78 static int timers_initialized = 0;
  79
  80 static int      mv_timer_probe(device_t);
  81 static int      mv_timer_attach(device_t);
  82
  83 static int      mv_hardclock(void *);
  84 static unsigned mv_timer_get_timecount(struct timecounter *);
  85
  86 static uint32_t mv_get_timer_control(void);
  87 static void     mv_set_timer_control(uint32_t);
  88 static uint32_t mv_get_timer(uint32_t);
  89 static void     mv_set_timer(uint32_t, uint32_t);
  90 static void     mv_set_timer_rel(uint32_t, uint32_t);
  91 static void     mv_watchdog_enable(void);
  92 static void     mv_watchdog_disable(void);
  93 static void     mv_watchdog_event(void *, unsigned int, int *);
  94 static int      mv_timer_start(struct eventtimer *et,
  95     sbintime_t first, sbintime_t period);
  96 static int      mv_timer_stop(struct eventtimer *et);
  97 static void     mv_setup_timers(void);
  98
  99 static struct timecounter mv_timer_timecounter = {
 100         .tc_get_timecount = mv_timer_get_timecount,
 101         .tc_name = "CPUTimer1",
 102         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
 103         .tc_counter_mask = ~0u,
 104         .tc_quality = 1000,
 105 };
 106
 107 static int
 108 mv_timer_probe(device_t dev)
 109 {
 110
 111         if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
 112                 return (ENXIO);
 113
 114         device_set_desc(dev, "Marvell CPU Timer");
 115         return (0);
 116 }
 117
 118 static int
 119 mv_timer_attach(device_t dev)
 120 {
 121         int     error;
 122         void    *ihl;
 123         struct  mv_timer_softc *sc;
 124 #if !defined(SOC_MV_ARMADAXP)
 125         uint32_t irq_cause, irq_mask;
 126 #endif
 127
 128         if (timer_softc != NULL)
 129                 return (ENXIO);
 130
 131         sc = (struct mv_timer_softc *)device_get_softc(dev);
 132         timer_softc = sc;
 133
 134         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
 135         if (error) {
 136                 device_printf(dev, "could not allocate resources\n");
 137                 return (ENXIO);
 138         }
 139
 140         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
 141         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
 142
 143         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
 144         mv_watchdog_disable();
 145         EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 146
 147         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
 148             mv_hardclock, NULL, sc, &ihl) != 0) {
 149                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 150                 device_printf(dev, "Could not setup interrupt.\n");
 151                 return (ENXIO);
 152         }
 153
 154         mv_setup_timers();
 155 #if !defined(SOC_MV_ARMADAXP)
 156         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 157         irq_cause &= IRQ_TIMER0_CLR;
 158
 159         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 160         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 161         irq_mask |= IRQ_TIMER0_MASK;
 162         irq_mask &= ~IRQ_TIMER1_MASK;
 163         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 164 #endif
 165         sc->et.et_name = "CPUTimer0";
 166         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 167         sc->et.et_quality = 1000;
 168
 169         sc->et.et_frequency = MV_CLOCK_SRC;
 170         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 171         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 172         sc->et.et_start = mv_timer_start;
 173         sc->et.et_stop = mv_timer_stop;
 174         sc->et.et_priv = sc;
 175         et_register(&sc->et);
 176         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
 177         tc_init(&mv_timer_timecounter);
 178
 179         return (0);
 180 }
 181
 182 static int
 183 mv_hardclock(void *arg)
 184 {
 185         struct  mv_timer_softc *sc;
 186         uint32_t irq_cause;
 187
 188         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 189         irq_cause &= IRQ_TIMER0_CLR;
 190         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 191
 192         sc = (struct mv_timer_softc *)arg;
 193         if (sc->et.et_active)
 194                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 195
 196         return (FILTER_HANDLED);
 197 }
 198
 199 static device_method_t mv_timer_methods[] = {
 200         DEVMETHOD(device_probe, mv_timer_probe),
 201         DEVMETHOD(device_attach, mv_timer_attach),
 202
 203         { 0, 0 }
 204 };
 205
 206 static driver_t mv_timer_driver = {
 207         "timer",
 208         mv_timer_methods,
 209         sizeof(struct mv_timer_softc),
 210 };
 211
 212 static devclass_t mv_timer_devclass;
 213
 214 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
 215
 216 static unsigned
 217 mv_timer_get_timecount(struct timecounter *tc)
 218 {
 219
 220         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
 221 }
 222
 223 void
 224 cpu_initclocks(void)
 225 {
 226
 227         cpu_initclocks_bsp();
 228 }
 229
 230 void
 231 DELAY(int usec)
 232 {
 233         uint32_t        val, val_temp;
 234         int32_t         nticks;
 235
 236         if (!timers_initialized) {
 237                 for (; usec > 0; usec--)
 238                         for (val = 100; val > 0; val--)
 239                                 __asm __volatile("nop" ::: "memory");
 240                 return;
 241         }
 242
 243         val = mv_get_timer(1);
 244         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
 245
 246         while (nticks > 0) {
 247                 val_temp = mv_get_timer(1);
 248                 if (val > val_temp)
 249                         nticks -= (val - val_temp);
 250                 else
 251                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
 252
 253                 val = val_temp;
 254         }
 255 }
 256
 257 static uint32_t
 258 mv_get_timer_control(void)
 259 {
 260
 261         return (bus_space_read_4(timer_softc->timer_bst,
 262             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
 263 }
 264
 265 static void
 266 mv_set_timer_control(uint32_t val)
 267 {
 268
 269         bus_space_write_4(timer_softc->timer_bst,
 270             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
 271 }
 272
 273 static uint32_t
 274 mv_get_timer(uint32_t timer)
 275 {
 276
 277         return (bus_space_read_4(timer_softc->timer_bst,
 278             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
 279 }
 280
 281 static void
 282 mv_set_timer(uint32_t timer, uint32_t val)
 283 {
 284
 285         bus_space_write_4(timer_softc->timer_bst,
 286             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
 287 }
 288
 289 static void
 290 mv_set_timer_rel(uint32_t timer, uint32_t val)
 291 {
 292
 293         bus_space_write_4(timer_softc->timer_bst,
 294             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
 295 }
 296
 297 static void
 298 mv_watchdog_enable(void)
 299 {
 300         uint32_t val, irq_cause;
 301 #if !defined(SOC_MV_ARMADAXP)
 302         uint32_t irq_mask;
 303 #endif
 304
 305         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 306         irq_cause &= IRQ_TIMER_WD_CLR;
 307         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 308
 309 #if defined(SOC_MV_ARMADAXP)
 310         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 311         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 312         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 313 #else
 314         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 315         irq_mask |= IRQ_TIMER_WD_MASK;
 316         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 317
 318         val = read_cpu_ctrl(RSTOUTn_MASK);
 319         val |= WD_RST_OUT_EN;
 320         write_cpu_ctrl(RSTOUTn_MASK, val);
 321 #endif
 322
 323         val = mv_get_timer_control();
 324         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
 325 #if defined(SOC_MV_ARMADAXP)
 326         val |= CPU_TIMER_WD_25MHZ_EN;
 327 #endif
 328         mv_set_timer_control(val);
 329 }
 330
 331 static void
 332 mv_watchdog_disable(void)
 333 {
 334         uint32_t val, irq_cause;
 335 #if !defined(SOC_MV_ARMADAXP)
 336         uint32_t irq_mask;
 337 #endif
 338
 339         val = mv_get_timer_control();
 340         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 341         mv_set_timer_control(val);
 342
 343 #if defined(SOC_MV_ARMADAXP)
 344         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 345         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 346         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 347 #else
 348         val = read_cpu_ctrl(RSTOUTn_MASK);
 349         val &= ~WD_RST_OUT_EN;
 350         write_cpu_ctrl(RSTOUTn_MASK, val);
 351
 352         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 353         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 354         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 355 #endif
 356
 357         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 358         irq_cause &= IRQ_TIMER_WD_CLR;
 359         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 360 }
 361
 362
 363 /*
 364  * Watchdog event handler.
 365  */
 366 static void
 367 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 368 {
 369         uint64_t ns;
 370         uint64_t ticks;
 371
 372         mtx_lock(&timer_softc->timer_mtx);
 373         if (cmd == 0)
 374                 mv_watchdog_disable();
 375         else {
 376                 /*
 377                  * Watchdog timeout is in nanosecs, calculation according to
 378                  * watchdog(9)
 379                  */
 380                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 381                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
 382                 if (ticks > MAX_WATCHDOG_TICKS)
 383                         mv_watchdog_disable();
 384                 else {
 385                         /* Timer 2 is the watchdog */
 386                         mv_set_timer(2, ticks);
 387                         mv_watchdog_enable();
 388                         *error = 0;
 389                 }
 390         }
 391         mtx_unlock(&timer_softc->timer_mtx);
 392 }
 393
 394 static int
 395 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 396 {
 397         struct  mv_timer_softc *sc;
 398         uint32_t val, val1;
 399
 400         /* Calculate dividers. */
 401         sc = (struct mv_timer_softc *)et->et_priv;
 402         if (period != 0)
 403                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
 404         else
 405                 val = 0;
 406         if (first != 0)
 407                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
 408         else
 409                 val1 = val;
 410
 411         /* Apply configuration. */
 412         mv_set_timer_rel(0, val);
 413         mv_set_timer(0, val1);
 414         val = mv_get_timer_control();
 415         val |= CPU_TIMER0_EN;
 416         if (period != 0)
 417                 val |= CPU_TIMER0_AUTO;
 418         else
 419                 val &= ~CPU_TIMER0_AUTO;
 420         mv_set_timer_control(val);
 421         return (0);
 422 }
 423
 424 static int
 425 mv_timer_stop(struct eventtimer *et)
 426 {
 427         uint32_t val;
 428
 429         val = mv_get_timer_control();
 430         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 431         mv_set_timer_control(val);
 432         return (0);
 433 }
 434
 435 static void
 436 mv_setup_timers(void)
 437 {
 438         uint32_t val;
 439
 440         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
 441         mv_set_timer(1, INITIAL_TIMECOUNTER);
 442         val = mv_get_timer_control();
 443         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 444         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
 445 #if defined(SOC_MV_ARMADAXP)
 446         /* Enable 25MHz mode */
 447         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
 448 #endif
 449         mv_set_timer_control(val);
 450         timers_initialized = 1;
 451 }