sys/arm/mv/timer.c

   1 /*-
   2  * Copyright (c) 2006 Benno Rice.
   3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
   4  * All rights reserved.
   5  *
   6  * Adapted to Marvell SoC by Semihalf.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/malloc.h>
  40 #include <sys/rman.h>
  41 #include <sys/timeet.h>
  42 #include <sys/timetc.h>
  43 #include <sys/watchdog.h>
  44 #include <machine/bus.h>
  45 #include <machine/cpu.h>
  46 #include <machine/intr.h>
  47
  48 #include <arm/mv/mvreg.h>
  49 #include <arm/mv/mvvar.h>
  50
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #define INITIAL_TIMECOUNTER     (0xffffffff)
  55 #define MAX_WATCHDOG_TICKS      (0xffffffff)
  56
  57 #if defined(SOC_MV_ARMADAXP)
  58 #define MV_CLOCK_SRC            25000000        /* Timers' 25MHz mode */
  59 #else
  60 #define MV_CLOCK_SRC            get_tclk()
  61 #endif
  62
  63 struct mv_timer_softc {
  64         struct resource *       timer_res[2];
  65         bus_space_tag_t         timer_bst;
  66         bus_space_handle_t      timer_bsh;
  67         struct mtx              timer_mtx;
  68         struct eventtimer       et;
  69 };
  70
  71 static struct resource_spec mv_timer_spec[] = {
  72         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  73         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  74         { -1, 0 }
  75 };
  76
  77 static struct mv_timer_softc *timer_softc = NULL;
  78 static int timers_initialized = 0;
  79
  80 static int      mv_timer_probe(device_t);
  81 static int      mv_timer_attach(device_t);
  82
  83 static int      mv_hardclock(void *);
  84 static unsigned mv_timer_get_timecount(struct timecounter *);
  85
  86 static uint32_t mv_get_timer_control(void);
  87 static void     mv_set_timer_control(uint32_t);
  88 static uint32_t mv_get_timer(uint32_t);
  89 static void     mv_set_timer(uint32_t, uint32_t);
  90 static void     mv_set_timer_rel(uint32_t, uint32_t);
  91 static void     mv_watchdog_enable(void);
  92 static void     mv_watchdog_disable(void);
  93 static void     mv_watchdog_event(void *, unsigned int, int *);
  94 static int      mv_timer_start(struct eventtimer *et,
  95     sbintime_t first, sbintime_t period);
  96 static int      mv_timer_stop(struct eventtimer *et);
  97 static void     mv_setup_timers(void);
  98
  99 static struct timecounter mv_timer_timecounter = {
 100         .tc_get_timecount = mv_timer_get_timecount,
 101         .tc_name = "CPUTimer1",
 102         .tc_frequency = 0,      /* This is assigned on the fly in the init sequence */
 103         .tc_counter_mask = ~0u,
 104         .tc_quality = 1000,
 105 };
 106
 107 static int
 108 mv_timer_probe(device_t dev)
 109 {
 110
 111         if (!ofw_bus_status_okay(dev))
 112                 return (ENXIO);
 113
 114         if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
 115                 return (ENXIO);
 116
 117         device_set_desc(dev, "Marvell CPU Timer");
 118         return (0);
 119 }
 120
 121 static int
 122 mv_timer_attach(device_t dev)
 123 {
 124         int     error;
 125         void    *ihl;
 126         struct  mv_timer_softc *sc;
 127 #if !defined(SOC_MV_ARMADAXP)
 128         uint32_t irq_cause, irq_mask;
 129 #endif
 130
 131         if (timer_softc != NULL)
 132                 return (ENXIO);
 133
 134         sc = (struct mv_timer_softc *)device_get_softc(dev);
 135         timer_softc = sc;
 136
 137         error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);
 138         if (error) {
 139                 device_printf(dev, "could not allocate resources\n");
 140                 return (ENXIO);
 141         }
 142
 143         sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
 144         sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
 145
 146         mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
 147         mv_watchdog_disable();
 148         EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
 149
 150         if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
 151             mv_hardclock, NULL, sc, &ihl) != 0) {
 152                 bus_release_resources(dev, mv_timer_spec, sc->timer_res);
 153                 device_printf(dev, "Could not setup interrupt.\n");
 154                 return (ENXIO);
 155         }
 156
 157         mv_setup_timers();
 158 #if !defined(SOC_MV_ARMADAXP)
 159         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 160         irq_cause &= IRQ_TIMER0_CLR;
 161
 162         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 163         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 164         irq_mask |= IRQ_TIMER0_MASK;
 165         irq_mask &= ~IRQ_TIMER1_MASK;
 166         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 167 #endif
 168         sc->et.et_name = "CPUTimer0";
 169         sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 170         sc->et.et_quality = 1000;
 171
 172         sc->et.et_frequency = MV_CLOCK_SRC;
 173         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 174         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 175         sc->et.et_start = mv_timer_start;
 176         sc->et.et_stop = mv_timer_stop;
 177         sc->et.et_priv = sc;
 178         et_register(&sc->et);
 179         mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC;
 180         tc_init(&mv_timer_timecounter);
 181
 182         return (0);
 183 }
 184
 185 static int
 186 mv_hardclock(void *arg)
 187 {
 188         struct  mv_timer_softc *sc;
 189         uint32_t irq_cause;
 190
 191         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 192         irq_cause &= IRQ_TIMER0_CLR;
 193         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 194
 195         sc = (struct mv_timer_softc *)arg;
 196         if (sc->et.et_active)
 197                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 198
 199         return (FILTER_HANDLED);
 200 }
 201
 202 static device_method_t mv_timer_methods[] = {
 203         DEVMETHOD(device_probe, mv_timer_probe),
 204         DEVMETHOD(device_attach, mv_timer_attach),
 205
 206         { 0, 0 }
 207 };
 208
 209 static driver_t mv_timer_driver = {
 210         "timer",
 211         mv_timer_methods,
 212         sizeof(struct mv_timer_softc),
 213 };
 214
 215 static devclass_t mv_timer_devclass;
 216
 217 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0);
 218
 219 static unsigned
 220 mv_timer_get_timecount(struct timecounter *tc)
 221 {
 222
 223         return (INITIAL_TIMECOUNTER - mv_get_timer(1));
 224 }
 225
 226 void
 227 cpu_initclocks(void)
 228 {
 229
 230         cpu_initclocks_bsp();
 231 }
 232
 233 void
 234 DELAY(int usec)
 235 {
 236         uint32_t        val, val_temp;
 237         int32_t         nticks;
 238
 239         if (!timers_initialized) {
 240                 for (; usec > 0; usec--)
 241                         for (val = 100; val > 0; val--)
 242                                 __asm __volatile("nop" ::: "memory");
 243                 return;
 244         }
 245
 246         val = mv_get_timer(1);
 247         nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec);
 248
 249         while (nticks > 0) {
 250                 val_temp = mv_get_timer(1);
 251                 if (val > val_temp)
 252                         nticks -= (val - val_temp);
 253                 else
 254                         nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
 255
 256                 val = val_temp;
 257         }
 258 }
 259
 260 static uint32_t
 261 mv_get_timer_control(void)
 262 {
 263
 264         return (bus_space_read_4(timer_softc->timer_bst,
 265             timer_softc->timer_bsh, CPU_TIMER_CONTROL));
 266 }
 267
 268 static void
 269 mv_set_timer_control(uint32_t val)
 270 {
 271
 272         bus_space_write_4(timer_softc->timer_bst,
 273             timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);
 274 }
 275
 276 static uint32_t
 277 mv_get_timer(uint32_t timer)
 278 {
 279
 280         return (bus_space_read_4(timer_softc->timer_bst,
 281             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));
 282 }
 283
 284 static void
 285 mv_set_timer(uint32_t timer, uint32_t val)
 286 {
 287
 288         bus_space_write_4(timer_softc->timer_bst,
 289             timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);
 290 }
 291
 292 static void
 293 mv_set_timer_rel(uint32_t timer, uint32_t val)
 294 {
 295
 296         bus_space_write_4(timer_softc->timer_bst,
 297             timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);
 298 }
 299
 300 static void
 301 mv_watchdog_enable(void)
 302 {
 303         uint32_t val, irq_cause;
 304 #if !defined(SOC_MV_ARMADAXP)
 305         uint32_t irq_mask;
 306 #endif
 307
 308         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 309         irq_cause &= IRQ_TIMER_WD_CLR;
 310         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 311
 312 #if defined(SOC_MV_ARMADAXP)
 313         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 314         val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
 315         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 316 #else
 317         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 318         irq_mask |= IRQ_TIMER_WD_MASK;
 319         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 320
 321         val = read_cpu_ctrl(RSTOUTn_MASK);
 322         val |= WD_RST_OUT_EN;
 323         write_cpu_ctrl(RSTOUTn_MASK, val);
 324 #endif
 325
 326         val = mv_get_timer_control();
 327         val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
 328 #if defined(SOC_MV_ARMADAXP)
 329         val |= CPU_TIMER_WD_25MHZ_EN;
 330 #endif
 331         mv_set_timer_control(val);
 332 }
 333
 334 static void
 335 mv_watchdog_disable(void)
 336 {
 337         uint32_t val, irq_cause;
 338 #if !defined(SOC_MV_ARMADAXP)
 339         uint32_t irq_mask;
 340 #endif
 341
 342         val = mv_get_timer_control();
 343         val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
 344         mv_set_timer_control(val);
 345
 346 #if defined(SOC_MV_ARMADAXP)
 347         val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
 348         val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
 349         write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
 350 #else
 351         val = read_cpu_ctrl(RSTOUTn_MASK);
 352         val &= ~WD_RST_OUT_EN;
 353         write_cpu_ctrl(RSTOUTn_MASK, val);
 354
 355         irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
 356         irq_mask &= ~(IRQ_TIMER_WD_MASK);
 357         write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
 358 #endif
 359
 360         irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
 361         irq_cause &= IRQ_TIMER_WD_CLR;
 362         write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
 363 }
 364
 365
 366 /*
 367  * Watchdog event handler.
 368  */
 369 static void
 370 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
 371 {
 372         uint64_t ns;
 373         uint64_t ticks;
 374
 375         mtx_lock(&timer_softc->timer_mtx);
 376         if (cmd == 0)
 377                 mv_watchdog_disable();
 378         else {
 379                 /*
 380                  * Watchdog timeout is in nanosecs, calculation according to
 381                  * watchdog(9)
 382                  */
 383                 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
 384                 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000;
 385                 if (ticks > MAX_WATCHDOG_TICKS)
 386                         mv_watchdog_disable();
 387                 else {
 388                         /* Timer 2 is the watchdog */
 389                         mv_set_timer(2, ticks);
 390                         mv_watchdog_enable();
 391                         *error = 0;
 392                 }
 393         }
 394         mtx_unlock(&timer_softc->timer_mtx);
 395 }
 396
 397 static int
 398 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 399 {
 400         struct  mv_timer_softc *sc;
 401         uint32_t val, val1;
 402
 403         /* Calculate dividers. */
 404         sc = (struct mv_timer_softc *)et->et_priv;
 405         if (period != 0)
 406                 val = ((uint32_t)sc->et.et_frequency * period) >> 32;
 407         else
 408                 val = 0;
 409         if (first != 0)
 410                 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;
 411         else
 412                 val1 = val;
 413
 414         /* Apply configuration. */
 415         mv_set_timer_rel(0, val);
 416         mv_set_timer(0, val1);
 417         val = mv_get_timer_control();
 418         val |= CPU_TIMER0_EN;
 419         if (period != 0)
 420                 val |= CPU_TIMER0_AUTO;
 421         else
 422                 val &= ~CPU_TIMER0_AUTO;
 423         mv_set_timer_control(val);
 424         return (0);
 425 }
 426
 427 static int
 428 mv_timer_stop(struct eventtimer *et)
 429 {
 430         uint32_t val;
 431
 432         val = mv_get_timer_control();
 433         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 434         mv_set_timer_control(val);
 435         return (0);
 436 }
 437
 438 static void
 439 mv_setup_timers(void)
 440 {
 441         uint32_t val;
 442
 443         mv_set_timer_rel(1, INITIAL_TIMECOUNTER);
 444         mv_set_timer(1, INITIAL_TIMECOUNTER);
 445         val = mv_get_timer_control();
 446         val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
 447         val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
 448 #if defined(SOC_MV_ARMADAXP)
 449         /* Enable 25MHz mode */
 450         val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
 451 #endif
 452         mv_set_timer_control(val);
 453         timers_initialized = 1;
 454 }