1 /* $NetBSD: s3c2410reg.h,v 1.6 2004/02/12 03:52:46 bsh Exp $ */
4 * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of Genetec corporation may not be used to endorse
16 * or promote products derived from this software without specific prior
19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
36 * Samsung S3C2410X processor is ARM920T based integrated CPU
39 * S3C2410X User's Manual
41 #ifndef _ARM_S3C2XX0_S3C2410REG_H_
42 #define _ARM_S3C2XX0_S3C2410REG_H_
44 /* common definitions for S3C2410 and S3C2440 */
45 #include <arm/s3c2xx0/s3c24x0reg.h>
50 #define S3C2410_BANK_SIZE 0x08000000
51 #define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n))
52 #define S3C2410_SDRAM_START S3C2410_BANK_START(6)
55 /* interrupt control */
56 #define S3C2410_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10)
60 #define S3C2410_CLKCON_SM (1<<0) /* 1=transition to SPECIAL mode */
62 #define S3C2410_CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */
64 /* NAND Flash controller */
65 #define S3C2410_NANDFC_SIZE 0x18
67 #define S3C2410_NFCONF_ENABLE (1<<15) /* NAND controller enabled */
68 #define S3C2410_NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */
69 #define S3C2410_NFCONF_FCE (1<<11) /* Flash chip enabled */
70 #define S3C2410_NFCONF_TACLS (7<<8) /* CLE and ALE duration */
71 #define S3C2410_NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */
72 #define S3C2410_NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */
73 #define S3C2410_NANDFC_NFCMD 0x04 /* command */
74 #define S3C2410_NANDFC_NFADDR 0x08 /* address */
75 #define S3C2410_NANDFC_NFDATA 0x0c /* data */
76 #define S3C2410_NANDFC_NFSTAT 0x10 /* operation status */
77 #define S3C2410_NANDFC_NFECC 0x14 /* ecc */
81 #define S3C2410_CON_FIFO_RESET (1<<1)
84 #define S3C2410_GPIO_SIZE 0xb4
87 #define S3C2410_SDI_SIZE 0x44
88 #define DCON_STOP (1<<14) /* Force the transfer to stop */
89 #define S3C2410_SDI_DAT 0x3c
90 #define S3C2410_SDI_IMSK 0x40 /* Interrupt mask */
91 #define S3C2410_SDI_IMASK_ALL 0x3ffdf
94 #define S3C2410_ADC_SIZE 0x14
96 #endif /* _ARM_S3C2XX0_S3C2410REG_H_ */