2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
38 #include <sys/taskqueue.h>
39 #include <sys/timeet.h>
40 #include <sys/timepps.h>
41 #include <sys/timetc.h>
42 #include <sys/watchdog.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/intr.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <machine/bus.h>
55 #include <machine/fdt.h>
57 #include <arm/ti/ti_prcm.h>
58 #include <arm/ti/ti_scm.h>
60 #define AM335X_NUM_TIMERS 8
62 #define DMT_TIDR 0x00 /* Identification Register */
63 #define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */
64 #define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */
65 #define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */
66 #define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */
67 #define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */
68 #define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */
69 #define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */
70 #define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */
71 #define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */
72 #define DMT_IRQ_OVF (1 << 1) /* IRQ: Overflow */
73 #define DMT_IRQ_TCAR (1 << 2) /* IRQ: Capture */
74 #define DMT_IRQ_MASK (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT)
75 #define DMT_TCLR 0x38 /* Control Register */
76 #define DMT_TCLR_START (1 << 0) /* Start timer */
77 #define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */
78 #define DMT_TCLR_PRES_MASK (7 << 2) /* Prescaler mask */
79 #define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */
80 #define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */
81 #define DMT_TCLR_PWM_HIGH (1 << 7) /* PWM default output high */
82 #define DMT_TCLR_CAPTRAN_MASK (3 << 8) /* Capture transition mask */
83 #define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */
84 #define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */
85 #define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */
86 #define DMT_TCLR_CAPTRAN_BOTH (3 << 8) /* Capture both transitions */
87 #define DMT_TCLR_TRGMODE_MASK (3 << 10) /* Trigger output mode mask */
88 #define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */
89 #define DMT_TCLR_TRGMODE_OVFL (1 << 10) /* Trigger on overflow */
90 #define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */
91 #define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */
92 #define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */
93 #define DMT_TCLR_GPO_CFG (1 << 14) /* (no descr in datasheet) */
94 #define DMT_TCRR 0x3C /* Counter Register */
95 #define DMT_TLDR 0x40 /* Load Reg */
96 #define DMT_TTGR 0x44 /* Trigger Reg */
97 #define DMT_TWPS 0x48 /* Write Posted Status Reg */
98 #define DMT_TMAR 0x4C /* Match Reg */
99 #define DMT_TCAR1 0x50 /* Capture Reg */
100 #define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */
101 #define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */
102 #define DMT_TCAR2 0x48 /* Capture Reg */
105 * Use timer 2 for the eventtimer. When PPS support is not compiled in, there's
106 * no need to use a timer that has an associated capture-input pin, so use timer
107 * 3 for timecounter. When PPS is compiled in we ignore the default and use
108 * whichever of timers 4-7 have the capture pin configured.
110 #define DEFAULT_ET_TIMER 2
111 #define DEFAULT_TC_TIMER 3
113 struct am335x_dmtimer_softc {
114 struct resource * tmr_mem_res[AM335X_NUM_TIMERS];
115 struct resource * tmr_irq_res[AM335X_NUM_TIMERS];
116 uint32_t sysclk_freq;
117 uint32_t tc_num; /* Which timer number is tc. */
118 uint32_t tc_tclr; /* Cached tc TCLR register. */
119 struct resource * tc_memres; /* Resources for tc timer. */
120 uint32_t et_num; /* Which timer number is et. */
121 uint32_t et_tclr; /* Cached et TCLR register. */
122 struct resource * et_memres; /* Resources for et timer. */
123 int pps_curmode; /* Edge mode now set in hw. */
124 struct task pps_task; /* For pps_event handling. */
125 struct cdev * pps_cdev;
126 struct pps_state pps;
127 struct timecounter tc;
128 struct eventtimer et;
131 static struct am335x_dmtimer_softc *am335x_dmtimer_sc;
133 static struct resource_spec am335x_dmtimer_mem_spec[] = {
134 { SYS_RES_MEMORY, 0, RF_ACTIVE },
135 { SYS_RES_MEMORY, 1, RF_ACTIVE },
136 { SYS_RES_MEMORY, 2, RF_ACTIVE },
137 { SYS_RES_MEMORY, 3, RF_ACTIVE },
138 { SYS_RES_MEMORY, 4, RF_ACTIVE },
139 { SYS_RES_MEMORY, 5, RF_ACTIVE },
140 { SYS_RES_MEMORY, 6, RF_ACTIVE },
141 { SYS_RES_MEMORY, 7, RF_ACTIVE },
144 static struct resource_spec am335x_dmtimer_irq_spec[] = {
145 { SYS_RES_IRQ, 0, RF_ACTIVE },
146 { SYS_RES_IRQ, 1, RF_ACTIVE },
147 { SYS_RES_IRQ, 2, RF_ACTIVE },
148 { SYS_RES_IRQ, 3, RF_ACTIVE },
149 { SYS_RES_IRQ, 4, RF_ACTIVE },
150 { SYS_RES_IRQ, 5, RF_ACTIVE },
151 { SYS_RES_IRQ, 6, RF_ACTIVE },
152 { SYS_RES_IRQ, 7, RF_ACTIVE },
156 static inline uint32_t
157 am335x_dmtimer_tc_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
160 return (bus_read_4(sc->tc_memres, reg));
164 am335x_dmtimer_tc_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
168 bus_write_4(sc->tc_memres, reg, val);
171 static inline uint32_t
172 am335x_dmtimer_et_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
175 return (bus_read_4(sc->et_memres, reg));
179 am335x_dmtimer_et_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
183 bus_write_4(sc->et_memres, reg, val);
187 * PPS driver routines, included when the kernel is built with option PPS_SYNC.
189 * Note that this PPS driver does not use an interrupt. Instead it uses the
190 * hardware's ability to latch the timer's count register in response to a
191 * signal on an IO pin. Each of timers 4-7 have an associated pin, and this
192 * code allows any one of those to be used.
194 * The timecounter routines in kern_tc.c call the pps poll routine periodically
195 * to see if a new counter value has been latched. When a new value has been
196 * latched, the only processing done in the poll routine is to capture the
197 * current set of timecounter timehands (done with pps_capture()) and the
198 * latched value from the timer. The remaining work (done by pps_event()) is
199 * scheduled to be done later in a non-interrupt context.
203 #define PPS_CDEV_NAME "pps"
206 am335x_dmtimer_set_capture_mode(struct am335x_dmtimer_softc *sc, bool force_off)
213 newmode = sc->pps.ppsparam.mode & PPS_CAPTUREBOTH;
215 if (newmode == sc->pps_curmode)
218 sc->pps_curmode = newmode;
219 sc->tc_tclr &= ~DMT_TCLR_CAPTRAN_MASK;
221 case PPS_CAPTUREASSERT:
222 sc->tc_tclr |= DMT_TCLR_CAPTRAN_LOHI;
224 case PPS_CAPTURECLEAR:
225 sc->tc_tclr |= DMT_TCLR_CAPTRAN_HILO;
228 /* It can't be BOTH, so it's disabled. */
231 am335x_dmtimer_tc_write_4(sc, DMT_TCLR, sc->tc_tclr);
235 am335x_dmtimer_tc_poll_pps(struct timecounter *tc)
237 struct am335x_dmtimer_softc *sc;
242 * Note that we don't have the TCAR interrupt enabled, but the hardware
243 * still provides the status bits in the "RAW" status register even when
244 * they're masked from generating an irq. However, when clearing the
245 * TCAR status to re-arm the capture for the next second, we have to
246 * write to the IRQ status register, not the RAW register. Quirky.
248 if (am335x_dmtimer_tc_read_4(sc, DMT_IRQSTATUS_RAW) & DMT_IRQ_TCAR) {
249 pps_capture(&sc->pps);
250 sc->pps.capcount = am335x_dmtimer_tc_read_4(sc, DMT_TCAR1);
251 am335x_dmtimer_tc_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR);
252 taskqueue_enqueue_fast(taskqueue_fast, &sc->pps_task);
257 am335x_dmtimer_process_pps_event(void *arg, int pending)
259 struct am335x_dmtimer_softc *sc;
263 /* This is the task function that gets enqueued by poll_pps. Once the
264 * time has been captured in the hw interrupt context, the remaining
265 * (more expensive) work to process the event is done later in a
266 * non-fast-interrupt context.
268 * We only support capture of the rising or falling edge, not both at
269 * once; tell the kernel to process whichever mode is currently active.
271 pps_event(&sc->pps, sc->pps.ppsparam.mode & PPS_CAPTUREBOTH);
275 am335x_dmtimer_pps_open(struct cdev *dev, int flags, int fmt,
278 struct am335x_dmtimer_softc *sc;
282 /* Enable capture on open. Harmless if already open. */
283 am335x_dmtimer_set_capture_mode(sc, 0);
289 am335x_dmtimer_pps_close(struct cdev *dev, int flags, int fmt,
292 struct am335x_dmtimer_softc *sc;
297 * Disable capture on last close. Use the force-off flag to override
298 * the configured mode and turn off the hardware capture.
300 am335x_dmtimer_set_capture_mode(sc, 1);
306 am335x_dmtimer_pps_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
307 int flags, struct thread *td)
309 struct am335x_dmtimer_softc *sc;
315 * The hardware has a "capture both edges" mode, but we can't do
316 * anything useful with it in terms of PPS capture, so don't even try.
318 if ((sc->pps.ppsparam.mode & PPS_CAPTUREBOTH) == PPS_CAPTUREBOTH)
321 /* Let the kernel do the heavy lifting for ioctl. */
322 err = pps_ioctl(cmd, data, &sc->pps);
327 * The capture mode could have changed, set the hardware to whatever
328 * mode is now current. Effectively a no-op if nothing changed.
330 am335x_dmtimer_set_capture_mode(sc, 0);
335 static struct cdevsw am335x_dmtimer_pps_cdevsw = {
336 .d_version = D_VERSION,
337 .d_open = am335x_dmtimer_pps_open,
338 .d_close = am335x_dmtimer_pps_close,
339 .d_ioctl = am335x_dmtimer_pps_ioctl,
340 .d_name = PPS_CDEV_NAME,
344 * Set up the PPS cdev and the the kernel timepps stuff.
346 * Note that this routine cannot touch the hardware, because bus space resources
347 * are not fully set up yet when this is called.
350 am335x_dmtimer_pps_init(device_t dev, struct am335x_dmtimer_softc *sc)
352 int i, timer_num, unit;
353 unsigned int padstate;
360 {"GPMC_ADVn_ALE", "timer4", 4},
361 {"GPMC_BEn0_CLE", "timer5", 5},
362 {"GPMC_WEn", "timer6", 6},
363 {"GPMC_OEn_REn", "timer7", 7},
367 * Figure out which pin the user has set up for pps. We'll use the
368 * first timer that has an external caputure pin configured as input.
370 * XXX The hieroglyphic "(padstate & (0x01 << 5)))" checks that the pin
371 * is configured for input. The right symbolic values aren't exported
375 for (i = 0; i < nitems(padinfo) && timer_num == 0; ++i) {
376 if (ti_scm_padconf_get(padinfo[i].ballname, &padmux,
378 if (strcasecmp(padinfo[i].muxname, padmux) == 0 &&
379 (padstate & (0x01 << 5)))
380 timer_num = padinfo[i].timer_num;
384 if (timer_num == 0) {
385 device_printf(dev, "No DMTimer found with capture pin "
386 "configured as input; PPS driver disabled.\n");
387 return (DEFAULT_TC_TIMER);
391 * Indicate our capabilities (pretty much just capture of either edge).
392 * Have the kernel init its part of the pps_state struct and add its
395 sc->pps.ppscap = PPS_CAPTUREBOTH;
399 * Set up to capture the PPS via timecounter polling, and init the task
400 * that does deferred pps_event() processing after capture.
402 sc->tc.tc_poll_pps = am335x_dmtimer_tc_poll_pps;
403 TASK_INIT(&sc->pps_task, 0, am335x_dmtimer_process_pps_event, sc);
405 /* Create the PPS cdev. */
406 unit = device_get_unit(dev);
407 sc->pps_cdev = make_dev(&am335x_dmtimer_pps_cdevsw, unit,
408 UID_ROOT, GID_WHEEL, 0600, PPS_CDEV_NAME "%d", unit);
409 sc->pps_cdev->si_drv1 = sc;
411 device_printf(dev, "Using DMTimer%d for PPS device /dev/%s%d\n",
412 timer_num, PPS_CDEV_NAME, unit);
420 am335x_dmtimer_pps_init(device_t dev, struct am335x_dmtimer_softc *sc)
424 * When PPS support is not compiled in, there's no need to use a timer
425 * that has an associated capture-input pin, so use the default.
427 return (DEFAULT_TC_TIMER);
430 #endif /* PPS_SYNC */
432 * End of PPS driver code.
436 am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
438 struct am335x_dmtimer_softc *sc;
442 return (am335x_dmtimer_tc_read_4(sc, DMT_TCRR));
446 am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
448 struct am335x_dmtimer_softc *sc;
449 uint32_t initial_count, reload_count;
454 * Stop the timer before changing it. This routine will often be called
455 * while the timer is still running, to either lengthen or shorten the
456 * current event time. We need to ensure the timer doesn't expire while
457 * we're working with it.
459 * Also clear any pending interrupt status, because it's at least
460 * theoretically possible that we're running in a primary interrupt
461 * context now, and a timer interrupt could be pending even before we
462 * stopped the timer. The more likely case is that we're being called
463 * from the et_event_cb() routine dispatched from our own handler, but
464 * it's not clear to me that that's the only case possible.
466 sc->et_tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
467 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
468 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
471 reload_count = ((uint32_t)et->et_frequency * period) >> 32;
472 sc->et_tclr |= DMT_TCLR_AUTOLOAD;
478 initial_count = ((uint32_t)et->et_frequency * first) >> 32;
480 initial_count = reload_count;
483 * Set auto-reload and current-count values. This timer hardware counts
484 * up from the initial/reload value and interrupts on the zero rollover.
486 am335x_dmtimer_et_write_4(sc, DMT_TLDR, 0xFFFFFFFF - reload_count);
487 am335x_dmtimer_et_write_4(sc, DMT_TCRR, 0xFFFFFFFF - initial_count);
489 /* Enable overflow interrupt, and start the timer. */
490 am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_SET, DMT_IRQ_OVF);
491 sc->et_tclr |= DMT_TCLR_START;
492 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
498 am335x_dmtimer_stop(struct eventtimer *et)
500 struct am335x_dmtimer_softc *sc;
504 /* Stop timer, disable and clear interrupt. */
505 sc->et_tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
506 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
507 am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_CLR, DMT_IRQ_OVF);
508 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
513 am335x_dmtimer_intr(void *arg)
515 struct am335x_dmtimer_softc *sc;
519 /* Ack the interrupt, and invoke the callback if it's still enabled. */
520 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
521 if (sc->et.et_active)
522 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
524 return (FILTER_HANDLED);
528 am335x_dmtimer_probe(device_t dev)
531 if (!ofw_bus_status_okay(dev))
534 if (ofw_bus_is_compatible(dev, "ti,am335x-dmtimer")) {
535 device_set_desc(dev, "AM335x DMTimer");
536 return(BUS_PROBE_DEFAULT);
543 am335x_dmtimer_attach(device_t dev)
545 struct am335x_dmtimer_softc *sc;
550 * Note that if this routine returns an error status rather than running
551 * to completion it makes no attempt to clean up allocated resources;
552 * the system is essentially dead anyway without functional timers.
555 sc = device_get_softc(dev);
557 if (am335x_dmtimer_sc != NULL)
560 /* Get the base clock frequency. */
561 err = ti_prcm_clk_get_source_freq(SYS_CLK, &sc->sysclk_freq);
563 device_printf(dev, "Error: could not get sysclk frequency\n");
567 /* Request the memory resources. */
568 err = bus_alloc_resources(dev, am335x_dmtimer_mem_spec,
571 device_printf(dev, "Error: could not allocate mem resources\n");
575 /* Request the IRQ resources. */
576 err = bus_alloc_resources(dev, am335x_dmtimer_irq_spec,
579 device_printf(dev, "Error: could not allocate irq resources\n");
584 * Use the default eventtimer. Let the PPS init routine decide which
585 * timer to use for the timecounter.
587 sc->et_num = DEFAULT_ET_TIMER;
588 sc->tc_num = am335x_dmtimer_pps_init(dev, sc);
590 sc->et_memres = sc->tmr_mem_res[sc->et_num];
591 sc->tc_memres = sc->tmr_mem_res[sc->tc_num];
593 /* Enable clocks and power on the chosen devices. */
594 err = ti_prcm_clk_set_source(DMTIMER0_CLK + sc->et_num, SYSCLK_CLK);
595 err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->et_num);
596 err |= ti_prcm_clk_set_source(DMTIMER0_CLK + sc->tc_num, SYSCLK_CLK);
597 err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->tc_num);
599 device_printf(dev, "Error: could not enable timer clock\n");
603 /* Setup eventtimer interrupt handler. */
604 if (bus_setup_intr(dev, sc->tmr_irq_res[sc->et_num], INTR_TYPE_CLK,
605 am335x_dmtimer_intr, NULL, sc, &ihl) != 0) {
606 device_printf(dev, "Unable to setup the clock irq handler.\n");
610 /* Set up timecounter, start it, register it. */
611 am335x_dmtimer_tc_write_4(sc, DMT_TSICR, DMT_TSICR_RESET);
612 while (am335x_dmtimer_tc_read_4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET)
615 sc->tc_tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD;
616 am335x_dmtimer_tc_write_4(sc, DMT_TLDR, 0);
617 am335x_dmtimer_tc_write_4(sc, DMT_TCRR, 0);
618 am335x_dmtimer_tc_write_4(sc, DMT_TCLR, sc->tc_tclr);
620 sc->tc.tc_name = "AM335x Timecounter";
621 sc->tc.tc_get_timecount = am335x_dmtimer_tc_get_timecount;
622 sc->tc.tc_counter_mask = ~0u;
623 sc->tc.tc_frequency = sc->sysclk_freq;
624 sc->tc.tc_quality = 1000;
628 sc->et.et_name = "AM335x Eventtimer";
629 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
630 sc->et.et_quality = 1000;
631 sc->et.et_frequency = sc->sysclk_freq;
632 sc->et.et_min_period =
633 ((0x00000005LLU << 32) / sc->et.et_frequency);
634 sc->et.et_max_period =
635 (0xfffffffeLLU << 32) / sc->et.et_frequency;
636 sc->et.et_start = am335x_dmtimer_start;
637 sc->et.et_stop = am335x_dmtimer_stop;
639 et_register(&sc->et);
641 /* Store a pointer to the softc for use in DELAY(). */
642 am335x_dmtimer_sc = sc;
647 static device_method_t am335x_dmtimer_methods[] = {
648 DEVMETHOD(device_probe, am335x_dmtimer_probe),
649 DEVMETHOD(device_attach, am335x_dmtimer_attach),
653 static driver_t am335x_dmtimer_driver = {
655 am335x_dmtimer_methods,
656 sizeof(struct am335x_dmtimer_softc),
659 static devclass_t am335x_dmtimer_devclass;
661 DRIVER_MODULE(am335x_dmtimer, simplebus, am335x_dmtimer_driver, am335x_dmtimer_devclass, 0, 0);
662 MODULE_DEPEND(am335x_dmtimer, am335x_prcm, 1, 1, 1);
667 struct am335x_dmtimer_softc *sc;
669 uint32_t first, last;
671 sc = am335x_dmtimer_sc;
674 for (; usec > 0; usec--)
675 for (counts = 200; counts > 0; counts--)
676 /* Prevent gcc from optimizing out the loop */
681 /* Get the number of times to count */
682 counts = (usec + 1) * (sc->sysclk_freq / 1000000);
684 first = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
687 last = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
689 counts -= (int32_t)(last - first);
691 counts -= (int32_t)((0xFFFFFFFF - first) + last);