2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define CPSW_INTR_COUNT 4
35 #define CPSW_MIIBUS_RETRIES 5
36 #define CPSW_MIIBUS_DELAY 1000
38 #define CPSW_MAX_ALE_ENTRIES 1024
40 #define CPSW_SYSCTL_COUNT 34
43 uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
46 STAILQ_ENTRY(cpsw_slot) next;
48 STAILQ_HEAD(cpsw_slots, cpsw_slot);
53 struct cpsw_slots active;
54 struct cpsw_slots avail;
55 uint32_t queue_adds; /* total bufs added */
56 uint32_t queue_removes; /* total bufs removed */
57 uint32_t queue_removes_at_last_tick; /* Used by watchdog */
60 int max_active_queue_len;
62 int max_avail_queue_len;
63 int longest_chain; /* Largest # segments in a single packet. */
71 struct bintime attach_uptime; /* system uptime when attach happened. */
72 struct bintime init_uptime; /* system uptime when init happened. */
74 /* TODO: We should set up a child structure for each port;
75 store mac, phy information, etc, in that structure. */
76 uint8_t mac_addr[ETHER_ADDR_LEN];
80 /* We expect 1 memory resource and 4 interrupts from the device tree. */
81 struct resource *res[1 + CPSW_INTR_COUNT];
83 /* Interrupts get recorded here as we initialize them. */
84 /* Interrupt teardown just walks this list. */
88 const char *description;
89 } interrupts[CPSW_INTR_COUNT];
92 uint32_t cpsw_if_flags;
93 int cpsw_media_status;
98 struct callout callout;
101 bus_dma_tag_t mbuf_dtag;
103 /* An mbuf full of nulls for TX padding. */
104 bus_dmamap_t null_mbuf_dmamap;
105 struct mbuf *null_mbuf;
106 bus_addr_t null_mbuf_paddr;
108 /* RX and TX buffer tracking */
109 struct cpsw_queue rx, tx;
111 /* 64-bit versions of 32-bit hardware statistics counters */
112 uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
114 /* CPPI STATERAM has 512 slots for building TX/RX queues. */
115 /* TODO: Size here supposedly varies with different versions
116 of the controller. Check DaVinci specs and find a good
117 way to adjust this. One option is to have a separate
118 Device Tree parameter for number slots; another option
119 is to calculate it from the memory size in the device tree. */
120 struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
121 struct cpsw_slots avail;
124 #endif /*_IF_CPSWVAR_H */