2 * Copyright (c) 2012 Olivier Houchard. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 /* Define the various function IDs used by the OMAP4 */
32 #define L2CACHE_WRITE_DEBUG_REG 0x100
33 #define L2CACHE_CLEAN_INV_RANG 0x101
34 #define L2CACHE_WRITE_CTRL_REG 0x102
35 #define READ_AUX_CORE_REGS 0x103
36 #define MODIFY_AUX_CORE_0 0x104
37 #define WRITE_AUX_CORE_1 0x105
38 #define READ_WKG_CTRL_REG 0x106
39 #define CLEAR_WKG_CTRL_REG 0x107
40 #define SET_POWER_STATUS_REG 0x108
41 #define WRITE_AUXCTRL_REG 0x109
42 #define LOCKDOWN_TLB 0x10a
43 #define SELECT_TLB_ENTRY_FOR_WRITE 0x10b
44 #define READ_TLB_VA_ENTRY 0x10c
45 #define WRITE_TLB_VA_ENTRY 0x10d
46 #define READ_TLB_PA_ENTRY 0x10e
47 #define WRITE_TLB_PA_ENTRY 0x10f
48 #define READ_TLB_ATTR_ENTRY 0x110
49 #define WRITE_TLB_ATTR_ENTRY 0x111
50 #define WRITE_LATENCY_CTRL_REG 0x112
51 #define WRITE_PREFETCH_CTRL_REG 0x113
52 #endif /* OMAP4_SMC_H_ */