3 * Ben Gray <ben.r.gray@gmail.com>.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the company nor the name of the author may be used to
15 * endorse or promote products derived from this software without specific
16 * prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/resource.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
46 #include <machine/bus.h>
47 #include <machine/cpu.h>
48 #include <machine/cpufunc.h>
49 #include <machine/resource.h>
50 #include <machine/intr.h>
53 void omap4_mask_all_intr(void);
54 void omap4_post_filter_intr(void *arg);
58 bus_space_tag_t sc_iotag;
60 /* Handles for the two generic interrupt controller (GIC) register mappings */
61 bus_space_handle_t sc_gic_cpu_ioh;
62 bus_space_handle_t sc_gic_dist_ioh;
64 /* Handle for the PL310 L2 cache controller */
65 bus_space_handle_t sc_pl310_ioh;
67 /* Handle for the global and provate timer register set in the Cortex core */
68 bus_space_handle_t sc_prv_timer_ioh;
69 bus_space_handle_t sc_gbl_timer_ioh;
72 struct resource *sc_scm_mem;
76 struct omap4_intr_conf {
78 unsigned int priority;
79 unsigned int target_cpu;
82 int omap4_setup_intr_controller(device_t dev,
83 const struct omap4_intr_conf *irqs);
84 int omap4_setup_gic_cpu(unsigned int prio_mask);
86 void omap4_init_timer(device_t dev);
88 int omap4_setup_l2cache_controller(struct omap4_softc *sc);
89 void omap4_smc_call(uint32_t fn, uint32_t arg);
91 #endif /* _OMAP4VAR_H_ */