2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/limits.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/resource.h>
41 #include <sys/sysctl.h>
43 #include <machine/bus.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <arm/ti/ti_prcm.h>
50 #include <arm/ti/ti_adcreg.h>
51 #include <arm/ti/ti_adcvar.h>
53 /* Define our 7 steps, one for each input channel. */
54 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
55 { .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 },
56 { .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 },
57 { .stepconfig = ADC_STEPCFG3, .stepdelay = ADC_STEPDLY3 },
58 { .stepconfig = ADC_STEPCFG4, .stepdelay = ADC_STEPDLY4 },
59 { .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 },
60 { .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 },
61 { .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 },
64 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
67 ti_adc_enable(struct ti_adc_softc *sc)
70 TI_ADC_LOCK_ASSERT(sc);
72 if (sc->sc_last_state == 1)
75 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
76 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
77 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
79 /* Enable the ADC. Run thru enabled steps, start the conversions. */
80 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) | ADC_CTRL_ENABLE);
82 sc->sc_last_state = 1;
86 ti_adc_disable(struct ti_adc_softc *sc)
91 TI_ADC_LOCK_ASSERT(sc);
93 if (sc->sc_last_state == 0)
96 /* Disable all the enabled steps. */
97 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
99 /* Disable the ADC. */
100 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
102 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
103 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
104 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ);
106 /* ACK any pending interrupt. */
107 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
109 /* Drain the FIFO data. */
110 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
112 data = ADC_READ4(sc, ADC_FIFO0DATA);
113 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
116 sc->sc_last_state = 0;
120 ti_adc_setup(struct ti_adc_softc *sc)
125 TI_ADC_LOCK_ASSERT(sc);
127 /* Check for enabled inputs. */
129 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
130 if (ti_adc_inputs[ain].enable)
131 enabled |= (1U << (ain + 1));
134 /* Set the ADC global status. */
137 /* Update the enabled steps. */
138 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
139 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
147 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
149 struct ti_adc_input *input;
152 TI_ADC_LOCK_ASSERT(sc);
154 input = &ti_adc_inputs[ain];
155 reg = input->stepconfig;
156 val = ADC_READ4(sc, reg);
158 /* Set single ended operation. */
159 val &= ~ADC_STEP_DIFF_CNTRL;
161 /* Set the negative voltage reference. */
162 val &= ~ADC_STEP_RFM_MSK;
163 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT;
165 /* Set the positive voltage reference. */
166 val &= ~ADC_STEP_RFP_MSK;
167 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT;
169 /* Set the samples average. */
170 val &= ~ADC_STEP_AVG_MSK;
171 val |= input->samples << ADC_STEP_AVG_SHIFT;
173 /* Select the desired input. */
174 val &= ~ADC_STEP_INP_MSK;
175 val |= ain << ADC_STEP_INP_SHIFT;
177 /* Set the ADC to one-shot mode. */
178 val &= ~ADC_STEP_MODE_MSK;
180 ADC_WRITE4(sc, reg, val);
184 ti_adc_reset(struct ti_adc_softc *sc)
188 TI_ADC_LOCK_ASSERT(sc);
190 /* Disable all the inputs. */
191 for (ain = 0; ain < TI_ADC_NPINS; ain++)
192 ti_adc_inputs[ain].enable = 0;
196 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
199 struct ti_adc_softc *sc;
201 sc = (struct ti_adc_softc *)arg1;
204 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
207 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
208 if (error != 0 || req->newptr == NULL)
212 * The actual written value is the prescaler setting - 1.
213 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
214 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
223 /* Disable the ADC. */
225 /* Update the ADC prescaler setting. */
226 ADC_WRITE4(sc, ADC_CLKDIV, reg);
227 /* Enable the ADC again. */
235 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
239 struct ti_adc_softc *sc;
240 struct ti_adc_input *input;
242 input = (struct ti_adc_input *)arg1;
245 enable = input->enable;
246 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
248 if (error != 0 || req->newptr == NULL)
255 /* Setup the ADC as needed. */
256 if (input->enable != enable) {
257 input->enable = enable;
259 if (input->enable == 0)
268 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
271 struct ti_adc_softc *sc;
272 struct ti_adc_input *input;
274 input = (struct ti_adc_input *)arg1;
278 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
281 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
282 if (error != 0 || req->newptr == NULL)
289 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
296 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
298 int error, samples, i;
299 struct ti_adc_softc *sc;
300 struct ti_adc_input *input;
302 input = (struct ti_adc_input *)arg1;
305 if (input->samples > nitems(ti_adc_samples))
306 input->samples = nitems(ti_adc_samples);
307 samples = ti_adc_samples[input->samples];
309 error = sysctl_handle_int(oidp, &samples, 0, req);
310 if (error != 0 || req->newptr == NULL)
314 if (samples != ti_adc_samples[input->samples]) {
316 for (i = 0; i < nitems(ti_adc_samples); i++)
317 if (samples >= ti_adc_samples[i])
319 ti_adc_input_setup(sc, input->input);
327 ti_adc_read_data(struct ti_adc_softc *sc)
330 struct ti_adc_input *input;
333 TI_ADC_LOCK_ASSERT(sc);
335 /* Read the available data. */
336 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
338 data = ADC_READ4(sc, ADC_FIFO0DATA);
339 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
340 input = &ti_adc_inputs[ain];
341 if (input->enable == 0)
344 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
345 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
350 ti_adc_intr(void *arg)
352 struct ti_adc_softc *sc;
355 sc = (struct ti_adc_softc *)arg;
357 status = ADC_READ4(sc, ADC_IRQSTATUS);
360 if (status & ~(ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ))
361 device_printf(sc->sc_dev, "stray interrupt: %#x\n", status);
364 /* ACK the interrupt. */
365 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
367 /* Read the available data. */
368 if (status & ADC_IRQ_FIFO0_THRES)
369 ti_adc_read_data(sc);
371 /* Start the next conversion ? */
372 if (status & ADC_IRQ_END_OF_SEQ)
378 ti_adc_sysctl_init(struct ti_adc_softc *sc)
381 struct sysctl_ctx_list *ctx;
382 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
383 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
387 * Add per-pin sysctl tree/handlers.
389 ctx = device_get_sysctl_ctx(sc->sc_dev);
390 tree_node = device_get_sysctl_tree(sc->sc_dev);
391 tree = SYSCTL_CHILDREN(tree_node);
392 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
393 CTLFLAG_RW | CTLTYPE_UINT, sc, 0,
394 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
395 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
396 CTLFLAG_RD, NULL, "ADC inputs");
397 inp_tree = SYSCTL_CHILDREN(inp_node);
399 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
401 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
402 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
403 CTLFLAG_RD, NULL, "ADC input");
404 inpN_tree = SYSCTL_CHILDREN(inpN_node);
406 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
407 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
408 ti_adc_enable_proc, "IU", "Enable ADC input");
409 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
410 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
411 ti_adc_open_delay_proc, "IU", "ADC open delay");
412 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
413 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0,
414 ti_adc_samples_avg_proc, "IU", "ADC samples average");
415 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
416 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
417 "Converted raw value for the ADC input");
422 ti_adc_inputs_init(struct ti_adc_softc *sc)
425 struct ti_adc_input *input;
428 for (ain = 0; ain < TI_ADC_NPINS; ain++) {
429 input = &ti_adc_inputs[ain];
435 ti_adc_input_setup(sc, ain);
441 ti_adc_idlestep_init(struct ti_adc_softc *sc)
445 val = ADC_READ4(sc, ADC_IDLECONFIG);
447 /* Set single ended operation. */
448 val &= ~ADC_STEP_DIFF_CNTRL;
450 /* Set the negative voltage reference. */
451 val &= ~ADC_STEP_RFM_MSK;
452 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT;
454 /* Set the positive voltage reference. */
455 val &= ~ADC_STEP_RFP_MSK;
456 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT;
458 /* Connect the input to VREFN. */
459 val &= ~ADC_STEP_INP_MSK;
460 val |= ADC_STEP_IN_VREFN << ADC_STEP_INP_SHIFT;
462 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
466 ti_adc_probe(device_t dev)
469 if (!ofw_bus_is_compatible(dev, "ti,adc"))
471 device_set_desc(dev, "TI ADC controller");
473 return (BUS_PROBE_DEFAULT);
477 ti_adc_attach(device_t dev)
480 struct ti_adc_softc *sc;
483 sc = device_get_softc(dev);
487 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
489 if (!sc->sc_mem_res) {
490 device_printf(dev, "cannot allocate memory window\n");
495 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
497 if (!sc->sc_irq_res) {
498 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
499 device_printf(dev, "cannot allocate interrupt\n");
503 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
504 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
505 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
506 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
507 device_printf(dev, "Unable to setup the irq handler.\n");
511 /* Activate the ADC_TSC module. */
512 err = ti_prcm_clk_enable(TSC_ADC_CLK);
516 /* Check the ADC revision. */
517 rev = ADC_READ4(sc, ADC_REVISION);
519 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
520 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
521 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
522 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
523 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
524 rev & ADC_REV_MINOR_MSK,
525 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
528 * Disable the step write protect and make it store the step ID for
529 * the captured data on FIFO.
531 reg = ADC_READ4(sc, ADC_CTRL);
532 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
535 * Set the ADC prescaler to 2400 (yes, the actual value written here
537 * This sets the ADC clock to ~10Khz (CLK_M_OSC / 2400).
539 ADC_WRITE4(sc, ADC_CLKDIV, 2399);
541 TI_ADC_LOCK_INIT(sc);
543 ti_adc_idlestep_init(sc);
544 ti_adc_inputs_init(sc);
545 ti_adc_sysctl_init(sc);
551 ti_adc_detach(device_t dev)
553 struct ti_adc_softc *sc;
555 sc = device_get_softc(dev);
557 /* Turn off the ADC. */
563 TI_ADC_LOCK_DESTROY(sc);
566 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
570 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
572 return (bus_generic_detach(dev));
575 static device_method_t ti_adc_methods[] = {
576 DEVMETHOD(device_probe, ti_adc_probe),
577 DEVMETHOD(device_attach, ti_adc_attach),
578 DEVMETHOD(device_detach, ti_adc_detach),
583 static driver_t ti_adc_driver = {
586 sizeof(struct ti_adc_softc),
589 static devclass_t ti_adc_devclass;
591 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0);
592 MODULE_VERSION(ti_adc, 1);
593 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);