2 * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
31 /* TI WDT registers */
32 #define TI_WDT_WIDR 0x00 /* Watchdog Identification Register */
33 #define TI_WDT_WDSC 0x10 /* Watchdog System Control Register */
34 #define TI_WDT_WDST 0x14 /* Watchdog Status Register */
35 #define TI_WDT_WISR 0x18 /* Watchdog Interrupt Status Register */
36 #define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */
37 #define TI_WDT_WCLR 0x24 /* Watchdog Control Register */
38 #define TI_WDT_WCRR 0x28 /* Watchdog Counter Register */
39 #define TI_WDT_WLDR 0x2c /* Watchdog Load Register */
40 #define TI_WDT_WTGR 0x30 /* Watchdog Trigger Register */
41 #define TI_WDT_WWPS 0x34 /* Watchdog Write Posting Register */
42 #define TI_WDT_WDLY 0x44 /* Watchdog Delay Configuration Reg */
43 #define TI_WDT_WSPR 0x48 /* Watchdog Start/Stop Register */
44 #define TI_WDT_WIRQSTATRAW 0x54 /* Watchdog Raw Interrupt Status Reg. */
45 #define TI_WDT_WIRQSTAT 0x58 /* Watchdog Int. Status Register */
46 #define TI_WDT_WIRQENSET 0x5c /* Watchdog Int. Enable Set Register */
47 #define TI_WDT_WIRQENCLR 0x60 /* Watchdog Int. Enable Clear Reg. */
49 /* WDT_WDSC Register */
50 #define TI_WDSC_SR (1 << 1) /* Soft reset */
55 * Writes to some registers require synchronisation with a different clock
56 * domain. The WDT_WWPS register is the place where this synchronisation
59 #define TI_W_PEND_WCLR (1 << 0)
60 #define TI_W_PEND_WCRR (1 << 1)
61 #define TI_W_PEND_WLDR (1 << 2)
62 #define TI_W_PEND_WTGR (1 << 3)
63 #define TI_W_PEND_WSPR (1 << 4)
64 #define TI_W_PEND_WDLY (1 << 5)
66 /* WDT_WIRQENSET Register */
67 #define TI_IRQ_EN_OVF (1 << 0) /* Overflow interrupt */
68 #define TI_IRQ_EN_DLY (1 << 1) /* Delay interrupt */
70 /* WDT_WIRQSTAT Register */
71 #define TI_IRQ_EV_OVF (1 << 0) /* Overflow event */
72 #define TI_IRQ_EV_DLY (1 << 1) /* Delay event */
74 #endif /* _TI_WDT_H_ */